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Linux kernel mirror (for testing)
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1/*
2 * arch/arm/include/asm/io.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21#ifndef __ASM_ARM_IO_H
22#define __ASM_ARM_IO_H
23
24#ifdef __KERNEL__
25
26#include <linux/types.h>
27#include <asm/byteorder.h>
28#include <asm/memory.h>
29#include <asm/system.h>
30
31/*
32 * ISA I/O bus memory addresses are 1:1 with the physical address.
33 */
34#define isa_virt_to_bus virt_to_phys
35#define isa_page_to_bus page_to_phys
36#define isa_bus_to_virt phys_to_virt
37
38/*
39 * Generic IO read/write. These perform native-endian accesses. Note
40 * that some architectures will want to re-define __raw_{read,write}w.
41 */
42extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
43extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
44extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
45
46extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
47extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
48extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
49
50#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
51#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
52#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
53
54#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
55#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
56#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
57
58/*
59 * Architecture ioremap implementation.
60 */
61#define MT_DEVICE 0
62#define MT_DEVICE_NONSHARED 1
63#define MT_DEVICE_CACHED 2
64#define MT_DEVICE_WC 3
65/*
66 * types 4 onwards can be found in asm/mach/map.h and are undefined
67 * for ioremap
68 */
69
70/*
71 * __arm_ioremap takes CPU physical address.
72 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
73 * The _caller variety takes a __builtin_return_address(0) value for
74 * /proc/vmalloc to use - and should only be used in non-inline functions.
75 */
76extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
77 size_t, unsigned int, void *);
78extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
79 void *);
80
81extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
82extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
83extern void __iounmap(volatile void __iomem *addr);
84
85/*
86 * Bad read/write accesses...
87 */
88extern void __readwrite_bug(const char *fn);
89
90/*
91 * A typesafe __io() helper
92 */
93static inline void __iomem *__typesafe_io(unsigned long addr)
94{
95 return (void __iomem *)addr;
96}
97
98/* IO barriers */
99#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
100#define __iormb() rmb()
101#define __iowmb() wmb()
102#else
103#define __iormb() do { } while (0)
104#define __iowmb() do { } while (0)
105#endif
106
107/*
108 * Now, pick up the machine-defined IO definitions
109 */
110#include <mach/io.h>
111
112/*
113 * IO port access primitives
114 * -------------------------
115 *
116 * The ARM doesn't have special IO access instructions; all IO is memory
117 * mapped. Note that these are defined to perform little endian accesses
118 * only. Their primary purpose is to access PCI and ISA peripherals.
119 *
120 * Note that for a big endian machine, this implies that the following
121 * big endian mode connectivity is in place, as described by numerous
122 * ARM documents:
123 *
124 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
125 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
126 *
127 * The machine specific io.h include defines __io to translate an "IO"
128 * address to a memory address.
129 *
130 * Note that we prevent GCC re-ordering or caching values in expressions
131 * by introducing sequence points into the in*() definitions. Note that
132 * __raw_* do not guarantee this behaviour.
133 *
134 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
135 */
136#ifdef __io
137#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
138#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
139 cpu_to_le16(v),__io(p)); })
140#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
141 cpu_to_le32(v),__io(p)); })
142
143#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
144#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
145 __raw_readw(__io(p))); __iormb(); __v; })
146#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
147 __raw_readl(__io(p))); __iormb(); __v; })
148
149#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
150#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
151#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
152
153#define insb(p,d,l) __raw_readsb(__io(p),d,l)
154#define insw(p,d,l) __raw_readsw(__io(p),d,l)
155#define insl(p,d,l) __raw_readsl(__io(p),d,l)
156#endif
157
158#define outb_p(val,port) outb((val),(port))
159#define outw_p(val,port) outw((val),(port))
160#define outl_p(val,port) outl((val),(port))
161#define inb_p(port) inb((port))
162#define inw_p(port) inw((port))
163#define inl_p(port) inl((port))
164
165#define outsb_p(port,from,len) outsb(port,from,len)
166#define outsw_p(port,from,len) outsw(port,from,len)
167#define outsl_p(port,from,len) outsl(port,from,len)
168#define insb_p(port,to,len) insb(port,to,len)
169#define insw_p(port,to,len) insw(port,to,len)
170#define insl_p(port,to,len) insl(port,to,len)
171
172/*
173 * String version of IO memory access ops:
174 */
175extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
176extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
177extern void _memset_io(volatile void __iomem *, int, size_t);
178
179#define mmiowb()
180
181/*
182 * Memory access primitives
183 * ------------------------
184 *
185 * These perform PCI memory accesses via an ioremap region. They don't
186 * take an address as such, but a cookie.
187 *
188 * Again, this are defined to perform little endian accesses. See the
189 * IO port primitives for more information.
190 */
191#ifdef __mem_pci
192#define readb_relaxed(c) ({ u8 __v = __raw_readb(__mem_pci(c)); __v; })
193#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
194 __raw_readw(__mem_pci(c))); __v; })
195#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
196 __raw_readl(__mem_pci(c))); __v; })
197
198#define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c)))
199#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
200 cpu_to_le16(v),__mem_pci(c)))
201#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
202 cpu_to_le32(v),__mem_pci(c)))
203
204#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
205#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
206#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
207
208#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
209#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
210#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
211
212#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
213#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
214#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
215
216#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
217#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
218#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
219
220#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
221#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
222#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
223
224#elif !defined(readb)
225
226#define readb(c) (__readwrite_bug("readb"),0)
227#define readw(c) (__readwrite_bug("readw"),0)
228#define readl(c) (__readwrite_bug("readl"),0)
229#define writeb(v,c) __readwrite_bug("writeb")
230#define writew(v,c) __readwrite_bug("writew")
231#define writel(v,c) __readwrite_bug("writel")
232
233#define check_signature(io,sig,len) (0)
234
235#endif /* __mem_pci */
236
237/*
238 * ioremap and friends.
239 *
240 * ioremap takes a PCI memory address, as specified in
241 * Documentation/IO-mapping.txt.
242 *
243 */
244#ifndef __arch_ioremap
245#define __arch_ioremap __arm_ioremap
246#define __arch_iounmap __iounmap
247#endif
248
249#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
250#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
251#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
252#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
253#define iounmap __arch_iounmap
254
255/*
256 * io{read,write}{8,16,32} macros
257 */
258#ifndef ioread8
259#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
260#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
261#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
262
263#define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); })
264#define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
265#define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
266
267#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
268#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
269#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
270
271#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
272#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
273#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
274
275extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
276extern void ioport_unmap(void __iomem *addr);
277#endif
278
279struct pci_dev;
280
281extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
282extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
283
284/*
285 * can the hardware map this into one segment or not, given no other
286 * constraints.
287 */
288#define BIOVEC_MERGEABLE(vec1, vec2) \
289 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
290
291#ifdef CONFIG_MMU
292#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
293extern int valid_phys_addr_range(unsigned long addr, size_t size);
294extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
295extern int devmem_is_allowed(unsigned long pfn);
296#endif
297
298/*
299 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
300 * access
301 */
302#define xlate_dev_mem_ptr(p) __va(p)
303
304/*
305 * Convert a virtual cached pointer to an uncached pointer
306 */
307#define xlate_dev_kmem_ptr(p) p
308
309/*
310 * Register ISA memory and port locations for glibc iopl/inb/outb
311 * emulation.
312 */
313extern void register_isa_ports(unsigned int mmio, unsigned int io,
314 unsigned int io_shift);
315
316#endif /* __KERNEL__ */
317#endif /* __ASM_ARM_IO_H */