tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#include <linux/slab.h>
27#include "netxen_nic.h"
28#include "netxen_nic_hw.h"
29
30#include <net/ip.h>
31
32#define MASK(n) ((1ULL<<(n))-1)
33#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
34#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
35#define MS_WIN(addr) (addr & 0x0ffc0000)
36
37#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38
39#define CRB_BLK(off) ((off >> 20) & 0x3f)
40#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41#define CRB_WINDOW_2M (0x130060)
42#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43#define CRB_INDIRECT_2M (0x1e0000UL)
44
45static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
48 void __iomem *addr);
49
50#ifndef readq
51static inline u64 readq(void __iomem *addr)
52{
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54}
55#endif
56
57#ifndef writeq
58static inline void writeq(u64 val, void __iomem *addr)
59{
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62}
63#endif
64
65#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
66 ((adapter)->ahw.pci_base0 + (off))
67#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
69#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
71
72static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
73 unsigned long off)
74{
75 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
76 return PCI_OFFSET_FIRST_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
79 return PCI_OFFSET_SECOND_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
82 return PCI_OFFSET_THIRD_RANGE(adapter, off);
83
84 return NULL;
85}
86
87static crb_128M_2M_block_map_t
88crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
89 {{{0, 0, 0, 0} } }, /* 0: PCI */
90 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
91 {1, 0x0110000, 0x0120000, 0x130000},
92 {1, 0x0120000, 0x0122000, 0x124000},
93 {1, 0x0130000, 0x0132000, 0x126000},
94 {1, 0x0140000, 0x0142000, 0x128000},
95 {1, 0x0150000, 0x0152000, 0x12a000},
96 {1, 0x0160000, 0x0170000, 0x110000},
97 {1, 0x0170000, 0x0172000, 0x12e000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {1, 0x01e0000, 0x01e0800, 0x122000},
105 {0, 0x0000000, 0x0000000, 0x000000} } },
106 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
107 {{{0, 0, 0, 0} } }, /* 3: */
108 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
109 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
110 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
111 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
112 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x08f0000, 0x08f2000, 0x172000} } },
128 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x09f0000, 0x09f2000, 0x176000} } },
144 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
160 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
176 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
177 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
178 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
179 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
180 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
181 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
182 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
183 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
184 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
185 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
186 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
187 {{{0, 0, 0, 0} } }, /* 23: */
188 {{{0, 0, 0, 0} } }, /* 24: */
189 {{{0, 0, 0, 0} } }, /* 25: */
190 {{{0, 0, 0, 0} } }, /* 26: */
191 {{{0, 0, 0, 0} } }, /* 27: */
192 {{{0, 0, 0, 0} } }, /* 28: */
193 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
194 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
195 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
196 {{{0} } }, /* 32: PCI */
197 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
198 {1, 0x2110000, 0x2120000, 0x130000},
199 {1, 0x2120000, 0x2122000, 0x124000},
200 {1, 0x2130000, 0x2132000, 0x126000},
201 {1, 0x2140000, 0x2142000, 0x128000},
202 {1, 0x2150000, 0x2152000, 0x12a000},
203 {1, 0x2160000, 0x2170000, 0x110000},
204 {1, 0x2170000, 0x2172000, 0x12e000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000} } },
213 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
214 {{{0} } }, /* 35: */
215 {{{0} } }, /* 36: */
216 {{{0} } }, /* 37: */
217 {{{0} } }, /* 38: */
218 {{{0} } }, /* 39: */
219 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
220 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
221 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
222 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
223 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
224 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
225 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
226 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
227 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
228 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
229 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
230 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
231 {{{0} } }, /* 52: */
232 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
233 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
234 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
235 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
236 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
237 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
238 {{{0} } }, /* 59: I2C0 */
239 {{{0} } }, /* 60: I2C1 */
240 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
241 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
242 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
243};
244
245/*
246 * top 12 bits of crb internal address (hub, agent)
247 */
248static unsigned crb_hub_agt[64] =
249{
250 0,
251 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
252 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
253 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
254 0,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
256 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
257 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
263 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
264 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
279 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
280 0,
281 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
282 0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
284 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
285 0,
286 0,
287 0,
288 0,
289 0,
290 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
299 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
300 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
301 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
302 0,
303 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
304 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
306 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
307 0,
308 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
309 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
311 0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
313 0,
314};
315
316/* PCI Windowing for DDR regions. */
317
318#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
319
320#define NETXEN_PCIE_SEM_TIMEOUT 10000
321
322static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
323
324int
325netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
326{
327 int done = 0, timeout = 0;
328
329 while (!done) {
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
331 if (done == 1)
332 break;
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
334 return -EIO;
335 msleep(1);
336 }
337
338 if (id_reg)
339 NXWR32(adapter, id_reg, adapter->portnum);
340
341 return 0;
342}
343
344void
345netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
346{
347 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
348}
349
350static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
351{
352 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
353 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
355 }
356
357 return 0;
358}
359
360/* Disable an XG interface */
361static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
362{
363 __u32 mac_cfg;
364 u32 port = adapter->physical_port;
365
366 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
367 return 0;
368
369 if (port > NETXEN_NIU_MAX_XG_PORTS)
370 return -EINVAL;
371
372 mac_cfg = 0;
373 if (NXWR32(adapter,
374 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
375 return -EIO;
376 return 0;
377}
378
379#define NETXEN_UNICAST_ADDR(port, index) \
380 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
381#define NETXEN_MCAST_ADDR(port, index) \
382 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
383#define MAC_HI(addr) \
384 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
385#define MAC_LO(addr) \
386 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
387
388static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
389{
390 u32 mac_cfg;
391 u32 cnt = 0;
392 __u32 reg = 0x0200;
393 u32 port = adapter->physical_port;
394 u16 board_type = adapter->ahw.board_type;
395
396 if (port > NETXEN_NIU_MAX_XG_PORTS)
397 return -EINVAL;
398
399 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
400 mac_cfg &= ~0x4;
401 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
402
403 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
404 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
405 reg = (0x20 << port);
406
407 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
408
409 mdelay(10);
410
411 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
412 mdelay(10);
413
414 if (cnt < 20) {
415
416 reg = NXRD32(adapter,
417 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
418
419 if (mode == NETXEN_NIU_PROMISC_MODE)
420 reg = (reg | 0x2000UL);
421 else
422 reg = (reg & ~0x2000UL);
423
424 if (mode == NETXEN_NIU_ALLMULTI_MODE)
425 reg = (reg | 0x1000UL);
426 else
427 reg = (reg & ~0x1000UL);
428
429 NXWR32(adapter,
430 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
431 }
432
433 mac_cfg |= 0x4;
434 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
435
436 return 0;
437}
438
439static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
440{
441 u32 mac_hi, mac_lo;
442 u32 reg_hi, reg_lo;
443
444 u8 phy = adapter->physical_port;
445
446 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
447 return -EINVAL;
448
449 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
450 mac_hi = addr[2] | ((u32)addr[3] << 8) |
451 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
452
453 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
454 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
455
456 /* write twice to flush */
457 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
458 return -EIO;
459 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
460 return -EIO;
461
462 return 0;
463}
464
465static int
466netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
467{
468 u32 val = 0;
469 u16 port = adapter->physical_port;
470 u8 *addr = adapter->mac_addr;
471
472 if (adapter->mc_enabled)
473 return 0;
474
475 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
476 val |= (1UL << (28+port));
477 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
478
479 /* add broadcast addr to filter */
480 val = 0xffffff;
481 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
483
484 /* add station addr to filter */
485 val = MAC_HI(addr);
486 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
487 val = MAC_LO(addr);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
489
490 adapter->mc_enabled = 1;
491 return 0;
492}
493
494static int
495netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
496{
497 u32 val = 0;
498 u16 port = adapter->physical_port;
499 u8 *addr = adapter->mac_addr;
500
501 if (!adapter->mc_enabled)
502 return 0;
503
504 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
505 val &= ~(1UL << (28+port));
506 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
507
508 val = MAC_HI(addr);
509 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
510 val = MAC_LO(addr);
511 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
512
513 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
514 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
515
516 adapter->mc_enabled = 0;
517 return 0;
518}
519
520static int
521netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
522 int index, u8 *addr)
523{
524 u32 hi = 0, lo = 0;
525 u16 port = adapter->physical_port;
526
527 lo = MAC_LO(addr);
528 hi = MAC_HI(addr);
529
530 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
531 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
532
533 return 0;
534}
535
536static void netxen_p2_nic_set_multi(struct net_device *netdev)
537{
538 struct netxen_adapter *adapter = netdev_priv(netdev);
539 struct netdev_hw_addr *ha;
540 u8 null_addr[6];
541 int i;
542
543 memset(null_addr, 0, 6);
544
545 if (netdev->flags & IFF_PROMISC) {
546
547 adapter->set_promisc(adapter,
548 NETXEN_NIU_PROMISC_MODE);
549
550 /* Full promiscuous mode */
551 netxen_nic_disable_mcast_filter(adapter);
552
553 return;
554 }
555
556 if (netdev_mc_empty(netdev)) {
557 adapter->set_promisc(adapter,
558 NETXEN_NIU_NON_PROMISC_MODE);
559 netxen_nic_disable_mcast_filter(adapter);
560 return;
561 }
562
563 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
564 if (netdev->flags & IFF_ALLMULTI ||
565 netdev_mc_count(netdev) > adapter->max_mc_count) {
566 netxen_nic_disable_mcast_filter(adapter);
567 return;
568 }
569
570 netxen_nic_enable_mcast_filter(adapter);
571
572 i = 0;
573 netdev_for_each_mc_addr(ha, netdev)
574 netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
575
576 /* Clear out remaining addresses */
577 while (i < adapter->max_mc_count)
578 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
579}
580
581static int
582netxen_send_cmd_descs(struct netxen_adapter *adapter,
583 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
584{
585 u32 i, producer, consumer;
586 struct netxen_cmd_buffer *pbuf;
587 struct cmd_desc_type0 *cmd_desc;
588 struct nx_host_tx_ring *tx_ring;
589
590 i = 0;
591
592 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
593 return -EIO;
594
595 tx_ring = adapter->tx_ring;
596 __netif_tx_lock_bh(tx_ring->txq);
597
598 producer = tx_ring->producer;
599 consumer = tx_ring->sw_consumer;
600
601 if (nr_desc >= netxen_tx_avail(tx_ring)) {
602 netif_tx_stop_queue(tx_ring->txq);
603 smp_mb();
604 if (netxen_tx_avail(tx_ring) > nr_desc) {
605 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
606 netif_tx_wake_queue(tx_ring->txq);
607 } else {
608 __netif_tx_unlock_bh(tx_ring->txq);
609 return -EBUSY;
610 }
611 }
612
613 do {
614 cmd_desc = &cmd_desc_arr[i];
615
616 pbuf = &tx_ring->cmd_buf_arr[producer];
617 pbuf->skb = NULL;
618 pbuf->frag_count = 0;
619
620 memcpy(&tx_ring->desc_head[producer],
621 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
622
623 producer = get_next_index(producer, tx_ring->num_desc);
624 i++;
625
626 } while (i != nr_desc);
627
628 tx_ring->producer = producer;
629
630 netxen_nic_update_cmd_producer(adapter, tx_ring);
631
632 __netif_tx_unlock_bh(tx_ring->txq);
633
634 return 0;
635}
636
637static int
638nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
639{
640 nx_nic_req_t req;
641 nx_mac_req_t *mac_req;
642 u64 word;
643
644 memset(&req, 0, sizeof(nx_nic_req_t));
645 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
646
647 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
648 req.req_hdr = cpu_to_le64(word);
649
650 mac_req = (nx_mac_req_t *)&req.words[0];
651 mac_req->op = op;
652 memcpy(mac_req->mac_addr, addr, 6);
653
654 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
655}
656
657static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
658 const u8 *addr, struct list_head *del_list)
659{
660 struct list_head *head;
661 nx_mac_list_t *cur;
662
663 /* look up if already exists */
664 list_for_each(head, del_list) {
665 cur = list_entry(head, nx_mac_list_t, list);
666
667 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
668 list_move_tail(head, &adapter->mac_list);
669 return 0;
670 }
671 }
672
673 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
674 if (cur == NULL) {
675 printk(KERN_ERR "%s: failed to add mac address filter\n",
676 adapter->netdev->name);
677 return -ENOMEM;
678 }
679 memcpy(cur->mac_addr, addr, ETH_ALEN);
680 list_add_tail(&cur->list, &adapter->mac_list);
681 return nx_p3_sre_macaddr_change(adapter,
682 cur->mac_addr, NETXEN_MAC_ADD);
683}
684
685static void netxen_p3_nic_set_multi(struct net_device *netdev)
686{
687 struct netxen_adapter *adapter = netdev_priv(netdev);
688 struct netdev_hw_addr *ha;
689 static const u8 bcast_addr[ETH_ALEN] = {
690 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
691 };
692 u32 mode = VPORT_MISS_MODE_DROP;
693 LIST_HEAD(del_list);
694 struct list_head *head;
695 nx_mac_list_t *cur;
696
697 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
698 return;
699
700 list_splice_tail_init(&adapter->mac_list, &del_list);
701
702 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
703 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
704
705 if (netdev->flags & IFF_PROMISC) {
706 mode = VPORT_MISS_MODE_ACCEPT_ALL;
707 goto send_fw_cmd;
708 }
709
710 if ((netdev->flags & IFF_ALLMULTI) ||
711 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
712 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
713 goto send_fw_cmd;
714 }
715
716 if (!netdev_mc_empty(netdev)) {
717 netdev_for_each_mc_addr(ha, netdev)
718 nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
719 }
720
721send_fw_cmd:
722 adapter->set_promisc(adapter, mode);
723 head = &del_list;
724 while (!list_empty(head)) {
725 cur = list_entry(head->next, nx_mac_list_t, list);
726
727 nx_p3_sre_macaddr_change(adapter,
728 cur->mac_addr, NETXEN_MAC_DEL);
729 list_del(&cur->list);
730 kfree(cur);
731 }
732}
733
734static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
735{
736 nx_nic_req_t req;
737 u64 word;
738
739 memset(&req, 0, sizeof(nx_nic_req_t));
740
741 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
742
743 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
744 ((u64)adapter->portnum << 16);
745 req.req_hdr = cpu_to_le64(word);
746
747 req.words[0] = cpu_to_le64(mode);
748
749 return netxen_send_cmd_descs(adapter,
750 (struct cmd_desc_type0 *)&req, 1);
751}
752
753void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
754{
755 nx_mac_list_t *cur;
756 struct list_head *head = &adapter->mac_list;
757
758 while (!list_empty(head)) {
759 cur = list_entry(head->next, nx_mac_list_t, list);
760 nx_p3_sre_macaddr_change(adapter,
761 cur->mac_addr, NETXEN_MAC_DEL);
762 list_del(&cur->list);
763 kfree(cur);
764 }
765}
766
767static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
768{
769 /* assuming caller has already copied new addr to netdev */
770 netxen_p3_nic_set_multi(adapter->netdev);
771 return 0;
772}
773
774#define NETXEN_CONFIG_INTR_COALESCE 3
775
776/*
777 * Send the interrupt coalescing parameter set by ethtool to the card.
778 */
779int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
780{
781 nx_nic_req_t req;
782 u64 word[6];
783 int rv, i;
784
785 memset(&req, 0, sizeof(nx_nic_req_t));
786 memset(word, 0, sizeof(word));
787
788 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
789
790 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
791 req.req_hdr = cpu_to_le64(word[0]);
792
793 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
794 for (i = 0; i < 6; i++)
795 req.words[i] = cpu_to_le64(word[i]);
796
797 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
798 if (rv != 0) {
799 printk(KERN_ERR "ERROR. Could not send "
800 "interrupt coalescing parameters\n");
801 }
802
803 return rv;
804}
805
806int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
807{
808 nx_nic_req_t req;
809 u64 word;
810 int rv = 0;
811
812 memset(&req, 0, sizeof(nx_nic_req_t));
813
814 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
815
816 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
817 req.req_hdr = cpu_to_le64(word);
818
819 req.words[0] = cpu_to_le64(enable);
820
821 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
822 if (rv != 0) {
823 printk(KERN_ERR "ERROR. Could not send "
824 "configure hw lro request\n");
825 }
826
827 return rv;
828}
829
830int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
831{
832 nx_nic_req_t req;
833 u64 word;
834 int rv = 0;
835
836 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
837 return rv;
838
839 memset(&req, 0, sizeof(nx_nic_req_t));
840
841 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
842
843 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
844 ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
846
847 req.words[0] = cpu_to_le64(enable);
848
849 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
850 if (rv != 0) {
851 printk(KERN_ERR "ERROR. Could not send "
852 "configure bridge mode request\n");
853 }
854
855 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
856
857 return rv;
858}
859
860
861#define RSS_HASHTYPE_IP_TCP 0x3
862
863int netxen_config_rss(struct netxen_adapter *adapter, int enable)
864{
865 nx_nic_req_t req;
866 u64 word;
867 int i, rv;
868
869 static const u64 key[] = {
870 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
871 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
872 0x255b0ec26d5a56daULL
873 };
874
875
876 memset(&req, 0, sizeof(nx_nic_req_t));
877 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
878
879 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
880 req.req_hdr = cpu_to_le64(word);
881
882 /*
883 * RSS request:
884 * bits 3-0: hash_method
885 * 5-4: hash_type_ipv4
886 * 7-6: hash_type_ipv6
887 * 8: enable
888 * 9: use indirection table
889 * 47-10: reserved
890 * 63-48: indirection table mask
891 */
892 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
893 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
894 ((u64)(enable & 0x1) << 8) |
895 ((0x7ULL) << 48);
896 req.words[0] = cpu_to_le64(word);
897 for (i = 0; i < ARRAY_SIZE(key); i++)
898 req.words[i+1] = cpu_to_le64(key[i]);
899
900
901 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
902 if (rv != 0) {
903 printk(KERN_ERR "%s: could not configure RSS\n",
904 adapter->netdev->name);
905 }
906
907 return rv;
908}
909
910int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
911{
912 nx_nic_req_t req;
913 u64 word;
914 int rv;
915
916 memset(&req, 0, sizeof(nx_nic_req_t));
917 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
918
919 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
920 req.req_hdr = cpu_to_le64(word);
921
922 req.words[0] = cpu_to_le64(cmd);
923 req.words[1] = cpu_to_le64(ip);
924
925 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
926 if (rv != 0) {
927 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
928 adapter->netdev->name,
929 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
930 }
931 return rv;
932}
933
934int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
935{
936 nx_nic_req_t req;
937 u64 word;
938 int rv;
939
940 memset(&req, 0, sizeof(nx_nic_req_t));
941 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
942
943 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
944 req.req_hdr = cpu_to_le64(word);
945 req.words[0] = cpu_to_le64(enable | (enable << 8));
946
947 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
948 if (rv != 0) {
949 printk(KERN_ERR "%s: could not configure link notification\n",
950 adapter->netdev->name);
951 }
952
953 return rv;
954}
955
956int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
957{
958 nx_nic_req_t req;
959 u64 word;
960 int rv;
961
962 memset(&req, 0, sizeof(nx_nic_req_t));
963 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
964
965 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
966 ((u64)adapter->portnum << 16) |
967 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
968
969 req.req_hdr = cpu_to_le64(word);
970
971 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
972 if (rv != 0) {
973 printk(KERN_ERR "%s: could not cleanup lro flows\n",
974 adapter->netdev->name);
975 }
976 return rv;
977}
978
979/*
980 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
981 * @returns 0 on success, negative on failure
982 */
983
984#define MTU_FUDGE_FACTOR 100
985
986int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
987{
988 struct netxen_adapter *adapter = netdev_priv(netdev);
989 int max_mtu;
990 int rc = 0;
991
992 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
993 max_mtu = P3_MAX_MTU;
994 else
995 max_mtu = P2_MAX_MTU;
996
997 if (mtu > max_mtu) {
998 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
999 netdev->name, max_mtu);
1000 return -EINVAL;
1001 }
1002
1003 if (adapter->set_mtu)
1004 rc = adapter->set_mtu(adapter, mtu);
1005
1006 if (!rc)
1007 netdev->mtu = mtu;
1008
1009 return rc;
1010}
1011
1012static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1013 int size, __le32 * buf)
1014{
1015 int i, v, addr;
1016 __le32 *ptr32;
1017
1018 addr = base;
1019 ptr32 = buf;
1020 for (i = 0; i < size / sizeof(u32); i++) {
1021 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1022 return -1;
1023 *ptr32 = cpu_to_le32(v);
1024 ptr32++;
1025 addr += sizeof(u32);
1026 }
1027 if ((char *)buf + size > (char *)ptr32) {
1028 __le32 local;
1029 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1030 return -1;
1031 local = cpu_to_le32(v);
1032 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1033 }
1034
1035 return 0;
1036}
1037
1038int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1039{
1040 __le32 *pmac = (__le32 *) mac;
1041 u32 offset;
1042
1043 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1044
1045 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1046 return -1;
1047
1048 if (*mac == cpu_to_le64(~0ULL)) {
1049
1050 offset = NX_OLD_MAC_ADDR_OFFSET +
1051 (adapter->portnum * sizeof(u64));
1052
1053 if (netxen_get_flash_block(adapter,
1054 offset, sizeof(u64), pmac) == -1)
1055 return -1;
1056
1057 if (*mac == cpu_to_le64(~0ULL))
1058 return -1;
1059 }
1060 return 0;
1061}
1062
1063int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1064{
1065 uint32_t crbaddr, mac_hi, mac_lo;
1066 int pci_func = adapter->ahw.pci_func;
1067
1068 crbaddr = CRB_MAC_BLOCK_START +
1069 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1070
1071 mac_lo = NXRD32(adapter, crbaddr);
1072 mac_hi = NXRD32(adapter, crbaddr+4);
1073
1074 if (pci_func & 1)
1075 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1076 else
1077 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1078
1079 return 0;
1080}
1081
1082/*
1083 * Changes the CRB window to the specified window.
1084 */
1085static void
1086netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1087 u32 window)
1088{
1089 void __iomem *offset;
1090 int count = 10;
1091 u8 func = adapter->ahw.pci_func;
1092
1093 if (adapter->ahw.crb_win == window)
1094 return;
1095
1096 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1097 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1098
1099 writel(window, offset);
1100 do {
1101 if (window == readl(offset))
1102 break;
1103
1104 if (printk_ratelimit())
1105 dev_warn(&adapter->pdev->dev,
1106 "failed to set CRB window to %d\n",
1107 (window == NETXEN_WINDOW_ONE));
1108 udelay(1);
1109
1110 } while (--count > 0);
1111
1112 if (count > 0)
1113 adapter->ahw.crb_win = window;
1114}
1115
1116/*
1117 * Returns < 0 if off is not valid,
1118 * 1 if window access is needed. 'off' is set to offset from
1119 * CRB space in 128M pci map
1120 * 0 if no window access is needed. 'off' is set to 2M addr
1121 * In: 'off' is offset from base in 128M pci map
1122 */
1123static int
1124netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1125 ulong off, void __iomem **addr)
1126{
1127 crb_128M_2M_sub_block_map_t *m;
1128
1129
1130 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
1131 return -EINVAL;
1132
1133 off -= NETXEN_PCI_CRBSPACE;
1134
1135 /*
1136 * Try direct map
1137 */
1138 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1139
1140 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1141 *addr = adapter->ahw.pci_base0 + m->start_2M +
1142 (off - m->start_128M);
1143 return 0;
1144 }
1145
1146 /*
1147 * Not in direct map, use crb window
1148 */
1149 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1150 (off & MASK(16));
1151 return 1;
1152}
1153
1154/*
1155 * In: 'off' is offset from CRB space in 128M pci map
1156 * Out: 'off' is 2M pci map addr
1157 * side effect: lock crb window
1158 */
1159static void
1160netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
1161{
1162 u32 window;
1163 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1164
1165 off -= NETXEN_PCI_CRBSPACE;
1166
1167 window = CRB_HI(off);
1168
1169 writel(window, addr);
1170 if (readl(addr) != window) {
1171 if (printk_ratelimit())
1172 dev_warn(&adapter->pdev->dev,
1173 "failed to set CRB window to %d off 0x%lx\n",
1174 window, off);
1175 }
1176}
1177
1178static void __iomem *
1179netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1180 ulong win_off, void __iomem **mem_ptr)
1181{
1182 ulong off = win_off;
1183 void __iomem *addr;
1184 resource_size_t mem_base;
1185
1186 if (ADDR_IN_WINDOW1(win_off))
1187 off = NETXEN_CRB_NORMAL(win_off);
1188
1189 addr = pci_base_offset(adapter, off);
1190 if (addr)
1191 return addr;
1192
1193 if (adapter->ahw.pci_len0 == 0)
1194 off -= NETXEN_PCI_CRBSPACE;
1195
1196 mem_base = pci_resource_start(adapter->pdev, 0);
1197 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1198 if (*mem_ptr)
1199 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1200
1201 return addr;
1202}
1203
1204static int
1205netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1206{
1207 unsigned long flags;
1208 void __iomem *addr, *mem_ptr = NULL;
1209
1210 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1211 if (!addr)
1212 return -EIO;
1213
1214 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1215 netxen_nic_io_write_128M(adapter, addr, data);
1216 } else { /* Window 0 */
1217 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1218 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1219 writel(data, addr);
1220 netxen_nic_pci_set_crbwindow_128M(adapter,
1221 NETXEN_WINDOW_ONE);
1222 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1223 }
1224
1225 if (mem_ptr)
1226 iounmap(mem_ptr);
1227
1228 return 0;
1229}
1230
1231static u32
1232netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1233{
1234 unsigned long flags;
1235 void __iomem *addr, *mem_ptr = NULL;
1236 u32 data;
1237
1238 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1239 if (!addr)
1240 return -EIO;
1241
1242 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1243 data = netxen_nic_io_read_128M(adapter, addr);
1244 } else { /* Window 0 */
1245 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1246 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1247 data = readl(addr);
1248 netxen_nic_pci_set_crbwindow_128M(adapter,
1249 NETXEN_WINDOW_ONE);
1250 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1251 }
1252
1253 if (mem_ptr)
1254 iounmap(mem_ptr);
1255
1256 return data;
1257}
1258
1259static int
1260netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1261{
1262 unsigned long flags;
1263 int rv;
1264 void __iomem *addr = NULL;
1265
1266 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1267
1268 if (rv == 0) {
1269 writel(data, addr);
1270 return 0;
1271 }
1272
1273 if (rv > 0) {
1274 /* indirect access */
1275 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1276 crb_win_lock(adapter);
1277 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1278 writel(data, addr);
1279 crb_win_unlock(adapter);
1280 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1281 return 0;
1282 }
1283
1284 dev_err(&adapter->pdev->dev,
1285 "%s: invalid offset: 0x%016lx\n", __func__, off);
1286 dump_stack();
1287 return -EIO;
1288}
1289
1290static u32
1291netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1292{
1293 unsigned long flags;
1294 int rv;
1295 u32 data;
1296 void __iomem *addr = NULL;
1297
1298 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1299
1300 if (rv == 0)
1301 return readl(addr);
1302
1303 if (rv > 0) {
1304 /* indirect access */
1305 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1306 crb_win_lock(adapter);
1307 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1308 data = readl(addr);
1309 crb_win_unlock(adapter);
1310 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1311 return data;
1312 }
1313
1314 dev_err(&adapter->pdev->dev,
1315 "%s: invalid offset: 0x%016lx\n", __func__, off);
1316 dump_stack();
1317 return -1;
1318}
1319
1320/* window 1 registers only */
1321static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1322 void __iomem *addr, u32 data)
1323{
1324 read_lock(&adapter->ahw.crb_lock);
1325 writel(data, addr);
1326 read_unlock(&adapter->ahw.crb_lock);
1327}
1328
1329static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1330 void __iomem *addr)
1331{
1332 u32 val;
1333
1334 read_lock(&adapter->ahw.crb_lock);
1335 val = readl(addr);
1336 read_unlock(&adapter->ahw.crb_lock);
1337
1338 return val;
1339}
1340
1341static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1342 void __iomem *addr, u32 data)
1343{
1344 writel(data, addr);
1345}
1346
1347static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1348 void __iomem *addr)
1349{
1350 return readl(addr);
1351}
1352
1353void __iomem *
1354netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1355{
1356 void __iomem *addr = NULL;
1357
1358 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1359 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1360 (offset > NETXEN_CRB_PCIX_HOST))
1361 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1362 else
1363 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1364 } else {
1365 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1366 offset, &addr));
1367 }
1368
1369 return addr;
1370}
1371
1372static int
1373netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1374 u64 addr, u32 *start)
1375{
1376 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1377 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1378 return 0;
1379 } else if (ADDR_IN_RANGE(addr,
1380 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1381 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1382 return 0;
1383 }
1384
1385 return -EIO;
1386}
1387
1388static int
1389netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1390 u64 addr, u32 *start)
1391{
1392 u32 window;
1393
1394 window = OCM_WIN(addr);
1395
1396 writel(window, adapter->ahw.ocm_win_crb);
1397 /* read back to flush */
1398 readl(adapter->ahw.ocm_win_crb);
1399
1400 adapter->ahw.ocm_win = window;
1401 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1402 return 0;
1403}
1404
1405static int
1406netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1407 u64 *data, int op)
1408{
1409 void __iomem *addr, *mem_ptr = NULL;
1410 resource_size_t mem_base;
1411 int ret;
1412 u32 start;
1413
1414 spin_lock(&adapter->ahw.mem_lock);
1415
1416 ret = adapter->pci_set_window(adapter, off, &start);
1417 if (ret != 0)
1418 goto unlock;
1419
1420 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1421 addr = adapter->ahw.pci_base0 + start;
1422 } else {
1423 addr = pci_base_offset(adapter, start);
1424 if (addr)
1425 goto noremap;
1426
1427 mem_base = pci_resource_start(adapter->pdev, 0) +
1428 (start & PAGE_MASK);
1429 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1430 if (mem_ptr == NULL) {
1431 ret = -EIO;
1432 goto unlock;
1433 }
1434
1435 addr = mem_ptr + (start & (PAGE_SIZE-1));
1436 }
1437noremap:
1438 if (op == 0) /* read */
1439 *data = readq(addr);
1440 else /* write */
1441 writeq(*data, addr);
1442
1443unlock:
1444 spin_unlock(&adapter->ahw.mem_lock);
1445
1446 if (mem_ptr)
1447 iounmap(mem_ptr);
1448 return ret;
1449}
1450
1451void
1452netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data)
1453{
1454 void __iomem *addr = adapter->ahw.pci_base0 +
1455 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1456
1457 spin_lock(&adapter->ahw.mem_lock);
1458 *data = readq(addr);
1459 spin_unlock(&adapter->ahw.mem_lock);
1460}
1461
1462void
1463netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data)
1464{
1465 void __iomem *addr = adapter->ahw.pci_base0 +
1466 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1467
1468 spin_lock(&adapter->ahw.mem_lock);
1469 writeq(data, addr);
1470 spin_unlock(&adapter->ahw.mem_lock);
1471}
1472
1473#define MAX_CTL_CHECK 1000
1474
1475static int
1476netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1477 u64 off, u64 data)
1478{
1479 int j, ret;
1480 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1481 void __iomem *mem_crb;
1482
1483 /* Only 64-bit aligned access */
1484 if (off & 7)
1485 return -EIO;
1486
1487 /* P2 has different SIU and MIU test agent base addr */
1488 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1489 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1490 mem_crb = pci_base_offset(adapter,
1491 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1492 addr_hi = SIU_TEST_AGT_ADDR_HI;
1493 data_lo = SIU_TEST_AGT_WRDATA_LO;
1494 data_hi = SIU_TEST_AGT_WRDATA_HI;
1495 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1496 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1497 goto correct;
1498 }
1499
1500 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1501 mem_crb = pci_base_offset(adapter,
1502 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1503 addr_hi = MIU_TEST_AGT_ADDR_HI;
1504 data_lo = MIU_TEST_AGT_WRDATA_LO;
1505 data_hi = MIU_TEST_AGT_WRDATA_HI;
1506 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1507 off_hi = 0;
1508 goto correct;
1509 }
1510
1511 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1512 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1513 if (adapter->ahw.pci_len0 != 0) {
1514 return netxen_nic_pci_mem_access_direct(adapter,
1515 off, &data, 1);
1516 }
1517 }
1518
1519 return -EIO;
1520
1521correct:
1522 spin_lock(&adapter->ahw.mem_lock);
1523 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1524
1525 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1526 writel(off_hi, (mem_crb + addr_hi));
1527 writel(data & 0xffffffff, (mem_crb + data_lo));
1528 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1529 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1530 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1531 (mem_crb + TEST_AGT_CTRL));
1532
1533 for (j = 0; j < MAX_CTL_CHECK; j++) {
1534 temp = readl((mem_crb + TEST_AGT_CTRL));
1535 if ((temp & TA_CTL_BUSY) == 0)
1536 break;
1537 }
1538
1539 if (j >= MAX_CTL_CHECK) {
1540 if (printk_ratelimit())
1541 dev_err(&adapter->pdev->dev,
1542 "failed to write through agent\n");
1543 ret = -EIO;
1544 } else
1545 ret = 0;
1546
1547 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1548 spin_unlock(&adapter->ahw.mem_lock);
1549 return ret;
1550}
1551
1552static int
1553netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1554 u64 off, u64 *data)
1555{
1556 int j, ret;
1557 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1558 u64 val;
1559 void __iomem *mem_crb;
1560
1561 /* Only 64-bit aligned access */
1562 if (off & 7)
1563 return -EIO;
1564
1565 /* P2 has different SIU and MIU test agent base addr */
1566 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1567 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1568 mem_crb = pci_base_offset(adapter,
1569 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1570 addr_hi = SIU_TEST_AGT_ADDR_HI;
1571 data_lo = SIU_TEST_AGT_RDDATA_LO;
1572 data_hi = SIU_TEST_AGT_RDDATA_HI;
1573 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1574 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1575 goto correct;
1576 }
1577
1578 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1579 mem_crb = pci_base_offset(adapter,
1580 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1581 addr_hi = MIU_TEST_AGT_ADDR_HI;
1582 data_lo = MIU_TEST_AGT_RDDATA_LO;
1583 data_hi = MIU_TEST_AGT_RDDATA_HI;
1584 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1585 off_hi = 0;
1586 goto correct;
1587 }
1588
1589 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1590 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1591 if (adapter->ahw.pci_len0 != 0) {
1592 return netxen_nic_pci_mem_access_direct(adapter,
1593 off, data, 0);
1594 }
1595 }
1596
1597 return -EIO;
1598
1599correct:
1600 spin_lock(&adapter->ahw.mem_lock);
1601 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1602
1603 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1604 writel(off_hi, (mem_crb + addr_hi));
1605 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1606 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1607
1608 for (j = 0; j < MAX_CTL_CHECK; j++) {
1609 temp = readl(mem_crb + TEST_AGT_CTRL);
1610 if ((temp & TA_CTL_BUSY) == 0)
1611 break;
1612 }
1613
1614 if (j >= MAX_CTL_CHECK) {
1615 if (printk_ratelimit())
1616 dev_err(&adapter->pdev->dev,
1617 "failed to read through agent\n");
1618 ret = -EIO;
1619 } else {
1620
1621 temp = readl(mem_crb + data_hi);
1622 val = ((u64)temp << 32);
1623 val |= readl(mem_crb + data_lo);
1624 *data = val;
1625 ret = 0;
1626 }
1627
1628 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1629 spin_unlock(&adapter->ahw.mem_lock);
1630
1631 return ret;
1632}
1633
1634static int
1635netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1636 u64 off, u64 data)
1637{
1638 int j, ret;
1639 u32 temp, off8;
1640 void __iomem *mem_crb;
1641
1642 /* Only 64-bit aligned access */
1643 if (off & 7)
1644 return -EIO;
1645
1646 /* P3 onward, test agent base for MIU and SIU is same */
1647 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1648 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1649 mem_crb = netxen_get_ioaddr(adapter,
1650 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1651 goto correct;
1652 }
1653
1654 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1655 mem_crb = netxen_get_ioaddr(adapter,
1656 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1657 goto correct;
1658 }
1659
1660 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1661 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1662
1663 return -EIO;
1664
1665correct:
1666 off8 = off & 0xfffffff8;
1667
1668 spin_lock(&adapter->ahw.mem_lock);
1669
1670 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1671 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1672
1673 writel(data & 0xffffffff,
1674 mem_crb + MIU_TEST_AGT_WRDATA_LO);
1675 writel((data >> 32) & 0xffffffff,
1676 mem_crb + MIU_TEST_AGT_WRDATA_HI);
1677
1678 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1679 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1680 (mem_crb + TEST_AGT_CTRL));
1681
1682 for (j = 0; j < MAX_CTL_CHECK; j++) {
1683 temp = readl(mem_crb + TEST_AGT_CTRL);
1684 if ((temp & TA_CTL_BUSY) == 0)
1685 break;
1686 }
1687
1688 if (j >= MAX_CTL_CHECK) {
1689 if (printk_ratelimit())
1690 dev_err(&adapter->pdev->dev,
1691 "failed to write through agent\n");
1692 ret = -EIO;
1693 } else
1694 ret = 0;
1695
1696 spin_unlock(&adapter->ahw.mem_lock);
1697
1698 return ret;
1699}
1700
1701static int
1702netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1703 u64 off, u64 *data)
1704{
1705 int j, ret;
1706 u32 temp, off8;
1707 u64 val;
1708 void __iomem *mem_crb;
1709
1710 /* Only 64-bit aligned access */
1711 if (off & 7)
1712 return -EIO;
1713
1714 /* P3 onward, test agent base for MIU and SIU is same */
1715 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1716 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1717 mem_crb = netxen_get_ioaddr(adapter,
1718 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1719 goto correct;
1720 }
1721
1722 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1723 mem_crb = netxen_get_ioaddr(adapter,
1724 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1725 goto correct;
1726 }
1727
1728 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1729 return netxen_nic_pci_mem_access_direct(adapter,
1730 off, data, 0);
1731 }
1732
1733 return -EIO;
1734
1735correct:
1736 off8 = off & 0xfffffff8;
1737
1738 spin_lock(&adapter->ahw.mem_lock);
1739
1740 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1741 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1742 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1743 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1744
1745 for (j = 0; j < MAX_CTL_CHECK; j++) {
1746 temp = readl(mem_crb + TEST_AGT_CTRL);
1747 if ((temp & TA_CTL_BUSY) == 0)
1748 break;
1749 }
1750
1751 if (j >= MAX_CTL_CHECK) {
1752 if (printk_ratelimit())
1753 dev_err(&adapter->pdev->dev,
1754 "failed to read through agent\n");
1755 ret = -EIO;
1756 } else {
1757 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1758 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1759 *data = val;
1760 ret = 0;
1761 }
1762
1763 spin_unlock(&adapter->ahw.mem_lock);
1764
1765 return ret;
1766}
1767
1768void
1769netxen_setup_hwops(struct netxen_adapter *adapter)
1770{
1771 adapter->init_port = netxen_niu_xg_init_port;
1772 adapter->stop_port = netxen_niu_disable_xg_port;
1773
1774 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1775 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1776 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1777 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1778 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1779 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1780 adapter->io_read = netxen_nic_io_read_128M,
1781 adapter->io_write = netxen_nic_io_write_128M,
1782
1783 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1784 adapter->set_multi = netxen_p2_nic_set_multi;
1785 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1786 adapter->set_promisc = netxen_p2_nic_set_promisc;
1787
1788 } else {
1789 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1790 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1791 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1792 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1793 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1794 adapter->io_read = netxen_nic_io_read_2M,
1795 adapter->io_write = netxen_nic_io_write_2M,
1796
1797 adapter->set_mtu = nx_fw_cmd_set_mtu;
1798 adapter->set_promisc = netxen_p3_nic_set_promisc;
1799 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1800 adapter->set_multi = netxen_p3_nic_set_multi;
1801
1802 adapter->phy_read = nx_fw_cmd_query_phy;
1803 adapter->phy_write = nx_fw_cmd_set_phy;
1804 }
1805}
1806
1807int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1808{
1809 int offset, board_type, magic;
1810 struct pci_dev *pdev = adapter->pdev;
1811
1812 offset = NX_FW_MAGIC_OFFSET;
1813 if (netxen_rom_fast_read(adapter, offset, &magic))
1814 return -EIO;
1815
1816 if (magic != NETXEN_BDINFO_MAGIC) {
1817 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1818 magic);
1819 return -EIO;
1820 }
1821
1822 offset = NX_BRDTYPE_OFFSET;
1823 if (netxen_rom_fast_read(adapter, offset, &board_type))
1824 return -EIO;
1825
1826 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1827 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1828 if ((gpio & 0x8000) == 0)
1829 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1830 }
1831
1832 adapter->ahw.board_type = board_type;
1833
1834 switch (board_type) {
1835 case NETXEN_BRDTYPE_P2_SB35_4G:
1836 adapter->ahw.port_type = NETXEN_NIC_GBE;
1837 break;
1838 case NETXEN_BRDTYPE_P2_SB31_10G:
1839 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1840 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1841 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1842 case NETXEN_BRDTYPE_P3_HMEZ:
1843 case NETXEN_BRDTYPE_P3_XG_LOM:
1844 case NETXEN_BRDTYPE_P3_10G_CX4:
1845 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1846 case NETXEN_BRDTYPE_P3_IMEZ:
1847 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1848 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1849 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1850 case NETXEN_BRDTYPE_P3_10G_XFP:
1851 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1852 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1853 break;
1854 case NETXEN_BRDTYPE_P1_BD:
1855 case NETXEN_BRDTYPE_P1_SB:
1856 case NETXEN_BRDTYPE_P1_SMAX:
1857 case NETXEN_BRDTYPE_P1_SOCK:
1858 case NETXEN_BRDTYPE_P3_REF_QG:
1859 case NETXEN_BRDTYPE_P3_4_GB:
1860 case NETXEN_BRDTYPE_P3_4_GB_MM:
1861 adapter->ahw.port_type = NETXEN_NIC_GBE;
1862 break;
1863 case NETXEN_BRDTYPE_P3_10G_TP:
1864 adapter->ahw.port_type = (adapter->portnum < 2) ?
1865 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1866 break;
1867 default:
1868 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1869 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1870 break;
1871 }
1872
1873 return 0;
1874}
1875
1876/* NIU access sections */
1877static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1878{
1879 new_mtu += MTU_FUDGE_FACTOR;
1880 if (adapter->physical_port == 0)
1881 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1882 else
1883 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1884 return 0;
1885}
1886
1887void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1888{
1889 __u32 status;
1890 __u32 autoneg;
1891 __u32 port_mode;
1892
1893 if (!netif_carrier_ok(adapter->netdev)) {
1894 adapter->link_speed = 0;
1895 adapter->link_duplex = -1;
1896 adapter->link_autoneg = AUTONEG_ENABLE;
1897 return;
1898 }
1899
1900 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1901 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1902 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1903 adapter->link_speed = SPEED_1000;
1904 adapter->link_duplex = DUPLEX_FULL;
1905 adapter->link_autoneg = AUTONEG_DISABLE;
1906 return;
1907 }
1908
1909 if (adapter->phy_read &&
1910 adapter->phy_read(adapter,
1911 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1912 &status) == 0) {
1913 if (netxen_get_phy_link(status)) {
1914 switch (netxen_get_phy_speed(status)) {
1915 case 0:
1916 adapter->link_speed = SPEED_10;
1917 break;
1918 case 1:
1919 adapter->link_speed = SPEED_100;
1920 break;
1921 case 2:
1922 adapter->link_speed = SPEED_1000;
1923 break;
1924 default:
1925 adapter->link_speed = 0;
1926 break;
1927 }
1928 switch (netxen_get_phy_duplex(status)) {
1929 case 0:
1930 adapter->link_duplex = DUPLEX_HALF;
1931 break;
1932 case 1:
1933 adapter->link_duplex = DUPLEX_FULL;
1934 break;
1935 default:
1936 adapter->link_duplex = -1;
1937 break;
1938 }
1939 if (adapter->phy_read &&
1940 adapter->phy_read(adapter,
1941 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1942 &autoneg) != 0)
1943 adapter->link_autoneg = autoneg;
1944 } else
1945 goto link_down;
1946 } else {
1947 link_down:
1948 adapter->link_speed = 0;
1949 adapter->link_duplex = -1;
1950 }
1951 }
1952}
1953
1954int
1955netxen_nic_wol_supported(struct netxen_adapter *adapter)
1956{
1957 u32 wol_cfg;
1958
1959 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1960 return 0;
1961
1962 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1963 if (wol_cfg & (1UL << adapter->portnum)) {
1964 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1965 if (wol_cfg & (1 << adapter->portnum))
1966 return 1;
1967 }
1968
1969 return 0;
1970}