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1/* 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18#ifndef BE_H 19#define BE_H 20 21#include <linux/pci.h> 22#include <linux/etherdevice.h> 23#include <linux/version.h> 24#include <linux/delay.h> 25#include <net/tcp.h> 26#include <net/ip.h> 27#include <net/ipv6.h> 28#include <linux/if_vlan.h> 29#include <linux/workqueue.h> 30#include <linux/interrupt.h> 31#include <linux/firmware.h> 32#include <linux/slab.h> 33 34#include "be_hw.h" 35 36#define DRV_VER "4.0.100u" 37#define DRV_NAME "be2net" 38#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" 39#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" 40#define OC_NAME "Emulex OneConnect 10Gbps NIC" 41#define OC_NAME_BE OC_NAME "(be3)" 42#define OC_NAME_LANCER OC_NAME "(Lancer)" 43#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver" 44 45#define BE_VENDOR_ID 0x19a2 46#define EMULEX_VENDOR_ID 0x10df 47#define BE_DEVICE_ID1 0x211 48#define BE_DEVICE_ID2 0x221 49#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 50#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 51#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 52 53static inline char *nic_name(struct pci_dev *pdev) 54{ 55 switch (pdev->device) { 56 case OC_DEVICE_ID1: 57 return OC_NAME; 58 case OC_DEVICE_ID2: 59 return OC_NAME_BE; 60 case OC_DEVICE_ID3: 61 return OC_NAME_LANCER; 62 case BE_DEVICE_ID2: 63 return BE3_NAME; 64 default: 65 return BE_NAME; 66 } 67} 68 69/* Number of bytes of an RX frame that are copied to skb->data */ 70#define BE_HDR_LEN ((u16) 64) 71#define BE_MAX_JUMBO_FRAME_SIZE 9018 72#define BE_MIN_MTU 256 73 74#define BE_NUM_VLANS_SUPPORTED 64 75#define BE_MAX_EQD 96 76#define BE_MAX_TX_FRAG_COUNT 30 77 78#define EVNT_Q_LEN 1024 79#define TX_Q_LEN 2048 80#define TX_CQ_LEN 1024 81#define RX_Q_LEN 1024 /* Does not support any other value */ 82#define RX_CQ_LEN 1024 83#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 84#define MCC_CQ_LEN 256 85 86#define MAX_RSS_QS 4 /* BE limit is 4 queues/port */ 87#define BE_MAX_MSIX_VECTORS (MAX_RSS_QS + 1 + 1)/* RSS qs + 1 def Rx + Tx */ 88#define BE_NAPI_WEIGHT 64 89#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 90#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 91 92#define FW_VER_LEN 32 93 94#define BE_MAX_VF 32 95 96struct be_dma_mem { 97 void *va; 98 dma_addr_t dma; 99 u32 size; 100}; 101 102struct be_queue_info { 103 struct be_dma_mem dma_mem; 104 u16 len; 105 u16 entry_size; /* Size of an element in the queue */ 106 u16 id; 107 u16 tail, head; 108 bool created; 109 atomic_t used; /* Number of valid elements in the queue */ 110}; 111 112static inline u32 MODULO(u16 val, u16 limit) 113{ 114 BUG_ON(limit & (limit - 1)); 115 return val & (limit - 1); 116} 117 118static inline void index_adv(u16 *index, u16 val, u16 limit) 119{ 120 *index = MODULO((*index + val), limit); 121} 122 123static inline void index_inc(u16 *index, u16 limit) 124{ 125 *index = MODULO((*index + 1), limit); 126} 127 128static inline void *queue_head_node(struct be_queue_info *q) 129{ 130 return q->dma_mem.va + q->head * q->entry_size; 131} 132 133static inline void *queue_tail_node(struct be_queue_info *q) 134{ 135 return q->dma_mem.va + q->tail * q->entry_size; 136} 137 138static inline void queue_head_inc(struct be_queue_info *q) 139{ 140 index_inc(&q->head, q->len); 141} 142 143static inline void queue_tail_inc(struct be_queue_info *q) 144{ 145 index_inc(&q->tail, q->len); 146} 147 148struct be_eq_obj { 149 struct be_queue_info q; 150 char desc[32]; 151 152 /* Adaptive interrupt coalescing (AIC) info */ 153 bool enable_aic; 154 u16 min_eqd; /* in usecs */ 155 u16 max_eqd; /* in usecs */ 156 u16 cur_eqd; /* in usecs */ 157 u8 eq_idx; 158 159 struct napi_struct napi; 160}; 161 162struct be_mcc_obj { 163 struct be_queue_info q; 164 struct be_queue_info cq; 165 bool rearm_cq; 166}; 167 168struct be_tx_stats { 169 u32 be_tx_reqs; /* number of TX requests initiated */ 170 u32 be_tx_stops; /* number of times TX Q was stopped */ 171 u32 be_tx_wrbs; /* number of tx WRBs used */ 172 u32 be_tx_events; /* number of tx completion events */ 173 u32 be_tx_compl; /* number of tx completion entries processed */ 174 ulong be_tx_jiffies; 175 u64 be_tx_bytes; 176 u64 be_tx_bytes_prev; 177 u64 be_tx_pkts; 178 u32 be_tx_rate; 179}; 180 181struct be_tx_obj { 182 struct be_queue_info q; 183 struct be_queue_info cq; 184 /* Remember the skbs that were transmitted */ 185 struct sk_buff *sent_skb_list[TX_Q_LEN]; 186}; 187 188/* Struct to remember the pages posted for rx frags */ 189struct be_rx_page_info { 190 struct page *page; 191 DEFINE_DMA_UNMAP_ADDR(bus); 192 u16 page_offset; 193 bool last_page_user; 194}; 195 196struct be_rx_stats { 197 u32 rx_post_fail;/* number of ethrx buffer alloc failures */ 198 u32 rx_polls; /* number of times NAPI called poll function */ 199 u32 rx_events; /* number of ucast rx completion events */ 200 u32 rx_compl; /* number of rx completion entries processed */ 201 ulong rx_jiffies; 202 u64 rx_bytes; 203 u64 rx_bytes_prev; 204 u64 rx_pkts; 205 u32 rx_rate; 206 u32 rx_mcast_pkts; 207 u32 rxcp_err; /* Num rx completion entries w/ err set. */ 208 ulong rx_fps_jiffies; /* jiffies at last FPS calc */ 209 u32 rx_frags; 210 u32 prev_rx_frags; 211 u32 rx_fps; /* Rx frags per second */ 212}; 213 214struct be_rx_compl_info { 215 u32 rss_hash; 216 u16 vid; 217 u16 pkt_size; 218 u16 rxq_idx; 219 u16 mac_id; 220 u8 vlanf; 221 u8 num_rcvd; 222 u8 err; 223 u8 ipf; 224 u8 tcpf; 225 u8 udpf; 226 u8 ip_csum; 227 u8 l4_csum; 228 u8 ipv6; 229 u8 vtm; 230 u8 pkt_type; 231}; 232 233struct be_rx_obj { 234 struct be_adapter *adapter; 235 struct be_queue_info q; 236 struct be_queue_info cq; 237 struct be_rx_compl_info rxcp; 238 struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 239 struct be_eq_obj rx_eq; 240 struct be_rx_stats stats; 241 u8 rss_id; 242 bool rx_post_starved; /* Zero rx frags have been posted to BE */ 243 u32 cache_line_barrier[16]; 244}; 245 246struct be_drv_stats { 247 u8 be_on_die_temperature; 248}; 249 250struct be_vf_cfg { 251 unsigned char vf_mac_addr[ETH_ALEN]; 252 u32 vf_if_handle; 253 u32 vf_pmac_id; 254 u16 vf_vlan_tag; 255 u32 vf_tx_rate; 256}; 257 258#define BE_INVALID_PMAC_ID 0xffffffff 259 260struct be_adapter { 261 struct pci_dev *pdev; 262 struct net_device *netdev; 263 264 u8 __iomem *csr; 265 u8 __iomem *db; /* Door Bell */ 266 u8 __iomem *pcicfg; /* PCI config space */ 267 268 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 269 struct be_dma_mem mbox_mem; 270 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 271 * is stored for freeing purpose */ 272 struct be_dma_mem mbox_mem_alloced; 273 274 struct be_mcc_obj mcc_obj; 275 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 276 spinlock_t mcc_cq_lock; 277 278 struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS]; 279 bool msix_enabled; 280 bool isr_registered; 281 282 /* TX Rings */ 283 struct be_eq_obj tx_eq; 284 struct be_tx_obj tx_obj; 285 struct be_tx_stats tx_stats; 286 287 u32 cache_line_break[8]; 288 289 /* Rx rings */ 290 struct be_rx_obj rx_obj[MAX_RSS_QS + 1]; /* one default non-rss Q */ 291 u32 num_rx_qs; 292 u32 big_page_size; /* Compounded page size shared by rx wrbs */ 293 294 u8 eq_next_idx; 295 struct be_drv_stats drv_stats; 296 297 struct vlan_group *vlan_grp; 298 u16 vlans_added; 299 u16 max_vlans; /* Number of vlans supported */ 300 u8 vlan_tag[VLAN_N_VID]; 301 u8 vlan_prio_bmap; /* Available Priority BitMap */ 302 u16 recommended_prio; /* Recommended Priority */ 303 struct be_dma_mem mc_cmd_mem; 304 305 struct be_dma_mem stats_cmd; 306 /* Work queue used to perform periodic tasks like getting statistics */ 307 struct delayed_work work; 308 u16 work_counter; 309 310 /* Ethtool knobs and info */ 311 bool rx_csum; /* BE card must perform rx-checksumming */ 312 char fw_ver[FW_VER_LEN]; 313 u32 if_handle; /* Used to configure filtering */ 314 u32 pmac_id; /* MAC addr handle used by BE card */ 315 316 bool eeh_err; 317 bool link_up; 318 u32 port_num; 319 bool promiscuous; 320 bool wol; 321 u32 function_mode; 322 u32 function_caps; 323 u32 rx_fc; /* Rx flow control */ 324 u32 tx_fc; /* Tx flow control */ 325 bool ue_detected; 326 bool stats_cmd_sent; 327 int link_speed; 328 u8 port_type; 329 u8 transceiver; 330 u8 autoneg; 331 u8 generation; /* BladeEngine ASIC generation */ 332 u32 flash_status; 333 struct completion flash_compl; 334 335 bool be3_native; 336 bool sriov_enabled; 337 struct be_vf_cfg vf_cfg[BE_MAX_VF]; 338 u8 is_virtfn; 339 u32 sli_family; 340 u8 hba_port_num; 341 u16 pvid; 342}; 343 344#define be_physfn(adapter) (!adapter->is_virtfn) 345 346/* BladeEngine Generation numbers */ 347#define BE_GEN2 2 348#define BE_GEN3 3 349 350#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3) 351 352extern const struct ethtool_ops be_ethtool_ops; 353 354#define tx_stats(adapter) (&adapter->tx_stats) 355#define rx_stats(rxo) (&rxo->stats) 356 357#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) 358 359#define for_all_rx_queues(adapter, rxo, i) \ 360 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 361 i++, rxo++) 362 363/* Just skip the first default non-rss queue */ 364#define for_all_rss_queues(adapter, rxo, i) \ 365 for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\ 366 i++, rxo++) 367 368#define PAGE_SHIFT_4K 12 369#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 370 371/* Returns number of pages spanned by the data starting at the given addr */ 372#define PAGES_4K_SPANNED(_address, size) \ 373 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 374 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 375 376/* Byte offset into the page corresponding to given address */ 377#define OFFSET_IN_PAGE(addr) \ 378 ((size_t)(addr) & (PAGE_SIZE_4K-1)) 379 380/* Returns bit offset within a DWORD of a bitfield */ 381#define AMAP_BIT_OFFSET(_struct, field) \ 382 (((size_t)&(((_struct *)0)->field))%32) 383 384/* Returns the bit mask of the field that is NOT shifted into location. */ 385static inline u32 amap_mask(u32 bitsize) 386{ 387 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 388} 389 390static inline void 391amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 392{ 393 u32 *dw = (u32 *) ptr + dw_offset; 394 *dw &= ~(mask << offset); 395 *dw |= (mask & value) << offset; 396} 397 398#define AMAP_SET_BITS(_struct, field, ptr, val) \ 399 amap_set(ptr, \ 400 offsetof(_struct, field)/32, \ 401 amap_mask(sizeof(((_struct *)0)->field)), \ 402 AMAP_BIT_OFFSET(_struct, field), \ 403 val) 404 405static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 406{ 407 u32 *dw = (u32 *) ptr; 408 return mask & (*(dw + dw_offset) >> offset); 409} 410 411#define AMAP_GET_BITS(_struct, field, ptr) \ 412 amap_get(ptr, \ 413 offsetof(_struct, field)/32, \ 414 amap_mask(sizeof(((_struct *)0)->field)), \ 415 AMAP_BIT_OFFSET(_struct, field)) 416 417#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 418#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 419static inline void swap_dws(void *wrb, int len) 420{ 421#ifdef __BIG_ENDIAN 422 u32 *dw = wrb; 423 BUG_ON(len % 4); 424 do { 425 *dw = cpu_to_le32(*dw); 426 dw++; 427 len -= 4; 428 } while (len); 429#endif /* __BIG_ENDIAN */ 430} 431 432static inline u8 is_tcp_pkt(struct sk_buff *skb) 433{ 434 u8 val = 0; 435 436 if (ip_hdr(skb)->version == 4) 437 val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 438 else if (ip_hdr(skb)->version == 6) 439 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 440 441 return val; 442} 443 444static inline u8 is_udp_pkt(struct sk_buff *skb) 445{ 446 u8 val = 0; 447 448 if (ip_hdr(skb)->version == 4) 449 val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 450 else if (ip_hdr(skb)->version == 6) 451 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 452 453 return val; 454} 455 456static inline void be_check_sriov_fn_type(struct be_adapter *adapter) 457{ 458 u8 data; 459 u32 sli_intf; 460 461 if (lancer_chip(adapter)) { 462 pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, 463 &sli_intf); 464 adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0; 465 } else { 466 pci_write_config_byte(adapter->pdev, 0xFE, 0xAA); 467 pci_read_config_byte(adapter->pdev, 0xFE, &data); 468 adapter->is_virtfn = (data != 0xAA); 469 } 470} 471 472static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) 473{ 474 u32 addr; 475 476 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); 477 478 mac[5] = (u8)(addr & 0xFF); 479 mac[4] = (u8)((addr >> 8) & 0xFF); 480 mac[3] = (u8)((addr >> 16) & 0xFF); 481 /* Use the OUI from the current MAC address */ 482 memcpy(mac, adapter->netdev->dev_addr, 3); 483} 484 485extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 486 u16 num_popped); 487extern void be_link_status_update(struct be_adapter *adapter, bool link_up); 488extern void netdev_stats_update(struct be_adapter *adapter); 489extern int be_load_fw(struct be_adapter *adapter, u8 *func); 490#endif /* BE_H */