tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * arch/sh/include/asm/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <asm/dma-register.h>
15#include <cpu/dma-register.h>
16#include <cpu/dma.h>
17
18/* DMAOR contorl: The DMAOR access size is different by CPU.*/
19#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7724) || \
21 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
22 defined(CONFIG_CPU_SUBTYPE_SH7785)
23#define dmaor_read_reg(n) \
24 (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
25 : __raw_readw(SH_DMAC_BASE0 + DMAOR))
26#define dmaor_write_reg(n, data) \
27 (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
28 : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
29#else /* Other CPU */
30#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
31#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
32#endif
33
34static int dmte_irq_map[] __maybe_unused = {
35#if (MAX_DMA_CHANNELS >= 4)
36 DMTE0_IRQ,
37 DMTE0_IRQ + 1,
38 DMTE0_IRQ + 2,
39 DMTE0_IRQ + 3,
40#endif
41#if (MAX_DMA_CHANNELS >= 6)
42 DMTE4_IRQ,
43 DMTE4_IRQ + 1,
44#endif
45#if (MAX_DMA_CHANNELS >= 8)
46 DMTE6_IRQ,
47 DMTE6_IRQ + 1,
48#endif
49#if (MAX_DMA_CHANNELS >= 12)
50 DMTE8_IRQ,
51 DMTE9_IRQ,
52 DMTE10_IRQ,
53 DMTE11_IRQ,
54#endif
55};
56
57/*
58 * Define the default configuration for dual address memory-memory transfer.
59 * The 0x400 value represents auto-request, external->external.
60 */
61#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
62
63/* DMA base address */
64static u32 dma_base_addr[] __maybe_unused = {
65#if (MAX_DMA_CHANNELS >= 4)
66 SH_DMAC_BASE0 + 0x00, /* channel 0 */
67 SH_DMAC_BASE0 + 0x10,
68 SH_DMAC_BASE0 + 0x20,
69 SH_DMAC_BASE0 + 0x30,
70#endif
71#if (MAX_DMA_CHANNELS >= 6)
72 SH_DMAC_BASE0 + 0x50,
73 SH_DMAC_BASE0 + 0x60,
74#endif
75#if (MAX_DMA_CHANNELS >= 8)
76 SH_DMAC_BASE1 + 0x00,
77 SH_DMAC_BASE1 + 0x10,
78#endif
79#if (MAX_DMA_CHANNELS >= 12)
80 SH_DMAC_BASE1 + 0x20,
81 SH_DMAC_BASE1 + 0x30,
82 SH_DMAC_BASE1 + 0x50,
83 SH_DMAC_BASE1 + 0x60, /* channel 11 */
84#endif
85};
86
87#endif /* __DMA_SH_H */