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1/*
2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#ifndef STE_DMA40_LL_H
8#define STE_DMA40_LL_H
9
10#define D40_DREG_PCBASE 0x400
11#define D40_DREG_PCDELTA (8 * 4)
12#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
13
14#define D40_LCPA_CHAN_SIZE 32
15#define D40_LCPA_CHAN_DST_DELTA 16
16
17#define D40_TYPE_TO_GROUP(type) (type / 16)
18#define D40_TYPE_TO_EVENT(type) (type % 16)
19
20/* Most bits of the CFG register are the same in log as in phy mode */
21#define D40_SREG_CFG_MST_POS 15
22#define D40_SREG_CFG_TIM_POS 14
23#define D40_SREG_CFG_EIM_POS 13
24#define D40_SREG_CFG_LOG_INCR_POS 12
25#define D40_SREG_CFG_PHY_PEN_POS 12
26#define D40_SREG_CFG_PSIZE_POS 10
27#define D40_SREG_CFG_ESIZE_POS 8
28#define D40_SREG_CFG_PRI_POS 7
29#define D40_SREG_CFG_LBE_POS 6
30#define D40_SREG_CFG_LOG_GIM_POS 5
31#define D40_SREG_CFG_LOG_MFU_POS 4
32#define D40_SREG_CFG_PHY_TM_POS 4
33#define D40_SREG_CFG_PHY_EVTL_POS 0
34
35
36/* Standard channel parameters - basic mode (element register) */
37#define D40_SREG_ELEM_PHY_ECNT_POS 16
38#define D40_SREG_ELEM_PHY_EIDX_POS 0
39
40#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
41
42/* Standard channel parameters - basic mode (Link register) */
43#define D40_SREG_LNK_PHY_TCP_POS 0
44#define D40_SREG_LNK_PHY_LMP_POS 1
45#define D40_SREG_LNK_PHY_PRE_POS 2
46/*
47 * Source destination link address. Contains the
48 * 29-bit byte word aligned address of the reload area.
49 */
50#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
51
52/* Standard basic channel logical mode */
53
54/* Element register */
55#define D40_SREG_ELEM_LOG_ECNT_POS 16
56#define D40_SREG_ELEM_LOG_LIDX_POS 8
57#define D40_SREG_ELEM_LOG_LOS_POS 1
58#define D40_SREG_ELEM_LOG_TCP_POS 0
59
60#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
61
62/* Link register */
63#define D40_DEACTIVATE_EVENTLINE 0x0
64#define D40_ACTIVATE_EVENTLINE 0x1
65#define D40_EVENTLINE_POS(i) (2 * i)
66#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
67
68/* Standard basic channel logical params in memory */
69
70/* LCSP0 */
71#define D40_MEM_LCSP0_ECNT_POS 16
72#define D40_MEM_LCSP0_SPTR_POS 0
73
74#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
75#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
76
77/* LCSP1 */
78#define D40_MEM_LCSP1_SPTR_POS 16
79#define D40_MEM_LCSP1_SCFG_MST_POS 15
80#define D40_MEM_LCSP1_SCFG_TIM_POS 14
81#define D40_MEM_LCSP1_SCFG_EIM_POS 13
82#define D40_MEM_LCSP1_SCFG_INCR_POS 12
83#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
84#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
85#define D40_MEM_LCSP1_SLOS_POS 1
86#define D40_MEM_LCSP1_STCP_POS 0
87
88#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
89#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
90#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
91#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
92#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
93#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
94
95/* LCSP2 */
96#define D40_MEM_LCSP2_ECNT_POS 16
97
98#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
99
100/* LCSP3 */
101#define D40_MEM_LCSP3_DCFG_MST_POS 15
102#define D40_MEM_LCSP3_DCFG_TIM_POS 14
103#define D40_MEM_LCSP3_DCFG_EIM_POS 13
104#define D40_MEM_LCSP3_DCFG_INCR_POS 12
105#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
106#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
107#define D40_MEM_LCSP3_DLOS_POS 1
108#define D40_MEM_LCSP3_DTCP_POS 0
109
110#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
111#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
112
113
114/* Standard channel parameter register offsets */
115#define D40_CHAN_REG_SSCFG 0x00
116#define D40_CHAN_REG_SSELT 0x04
117#define D40_CHAN_REG_SSPTR 0x08
118#define D40_CHAN_REG_SSLNK 0x0C
119#define D40_CHAN_REG_SDCFG 0x10
120#define D40_CHAN_REG_SDELT 0x14
121#define D40_CHAN_REG_SDPTR 0x18
122#define D40_CHAN_REG_SDLNK 0x1C
123
124/* DMA Register Offsets */
125#define D40_DREG_GCC 0x000
126#define D40_DREG_PRTYP 0x004
127#define D40_DREG_PRSME 0x008
128#define D40_DREG_PRSMO 0x00C
129#define D40_DREG_PRMSE 0x010
130#define D40_DREG_PRMSO 0x014
131#define D40_DREG_PRMOE 0x018
132#define D40_DREG_PRMOO 0x01C
133#define D40_DREG_PRMO_PCHAN_BASIC 0x1
134#define D40_DREG_PRMO_PCHAN_MODULO 0x2
135#define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
136#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
137#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
138#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
139
140#define D40_DREG_LCPA 0x020
141#define D40_DREG_LCLA 0x024
142#define D40_DREG_ACTIVE 0x050
143#define D40_DREG_ACTIVO 0x054
144#define D40_DREG_FSEB1 0x058
145#define D40_DREG_FSEB2 0x05C
146#define D40_DREG_PCMIS 0x060
147#define D40_DREG_PCICR 0x064
148#define D40_DREG_PCTIS 0x068
149#define D40_DREG_PCEIS 0x06C
150#define D40_DREG_LCMIS0 0x080
151#define D40_DREG_LCMIS1 0x084
152#define D40_DREG_LCMIS2 0x088
153#define D40_DREG_LCMIS3 0x08C
154#define D40_DREG_LCICR0 0x090
155#define D40_DREG_LCICR1 0x094
156#define D40_DREG_LCICR2 0x098
157#define D40_DREG_LCICR3 0x09C
158#define D40_DREG_LCTIS0 0x0A0
159#define D40_DREG_LCTIS1 0x0A4
160#define D40_DREG_LCTIS2 0x0A8
161#define D40_DREG_LCTIS3 0x0AC
162#define D40_DREG_LCEIS0 0x0B0
163#define D40_DREG_LCEIS1 0x0B4
164#define D40_DREG_LCEIS2 0x0B8
165#define D40_DREG_LCEIS3 0x0BC
166#define D40_DREG_STFU 0xFC8
167#define D40_DREG_ICFG 0xFCC
168#define D40_DREG_PERIPHID0 0xFE0
169#define D40_DREG_PERIPHID1 0xFE4
170#define D40_DREG_PERIPHID2 0xFE8
171#define D40_DREG_PERIPHID2_REV_POS 4
172#define D40_DREG_PERIPHID2_REV_MASK (0xf << D40_DREG_PERIPHID2_REV_POS)
173#define D40_DREG_PERIPHID2_DESIGNER_MASK 0xf
174#define D40_DREG_PERIPHID3 0xFEC
175#define D40_DREG_CELLID0 0xFF0
176#define D40_DREG_CELLID1 0xFF4
177#define D40_DREG_CELLID2 0xFF8
178#define D40_DREG_CELLID3 0xFFC
179
180/* LLI related structures */
181
182/**
183 * struct d40_phy_lli - The basic configration register for each physical
184 * channel.
185 *
186 * @reg_cfg: The configuration register.
187 * @reg_elt: The element register.
188 * @reg_ptr: The pointer register.
189 * @reg_lnk: The link register.
190 *
191 * These registers are set up for both physical and logical transfers
192 * Note that the bit in each register means differently in logical and
193 * physical(standard) mode.
194 *
195 * This struct must be 16 bytes aligned, and only contain physical registers
196 * since it will be directly accessed by the DMA.
197 */
198struct d40_phy_lli {
199 u32 reg_cfg;
200 u32 reg_elt;
201 u32 reg_ptr;
202 u32 reg_lnk;
203};
204
205/**
206 * struct d40_phy_lli_bidir - struct for a transfer.
207 *
208 * @src: Register settings for src channel.
209 * @dst: Register settings for dst channel.
210 *
211 * All DMA transfers have a source and a destination.
212 */
213
214struct d40_phy_lli_bidir {
215 struct d40_phy_lli *src;
216 struct d40_phy_lli *dst;
217};
218
219
220/**
221 * struct d40_log_lli - logical lli configuration
222 *
223 * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
224 * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
225 *
226 * This struct must be 8 bytes aligned since it will be accessed directy by
227 * the DMA. Never add any none hw mapped registers to this struct.
228 */
229
230struct d40_log_lli {
231 u32 lcsp02;
232 u32 lcsp13;
233};
234
235/**
236 * struct d40_log_lli_bidir - For both src and dst
237 *
238 * @src: pointer to src lli configuration.
239 * @dst: pointer to dst lli configuration.
240 *
241 * You always have a src and a dst when doing DMA transfers.
242 */
243
244struct d40_log_lli_bidir {
245 struct d40_log_lli *src;
246 struct d40_log_lli *dst;
247};
248
249/**
250 * struct d40_log_lli_full - LCPA layout
251 *
252 * @lcsp0: Logical Channel Standard Param 0 - Src.
253 * @lcsp1: Logical Channel Standard Param 1 - Src.
254 * @lcsp2: Logical Channel Standard Param 2 - Dst.
255 * @lcsp3: Logical Channel Standard Param 3 - Dst.
256 *
257 * This struct maps to LCPA physical memory layout. Must map to
258 * the hw.
259 */
260struct d40_log_lli_full {
261 u32 lcsp0;
262 u32 lcsp1;
263 u32 lcsp2;
264 u32 lcsp3;
265};
266
267/**
268 * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
269 *
270 * @lcsp3: The default configuration for dst.
271 * @lcsp1: The default configuration for src.
272 */
273struct d40_def_lcsp {
274 u32 lcsp3;
275 u32 lcsp1;
276};
277
278/* Physical channels */
279
280void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
281 u32 *src_cfg,
282 u32 *dst_cfg,
283 bool is_log);
284
285void d40_log_cfg(struct stedma40_chan_cfg *cfg,
286 u32 *lcsp1,
287 u32 *lcsp2);
288
289int d40_phy_sg_to_lli(struct scatterlist *sg,
290 int sg_len,
291 dma_addr_t target,
292 struct d40_phy_lli *lli,
293 dma_addr_t lli_phys,
294 u32 reg_cfg,
295 u32 data_width1,
296 u32 data_width2,
297 int psize);
298
299struct d40_phy_lli *d40_phy_buf_to_lli(struct d40_phy_lli *lli,
300 dma_addr_t data,
301 u32 data_size,
302 int psize,
303 dma_addr_t next_lli,
304 u32 reg_cfg,
305 bool term_int,
306 u32 data_width1,
307 u32 data_width2,
308 bool is_device);
309
310void d40_phy_lli_write(void __iomem *virtbase,
311 u32 phy_chan_num,
312 struct d40_phy_lli *lli_dst,
313 struct d40_phy_lli *lli_src);
314
315/* Logical channels */
316
317struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
318 dma_addr_t addr,
319 int size,
320 u32 lcsp13, /* src or dst*/
321 u32 data_width1, u32 data_width2,
322 bool addr_inc);
323
324int d40_log_sg_to_dev(struct scatterlist *sg,
325 int sg_len,
326 struct d40_log_lli_bidir *lli,
327 struct d40_def_lcsp *lcsp,
328 u32 src_data_width,
329 u32 dst_data_width,
330 enum dma_data_direction direction,
331 dma_addr_t dev_addr);
332
333int d40_log_sg_to_lli(struct scatterlist *sg,
334 int sg_len,
335 struct d40_log_lli *lli_sg,
336 u32 lcsp13, /* src or dst*/
337 u32 data_width1, u32 data_width2);
338
339void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
340 struct d40_log_lli *lli_dst,
341 struct d40_log_lli *lli_src,
342 int next);
343
344void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
345 struct d40_log_lli *lli_dst,
346 struct d40_log_lli *lli_src,
347 int next);
348
349#endif /* STE_DMA40_LLI_H */