tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_PHY_H_
29#define _IXGBE_PHY_H_
30
31#include "ixgbe_type.h"
32#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
33
34/* EEPROM byte offsets */
35#define IXGBE_SFF_IDENTIFIER 0x0
36#define IXGBE_SFF_IDENTIFIER_SFP 0x3
37#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
38#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
39#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
40#define IXGBE_SFF_1GBE_COMP_CODES 0x6
41#define IXGBE_SFF_10GBE_COMP_CODES 0x3
42#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
43#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
44
45/* Bitmasks */
46#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
47#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
48#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
49#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
50#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
51#define IXGBE_SFF_1GBASET_CAPABLE 0x8
52#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
53#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
54#define IXGBE_I2C_EEPROM_READ_MASK 0x100
55#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
56#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
57#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
58#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
59#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
60
61/* Bit-shift macros */
62#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
63#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
64#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
65
66/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
67#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
68#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
69#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
70#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
71
72/* I2C SDA and SCL timing parameters for standard mode */
73#define IXGBE_I2C_T_HD_STA 4
74#define IXGBE_I2C_T_LOW 5
75#define IXGBE_I2C_T_HIGH 4
76#define IXGBE_I2C_T_SU_STA 5
77#define IXGBE_I2C_T_HD_DATA 5
78#define IXGBE_I2C_T_SU_DATA 1
79#define IXGBE_I2C_T_RISE 1
80#define IXGBE_I2C_T_FALL 1
81#define IXGBE_I2C_T_SU_STO 4
82#define IXGBE_I2C_T_BUF 5
83
84#define IXGBE_TN_LASI_STATUS_REG 0x9005
85#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
86
87s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
88s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
89s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
90s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
91 u32 device_type, u16 *phy_data);
92s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
93 u32 device_type, u16 phy_data);
94s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
95s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
96 ixgbe_link_speed speed,
97 bool autoneg,
98 bool autoneg_wait_to_complete);
99
100/* PHY specific */
101s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
102 ixgbe_link_speed *speed,
103 bool *link_up);
104s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
105 u16 *firmware_version);
106
107s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
108s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
109s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
110 u16 *list_offset,
111 u16 *data_offset);
112s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
113s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
114 u8 dev_addr, u8 *data);
115s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
116 u8 dev_addr, u8 data);
117s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
118 u8 *eeprom_data);
119s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
120 u8 eeprom_data);
121#endif /* _IXGBE_PHY_H_ */