Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SYSTEM_H
16#define _ASM_TILE_SYSTEM_H
17
18#ifndef __ASSEMBLY__
19
20#include <linux/types.h>
21#include <linux/irqflags.h>
22
23/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */
24#include <asm/ptrace.h>
25
26#include <arch/chip.h>
27#include <arch/sim_def.h>
28#include <arch/spr_def.h>
29
30/*
31 * read_barrier_depends - Flush all pending reads that subsequents reads
32 * depend on.
33 *
34 * No data-dependent reads from memory-like regions are ever reordered
35 * over this barrier. All reads preceding this primitive are guaranteed
36 * to access memory (but not necessarily other CPUs' caches) before any
37 * reads following this primitive that depend on the data return by
38 * any of the preceding reads. This primitive is much lighter weight than
39 * rmb() on most CPUs, and is never heavier weight than is
40 * rmb().
41 *
42 * These ordering constraints are respected by both the local CPU
43 * and the compiler.
44 *
45 * Ordering is not guaranteed by anything other than these primitives,
46 * not even by data dependencies. See the documentation for
47 * memory_barrier() for examples and URLs to more information.
48 *
49 * For example, the following code would force ordering (the initial
50 * value of "a" is zero, "b" is one, and "p" is "&a"):
51 *
52 * <programlisting>
53 * CPU 0 CPU 1
54 *
55 * b = 2;
56 * memory_barrier();
57 * p = &b; q = p;
58 * read_barrier_depends();
59 * d = *q;
60 * </programlisting>
61 *
62 * because the read of "*q" depends on the read of "p" and these
63 * two reads are separated by a read_barrier_depends(). However,
64 * the following code, with the same initial values for "a" and "b":
65 *
66 * <programlisting>
67 * CPU 0 CPU 1
68 *
69 * a = 2;
70 * memory_barrier();
71 * b = 3; y = b;
72 * read_barrier_depends();
73 * x = a;
74 * </programlisting>
75 *
76 * does not enforce ordering, since there is no data dependency between
77 * the read of "a" and the read of "b". Therefore, on some CPUs, such
78 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
79 * in cases like this where there are no data dependencies.
80 */
81
82#define read_barrier_depends() do { } while (0)
83
84#define __sync() __insn_mf()
85
86#if CHIP_HAS_SPLIT_CYCLE()
87#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
88#else
89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
90#endif
91
92#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
93int __mb_incoherent(void); /* Helper routine for mb_incoherent(). */
94#endif
95
96/* Fence to guarantee visibility of stores to incoherent memory. */
97static inline void
98mb_incoherent(void)
99{
100 __insn_mf();
101
102#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
103 {
104#if CHIP_HAS_TILE_WRITE_PENDING()
105 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
106 unsigned long start = get_cycles_low();
107 do {
108 if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
109 return;
110 } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
111#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
112 (void) __mb_incoherent();
113 }
114#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
115}
116
117#define fast_wmb() __sync()
118#define fast_rmb() __sync()
119#define fast_mb() __sync()
120#define fast_iob() mb_incoherent()
121
122#define wmb() fast_wmb()
123#define rmb() fast_rmb()
124#define mb() fast_mb()
125#define iob() fast_iob()
126
127#ifdef CONFIG_SMP
128#define smp_mb() mb()
129#define smp_rmb() rmb()
130#define smp_wmb() wmb()
131#define smp_read_barrier_depends() read_barrier_depends()
132#else
133#define smp_mb() barrier()
134#define smp_rmb() barrier()
135#define smp_wmb() barrier()
136#define smp_read_barrier_depends() do { } while (0)
137#endif
138
139#define set_mb(var, value) \
140 do { var = value; mb(); } while (0)
141
142/*
143 * Pause the DMA engine and static network before task switching.
144 */
145#define prepare_arch_switch(next) _prepare_arch_switch(next)
146void _prepare_arch_switch(struct task_struct *next);
147
148
149/*
150 * switch_to(n) should switch tasks to task nr n, first
151 * checking that n isn't the current task, in which case it does nothing.
152 * The number of callee-saved registers saved on the kernel stack
153 * is defined here for use in copy_thread() and must agree with __switch_to().
154 */
155#endif /* !__ASSEMBLY__ */
156#define CALLEE_SAVED_FIRST_REG 30
157#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
158#ifndef __ASSEMBLY__
159struct task_struct;
160#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
161extern struct task_struct *_switch_to(struct task_struct *prev,
162 struct task_struct *next);
163
164/* Helper function for _switch_to(). */
165extern struct task_struct *__switch_to(struct task_struct *prev,
166 struct task_struct *next,
167 unsigned long new_system_save_k_0);
168
169/* Address that switched-away from tasks are at. */
170extern unsigned long get_switch_to_pc(void);
171
172/*
173 * On SMP systems, when the scheduler does migration-cost autodetection,
174 * it needs a way to flush as much of the CPU's caches as possible:
175 *
176 * TODO: fill this in!
177 */
178static inline void sched_cacheflush(void)
179{
180}
181
182#define arch_align_stack(x) (x)
183
184/*
185 * Is the kernel doing fixups of unaligned accesses? If <0, no kernel
186 * intervention occurs and SIGBUS is delivered with no data address
187 * info. If 0, the kernel single-steps the instruction to discover
188 * the data address to provide with the SIGBUS. If 1, the kernel does
189 * a fixup.
190 */
191extern int unaligned_fixup;
192
193/* Is the kernel printing on each unaligned fixup? */
194extern int unaligned_printk;
195
196/* Number of unaligned fixups performed */
197extern unsigned int unaligned_fixup_count;
198
199/* Init-time routine to do tile-specific per-cpu setup. */
200void setup_cpu(int boot);
201
202/* User-level DMA management functions */
203void grant_dma_mpls(void);
204void restrict_dma_mpls(void);
205
206#ifdef CONFIG_HARDWALL
207/* User-level network management functions */
208void reset_network_state(void);
209void grant_network_mpls(void);
210void restrict_network_mpls(void);
211int hardwall_deactivate(struct task_struct *task);
212
213/* Hook hardwall code into changes in affinity. */
214#define arch_set_cpus_allowed(p, new_mask) do { \
215 if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
216 hardwall_deactivate(p); \
217} while (0)
218#endif
219
220/*
221 * Kernel threads can check to see if they need to migrate their
222 * stack whenever they return from a context switch; for user
223 * threads, we defer until they are returning to user-space.
224 */
225#define finish_arch_switch(prev) do { \
226 if (unlikely((prev)->state == TASK_DEAD)) \
227 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
228 ((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
229 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
230 (current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
231 if (current->mm == NULL && !kstack_hash && \
232 current_thread_info()->homecache_cpu != smp_processor_id()) \
233 homecache_migrate_kthread(); \
234} while (0)
235
236/* Support function for forking a new task. */
237void ret_from_fork(void);
238
239/* Called from ret_from_fork() when a new process starts up. */
240struct task_struct *sim_notify_fork(struct task_struct *prev);
241
242#endif /* !__ASSEMBLY__ */
243
244#endif /* _ASM_TILE_SYSTEM_H */