tjh.dev / kernel
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kernel / drivers / net / ucc_geth.c
at v2.6.37-rc5 4026 lines 122 kB view raw
1/* 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Gigabit Ethernet Driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15#include <linux/kernel.h> 16#include <linux/init.h> 17#include <linux/errno.h> 18#include <linux/slab.h> 19#include <linux/stddef.h> 20#include <linux/interrupt.h> 21#include <linux/netdevice.h> 22#include <linux/etherdevice.h> 23#include <linux/skbuff.h> 24#include <linux/spinlock.h> 25#include <linux/mm.h> 26#include <linux/dma-mapping.h> 27#include <linux/mii.h> 28#include <linux/phy.h> 29#include <linux/workqueue.h> 30#include <linux/of_mdio.h> 31#include <linux/of_platform.h> 32 33#include <asm/uaccess.h> 34#include <asm/irq.h> 35#include <asm/io.h> 36#include <asm/immap_qe.h> 37#include <asm/qe.h> 38#include <asm/ucc.h> 39#include <asm/ucc_fast.h> 40#include <asm/machdep.h> 41 42#include "ucc_geth.h" 43#include "fsl_pq_mdio.h" 44 45#undef DEBUG 46 47#define ugeth_printk(level, format, arg...) \ 48 printk(level format "\n", ## arg) 49 50#define ugeth_dbg(format, arg...) \ 51 ugeth_printk(KERN_DEBUG , format , ## arg) 52#define ugeth_err(format, arg...) \ 53 ugeth_printk(KERN_ERR , format , ## arg) 54#define ugeth_info(format, arg...) \ 55 ugeth_printk(KERN_INFO , format , ## arg) 56#define ugeth_warn(format, arg...) \ 57 ugeth_printk(KERN_WARNING , format , ## arg) 58 59#ifdef UGETH_VERBOSE_DEBUG 60#define ugeth_vdbg ugeth_dbg 61#else 62#define ugeth_vdbg(fmt, args...) do { } while (0) 63#endif /* UGETH_VERBOSE_DEBUG */ 64#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 65 66 67static DEFINE_SPINLOCK(ugeth_lock); 68 69static struct { 70 u32 msg_enable; 71} debug = { -1 }; 72 73module_param_named(debug, debug.msg_enable, int, 0); 74MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 75 76static struct ucc_geth_info ugeth_primary_info = { 77 .uf_info = { 78 .bd_mem_part = MEM_PART_SYSTEM, 79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 80 .max_rx_buf_length = 1536, 81 /* adjusted at startup if max-speed 1000 */ 82 .urfs = UCC_GETH_URFS_INIT, 83 .urfet = UCC_GETH_URFET_INIT, 84 .urfset = UCC_GETH_URFSET_INIT, 85 .utfs = UCC_GETH_UTFS_INIT, 86 .utfet = UCC_GETH_UTFET_INIT, 87 .utftt = UCC_GETH_UTFTT_INIT, 88 .ufpt = 256, 89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 91 .tenc = UCC_FAST_TX_ENCODING_NRZ, 92 .renc = UCC_FAST_RX_ENCODING_NRZ, 93 .tcrc = UCC_FAST_16_BIT_CRC, 94 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 95 }, 96 .numQueuesTx = 1, 97 .numQueuesRx = 1, 98 .extendedFilteringChainPointer = ((uint32_t) NULL), 99 .typeorlen = 3072 /*1536 */ , 100 .nonBackToBackIfgPart1 = 0x40, 101 .nonBackToBackIfgPart2 = 0x60, 102 .miminumInterFrameGapEnforcement = 0x50, 103 .backToBackInterFrameGap = 0x60, 104 .mblinterval = 128, 105 .nortsrbytetime = 5, 106 .fracsiz = 1, 107 .strictpriorityq = 0xff, 108 .altBebTruncation = 0xa, 109 .excessDefer = 1, 110 .maxRetransmission = 0xf, 111 .collisionWindow = 0x37, 112 .receiveFlowControl = 1, 113 .transmitFlowControl = 1, 114 .maxGroupAddrInHash = 4, 115 .maxIndAddrInHash = 4, 116 .prel = 7, 117 .maxFrameLength = 1518, 118 .minFrameLength = 64, 119 .maxD1Length = 1520, 120 .maxD2Length = 1520, 121 .vlantype = 0x8100, 122 .ecamptr = ((uint32_t) NULL), 123 .eventRegMask = UCCE_OTHER, 124 .pausePeriod = 0xf000, 125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 126 .bdRingLenTx = { 127 TX_BD_RING_LEN, 128 TX_BD_RING_LEN, 129 TX_BD_RING_LEN, 130 TX_BD_RING_LEN, 131 TX_BD_RING_LEN, 132 TX_BD_RING_LEN, 133 TX_BD_RING_LEN, 134 TX_BD_RING_LEN}, 135 136 .bdRingLenRx = { 137 RX_BD_RING_LEN, 138 RX_BD_RING_LEN, 139 RX_BD_RING_LEN, 140 RX_BD_RING_LEN, 141 RX_BD_RING_LEN, 142 RX_BD_RING_LEN, 143 RX_BD_RING_LEN, 144 RX_BD_RING_LEN}, 145 146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 147 .largestexternallookupkeysize = 148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 161}; 162 163static struct ucc_geth_info ugeth_info[8]; 164 165#ifdef DEBUG 166static void mem_disp(u8 *addr, int size) 167{ 168 u8 *i; 169 int size16Aling = (size >> 4) << 4; 170 int size4Aling = (size >> 2) << 2; 171 int notAlign = 0; 172 if (size % 16) 173 notAlign = 1; 174 175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 176 printk("0x%08x: %08x %08x %08x %08x\r\n", 177 (u32) i, 178 *((u32 *) (i)), 179 *((u32 *) (i + 4)), 180 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 181 if (notAlign == 1) 182 printk("0x%08x: ", (u32) i); 183 for (; (u32) i < (u32) addr + size4Aling; i += 4) 184 printk("%08x ", *((u32 *) (i))); 185 for (; (u32) i < (u32) addr + size; i++) 186 printk("%02x", *((u8 *) (i))); 187 if (notAlign == 1) 188 printk("\r\n"); 189} 190#endif /* DEBUG */ 191 192static struct list_head *dequeue(struct list_head *lh) 193{ 194 unsigned long flags; 195 196 spin_lock_irqsave(&ugeth_lock, flags); 197 if (!list_empty(lh)) { 198 struct list_head *node = lh->next; 199 list_del(node); 200 spin_unlock_irqrestore(&ugeth_lock, flags); 201 return node; 202 } else { 203 spin_unlock_irqrestore(&ugeth_lock, flags); 204 return NULL; 205 } 206} 207 208static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 209 u8 __iomem *bd) 210{ 211 struct sk_buff *skb = NULL; 212 213 skb = __skb_dequeue(&ugeth->rx_recycle); 214 if (!skb) 215 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length + 216 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 217 if (skb == NULL) 218 return NULL; 219 220 /* We need the data buffer to be aligned properly. We will reserve 221 * as many bytes as needed to align the data properly 222 */ 223 skb_reserve(skb, 224 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 225 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 226 1))); 227 228 skb->dev = ugeth->ndev; 229 230 out_be32(&((struct qe_bd __iomem *)bd)->buf, 231 dma_map_single(ugeth->dev, 232 skb->data, 233 ugeth->ug_info->uf_info.max_rx_buf_length + 234 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 235 DMA_FROM_DEVICE)); 236 237 out_be32((u32 __iomem *)bd, 238 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 239 240 return skb; 241} 242 243static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 244{ 245 u8 __iomem *bd; 246 u32 bd_status; 247 struct sk_buff *skb; 248 int i; 249 250 bd = ugeth->p_rx_bd_ring[rxQ]; 251 i = 0; 252 253 do { 254 bd_status = in_be32((u32 __iomem *)bd); 255 skb = get_new_skb(ugeth, bd); 256 257 if (!skb) /* If can not allocate data buffer, 258 abort. Cleanup will be elsewhere */ 259 return -ENOMEM; 260 261 ugeth->rx_skbuff[rxQ][i] = skb; 262 263 /* advance the BD pointer */ 264 bd += sizeof(struct qe_bd); 265 i++; 266 } while (!(bd_status & R_W)); 267 268 return 0; 269} 270 271static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 272 u32 *p_start, 273 u8 num_entries, 274 u32 thread_size, 275 u32 thread_alignment, 276 unsigned int risc, 277 int skip_page_for_first_entry) 278{ 279 u32 init_enet_offset; 280 u8 i; 281 int snum; 282 283 for (i = 0; i < num_entries; i++) { 284 if ((snum = qe_get_snum()) < 0) { 285 if (netif_msg_ifup(ugeth)) 286 ugeth_err("fill_init_enet_entries: Can not get SNUM."); 287 return snum; 288 } 289 if ((i == 0) && skip_page_for_first_entry) 290 /* First entry of Rx does not have page */ 291 init_enet_offset = 0; 292 else { 293 init_enet_offset = 294 qe_muram_alloc(thread_size, thread_alignment); 295 if (IS_ERR_VALUE(init_enet_offset)) { 296 if (netif_msg_ifup(ugeth)) 297 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory."); 298 qe_put_snum((u8) snum); 299 return -ENOMEM; 300 } 301 } 302 *(p_start++) = 303 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 304 | risc; 305 } 306 307 return 0; 308} 309 310static int return_init_enet_entries(struct ucc_geth_private *ugeth, 311 u32 *p_start, 312 u8 num_entries, 313 unsigned int risc, 314 int skip_page_for_first_entry) 315{ 316 u32 init_enet_offset; 317 u8 i; 318 int snum; 319 320 for (i = 0; i < num_entries; i++) { 321 u32 val = *p_start; 322 323 /* Check that this entry was actually valid -- 324 needed in case failed in allocations */ 325 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 326 snum = 327 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 328 ENET_INIT_PARAM_SNUM_SHIFT; 329 qe_put_snum((u8) snum); 330 if (!((i == 0) && skip_page_for_first_entry)) { 331 /* First entry of Rx does not have page */ 332 init_enet_offset = 333 (val & ENET_INIT_PARAM_PTR_MASK); 334 qe_muram_free(init_enet_offset); 335 } 336 *p_start++ = 0; 337 } 338 } 339 340 return 0; 341} 342 343#ifdef DEBUG 344static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 345 u32 __iomem *p_start, 346 u8 num_entries, 347 u32 thread_size, 348 unsigned int risc, 349 int skip_page_for_first_entry) 350{ 351 u32 init_enet_offset; 352 u8 i; 353 int snum; 354 355 for (i = 0; i < num_entries; i++) { 356 u32 val = in_be32(p_start); 357 358 /* Check that this entry was actually valid -- 359 needed in case failed in allocations */ 360 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 361 snum = 362 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 363 ENET_INIT_PARAM_SNUM_SHIFT; 364 qe_put_snum((u8) snum); 365 if (!((i == 0) && skip_page_for_first_entry)) { 366 /* First entry of Rx does not have page */ 367 init_enet_offset = 368 (in_be32(p_start) & 369 ENET_INIT_PARAM_PTR_MASK); 370 ugeth_info("Init enet entry %d:", i); 371 ugeth_info("Base address: 0x%08x", 372 (u32) 373 qe_muram_addr(init_enet_offset)); 374 mem_disp(qe_muram_addr(init_enet_offset), 375 thread_size); 376 } 377 p_start++; 378 } 379 } 380 381 return 0; 382} 383#endif 384 385static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 386{ 387 kfree(enet_addr_cont); 388} 389 390static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 391{ 392 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]); 393 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]); 394 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]); 395} 396 397static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 398{ 399 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 400 401 if (!(paddr_num < NUM_OF_PADDRS)) { 402 ugeth_warn("%s: Illagel paddr_num.", __func__); 403 return -EINVAL; 404 } 405 406 p_82xx_addr_filt = 407 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 408 addressfiltering; 409 410 /* Writing address ff.ff.ff.ff.ff.ff disables address 411 recognition for this register */ 412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 413 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 414 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 415 416 return 0; 417} 418 419static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 420 u8 *p_enet_addr) 421{ 422 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 423 u32 cecr_subblock; 424 425 p_82xx_addr_filt = 426 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 427 addressfiltering; 428 429 cecr_subblock = 430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 431 432 /* Ethernet frames are defined in Little Endian mode, 433 therefore to insert */ 434 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 435 436 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 437 438 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 439 QE_CR_PROTOCOL_ETHERNET, 0); 440} 441 442static inline int compare_addr(u8 **addr1, u8 **addr2) 443{ 444 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS); 445} 446 447#ifdef DEBUG 448static void get_statistics(struct ucc_geth_private *ugeth, 449 struct ucc_geth_tx_firmware_statistics * 450 tx_firmware_statistics, 451 struct ucc_geth_rx_firmware_statistics * 452 rx_firmware_statistics, 453 struct ucc_geth_hardware_statistics *hardware_statistics) 454{ 455 struct ucc_fast __iomem *uf_regs; 456 struct ucc_geth __iomem *ug_regs; 457 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 458 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 459 460 ug_regs = ugeth->ug_regs; 461 uf_regs = (struct ucc_fast __iomem *) ug_regs; 462 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 463 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 464 465 /* Tx firmware only if user handed pointer and driver actually 466 gathers Tx firmware statistics */ 467 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 468 tx_firmware_statistics->sicoltx = 469 in_be32(&p_tx_fw_statistics_pram->sicoltx); 470 tx_firmware_statistics->mulcoltx = 471 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 472 tx_firmware_statistics->latecoltxfr = 473 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 474 tx_firmware_statistics->frabortduecol = 475 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 476 tx_firmware_statistics->frlostinmactxer = 477 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 478 tx_firmware_statistics->carriersenseertx = 479 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 480 tx_firmware_statistics->frtxok = 481 in_be32(&p_tx_fw_statistics_pram->frtxok); 482 tx_firmware_statistics->txfrexcessivedefer = 483 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 484 tx_firmware_statistics->txpkts256 = 485 in_be32(&p_tx_fw_statistics_pram->txpkts256); 486 tx_firmware_statistics->txpkts512 = 487 in_be32(&p_tx_fw_statistics_pram->txpkts512); 488 tx_firmware_statistics->txpkts1024 = 489 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 490 tx_firmware_statistics->txpktsjumbo = 491 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 492 } 493 494 /* Rx firmware only if user handed pointer and driver actually 495 * gathers Rx firmware statistics */ 496 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 497 int i; 498 rx_firmware_statistics->frrxfcser = 499 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 500 rx_firmware_statistics->fraligner = 501 in_be32(&p_rx_fw_statistics_pram->fraligner); 502 rx_firmware_statistics->inrangelenrxer = 503 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 504 rx_firmware_statistics->outrangelenrxer = 505 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 506 rx_firmware_statistics->frtoolong = 507 in_be32(&p_rx_fw_statistics_pram->frtoolong); 508 rx_firmware_statistics->runt = 509 in_be32(&p_rx_fw_statistics_pram->runt); 510 rx_firmware_statistics->verylongevent = 511 in_be32(&p_rx_fw_statistics_pram->verylongevent); 512 rx_firmware_statistics->symbolerror = 513 in_be32(&p_rx_fw_statistics_pram->symbolerror); 514 rx_firmware_statistics->dropbsy = 515 in_be32(&p_rx_fw_statistics_pram->dropbsy); 516 for (i = 0; i < 0x8; i++) 517 rx_firmware_statistics->res0[i] = 518 p_rx_fw_statistics_pram->res0[i]; 519 rx_firmware_statistics->mismatchdrop = 520 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 521 rx_firmware_statistics->underpkts = 522 in_be32(&p_rx_fw_statistics_pram->underpkts); 523 rx_firmware_statistics->pkts256 = 524 in_be32(&p_rx_fw_statistics_pram->pkts256); 525 rx_firmware_statistics->pkts512 = 526 in_be32(&p_rx_fw_statistics_pram->pkts512); 527 rx_firmware_statistics->pkts1024 = 528 in_be32(&p_rx_fw_statistics_pram->pkts1024); 529 rx_firmware_statistics->pktsjumbo = 530 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 531 rx_firmware_statistics->frlossinmacer = 532 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 533 rx_firmware_statistics->pausefr = 534 in_be32(&p_rx_fw_statistics_pram->pausefr); 535 for (i = 0; i < 0x4; i++) 536 rx_firmware_statistics->res1[i] = 537 p_rx_fw_statistics_pram->res1[i]; 538 rx_firmware_statistics->removevlan = 539 in_be32(&p_rx_fw_statistics_pram->removevlan); 540 rx_firmware_statistics->replacevlan = 541 in_be32(&p_rx_fw_statistics_pram->replacevlan); 542 rx_firmware_statistics->insertvlan = 543 in_be32(&p_rx_fw_statistics_pram->insertvlan); 544 } 545 546 /* Hardware only if user handed pointer and driver actually 547 gathers hardware statistics */ 548 if (hardware_statistics && 549 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 550 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 551 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 552 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 553 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 554 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 555 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 556 hardware_statistics->txok = in_be32(&ug_regs->txok); 557 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 558 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 559 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 560 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 561 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 562 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 563 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 564 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 565 } 566} 567 568static void dump_bds(struct ucc_geth_private *ugeth) 569{ 570 int i; 571 int length; 572 573 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 574 if (ugeth->p_tx_bd_ring[i]) { 575 length = 576 (ugeth->ug_info->bdRingLenTx[i] * 577 sizeof(struct qe_bd)); 578 ugeth_info("TX BDs[%d]", i); 579 mem_disp(ugeth->p_tx_bd_ring[i], length); 580 } 581 } 582 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 583 if (ugeth->p_rx_bd_ring[i]) { 584 length = 585 (ugeth->ug_info->bdRingLenRx[i] * 586 sizeof(struct qe_bd)); 587 ugeth_info("RX BDs[%d]", i); 588 mem_disp(ugeth->p_rx_bd_ring[i], length); 589 } 590 } 591} 592 593static void dump_regs(struct ucc_geth_private *ugeth) 594{ 595 int i; 596 597 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num + 1); 598 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs); 599 600 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x", 601 (u32) & ugeth->ug_regs->maccfg1, 602 in_be32(&ugeth->ug_regs->maccfg1)); 603 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x", 604 (u32) & ugeth->ug_regs->maccfg2, 605 in_be32(&ugeth->ug_regs->maccfg2)); 606 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x", 607 (u32) & ugeth->ug_regs->ipgifg, 608 in_be32(&ugeth->ug_regs->ipgifg)); 609 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x", 610 (u32) & ugeth->ug_regs->hafdup, 611 in_be32(&ugeth->ug_regs->hafdup)); 612 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x", 613 (u32) & ugeth->ug_regs->ifctl, 614 in_be32(&ugeth->ug_regs->ifctl)); 615 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x", 616 (u32) & ugeth->ug_regs->ifstat, 617 in_be32(&ugeth->ug_regs->ifstat)); 618 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x", 619 (u32) & ugeth->ug_regs->macstnaddr1, 620 in_be32(&ugeth->ug_regs->macstnaddr1)); 621 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x", 622 (u32) & ugeth->ug_regs->macstnaddr2, 623 in_be32(&ugeth->ug_regs->macstnaddr2)); 624 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x", 625 (u32) & ugeth->ug_regs->uempr, 626 in_be32(&ugeth->ug_regs->uempr)); 627 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x", 628 (u32) & ugeth->ug_regs->utbipar, 629 in_be32(&ugeth->ug_regs->utbipar)); 630 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x", 631 (u32) & ugeth->ug_regs->uescr, 632 in_be16(&ugeth->ug_regs->uescr)); 633 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x", 634 (u32) & ugeth->ug_regs->tx64, 635 in_be32(&ugeth->ug_regs->tx64)); 636 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x", 637 (u32) & ugeth->ug_regs->tx127, 638 in_be32(&ugeth->ug_regs->tx127)); 639 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x", 640 (u32) & ugeth->ug_regs->tx255, 641 in_be32(&ugeth->ug_regs->tx255)); 642 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x", 643 (u32) & ugeth->ug_regs->rx64, 644 in_be32(&ugeth->ug_regs->rx64)); 645 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x", 646 (u32) & ugeth->ug_regs->rx127, 647 in_be32(&ugeth->ug_regs->rx127)); 648 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x", 649 (u32) & ugeth->ug_regs->rx255, 650 in_be32(&ugeth->ug_regs->rx255)); 651 ugeth_info("txok : addr - 0x%08x, val - 0x%08x", 652 (u32) & ugeth->ug_regs->txok, 653 in_be32(&ugeth->ug_regs->txok)); 654 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x", 655 (u32) & ugeth->ug_regs->txcf, 656 in_be16(&ugeth->ug_regs->txcf)); 657 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x", 658 (u32) & ugeth->ug_regs->tmca, 659 in_be32(&ugeth->ug_regs->tmca)); 660 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x", 661 (u32) & ugeth->ug_regs->tbca, 662 in_be32(&ugeth->ug_regs->tbca)); 663 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x", 664 (u32) & ugeth->ug_regs->rxfok, 665 in_be32(&ugeth->ug_regs->rxfok)); 666 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x", 667 (u32) & ugeth->ug_regs->rxbok, 668 in_be32(&ugeth->ug_regs->rxbok)); 669 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x", 670 (u32) & ugeth->ug_regs->rbyt, 671 in_be32(&ugeth->ug_regs->rbyt)); 672 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x", 673 (u32) & ugeth->ug_regs->rmca, 674 in_be32(&ugeth->ug_regs->rmca)); 675 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x", 676 (u32) & ugeth->ug_regs->rbca, 677 in_be32(&ugeth->ug_regs->rbca)); 678 ugeth_info("scar : addr - 0x%08x, val - 0x%08x", 679 (u32) & ugeth->ug_regs->scar, 680 in_be32(&ugeth->ug_regs->scar)); 681 ugeth_info("scam : addr - 0x%08x, val - 0x%08x", 682 (u32) & ugeth->ug_regs->scam, 683 in_be32(&ugeth->ug_regs->scam)); 684 685 if (ugeth->p_thread_data_tx) { 686 int numThreadsTxNumerical; 687 switch (ugeth->ug_info->numThreadsTx) { 688 case UCC_GETH_NUM_OF_THREADS_1: 689 numThreadsTxNumerical = 1; 690 break; 691 case UCC_GETH_NUM_OF_THREADS_2: 692 numThreadsTxNumerical = 2; 693 break; 694 case UCC_GETH_NUM_OF_THREADS_4: 695 numThreadsTxNumerical = 4; 696 break; 697 case UCC_GETH_NUM_OF_THREADS_6: 698 numThreadsTxNumerical = 6; 699 break; 700 case UCC_GETH_NUM_OF_THREADS_8: 701 numThreadsTxNumerical = 8; 702 break; 703 default: 704 numThreadsTxNumerical = 0; 705 break; 706 } 707 708 ugeth_info("Thread data TXs:"); 709 ugeth_info("Base address: 0x%08x", 710 (u32) ugeth->p_thread_data_tx); 711 for (i = 0; i < numThreadsTxNumerical; i++) { 712 ugeth_info("Thread data TX[%d]:", i); 713 ugeth_info("Base address: 0x%08x", 714 (u32) & ugeth->p_thread_data_tx[i]); 715 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 716 sizeof(struct ucc_geth_thread_data_tx)); 717 } 718 } 719 if (ugeth->p_thread_data_rx) { 720 int numThreadsRxNumerical; 721 switch (ugeth->ug_info->numThreadsRx) { 722 case UCC_GETH_NUM_OF_THREADS_1: 723 numThreadsRxNumerical = 1; 724 break; 725 case UCC_GETH_NUM_OF_THREADS_2: 726 numThreadsRxNumerical = 2; 727 break; 728 case UCC_GETH_NUM_OF_THREADS_4: 729 numThreadsRxNumerical = 4; 730 break; 731 case UCC_GETH_NUM_OF_THREADS_6: 732 numThreadsRxNumerical = 6; 733 break; 734 case UCC_GETH_NUM_OF_THREADS_8: 735 numThreadsRxNumerical = 8; 736 break; 737 default: 738 numThreadsRxNumerical = 0; 739 break; 740 } 741 742 ugeth_info("Thread data RX:"); 743 ugeth_info("Base address: 0x%08x", 744 (u32) ugeth->p_thread_data_rx); 745 for (i = 0; i < numThreadsRxNumerical; i++) { 746 ugeth_info("Thread data RX[%d]:", i); 747 ugeth_info("Base address: 0x%08x", 748 (u32) & ugeth->p_thread_data_rx[i]); 749 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 750 sizeof(struct ucc_geth_thread_data_rx)); 751 } 752 } 753 if (ugeth->p_exf_glbl_param) { 754 ugeth_info("EXF global param:"); 755 ugeth_info("Base address: 0x%08x", 756 (u32) ugeth->p_exf_glbl_param); 757 mem_disp((u8 *) ugeth->p_exf_glbl_param, 758 sizeof(*ugeth->p_exf_glbl_param)); 759 } 760 if (ugeth->p_tx_glbl_pram) { 761 ugeth_info("TX global param:"); 762 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram); 763 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x", 764 (u32) & ugeth->p_tx_glbl_pram->temoder, 765 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 766 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x", 767 (u32) & ugeth->p_tx_glbl_pram->sqptr, 768 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 769 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x", 770 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer, 771 in_be32(&ugeth->p_tx_glbl_pram-> 772 schedulerbasepointer)); 773 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x", 774 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr, 775 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 776 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x", 777 (u32) & ugeth->p_tx_glbl_pram->tstate, 778 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 779 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x", 780 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0], 781 ugeth->p_tx_glbl_pram->iphoffset[0]); 782 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x", 783 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1], 784 ugeth->p_tx_glbl_pram->iphoffset[1]); 785 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x", 786 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2], 787 ugeth->p_tx_glbl_pram->iphoffset[2]); 788 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x", 789 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3], 790 ugeth->p_tx_glbl_pram->iphoffset[3]); 791 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x", 792 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4], 793 ugeth->p_tx_glbl_pram->iphoffset[4]); 794 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x", 795 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5], 796 ugeth->p_tx_glbl_pram->iphoffset[5]); 797 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x", 798 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6], 799 ugeth->p_tx_glbl_pram->iphoffset[6]); 800 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x", 801 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7], 802 ugeth->p_tx_glbl_pram->iphoffset[7]); 803 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x", 804 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0], 805 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 806 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x", 807 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1], 808 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 809 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x", 810 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2], 811 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 812 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x", 813 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3], 814 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 815 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x", 816 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4], 817 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 818 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x", 819 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5], 820 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 821 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x", 822 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6], 823 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 824 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x", 825 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7], 826 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 827 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x", 828 (u32) & ugeth->p_tx_glbl_pram->tqptr, 829 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 830 } 831 if (ugeth->p_rx_glbl_pram) { 832 ugeth_info("RX global param:"); 833 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram); 834 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x", 835 (u32) & ugeth->p_rx_glbl_pram->remoder, 836 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 837 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x", 838 (u32) & ugeth->p_rx_glbl_pram->rqptr, 839 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 840 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x", 841 (u32) & ugeth->p_rx_glbl_pram->typeorlen, 842 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 843 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x", 844 (u32) & ugeth->p_rx_glbl_pram->rxgstpack, 845 ugeth->p_rx_glbl_pram->rxgstpack); 846 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x", 847 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr, 848 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 849 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x", 850 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr, 851 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 852 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x", 853 (u32) & ugeth->p_rx_glbl_pram->rstate, 854 ugeth->p_rx_glbl_pram->rstate); 855 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x", 856 (u32) & ugeth->p_rx_glbl_pram->mrblr, 857 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 858 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x", 859 (u32) & ugeth->p_rx_glbl_pram->rbdqptr, 860 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 861 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x", 862 (u32) & ugeth->p_rx_glbl_pram->mflr, 863 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 864 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x", 865 (u32) & ugeth->p_rx_glbl_pram->minflr, 866 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 867 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x", 868 (u32) & ugeth->p_rx_glbl_pram->maxd1, 869 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 870 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x", 871 (u32) & ugeth->p_rx_glbl_pram->maxd2, 872 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 873 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x", 874 (u32) & ugeth->p_rx_glbl_pram->ecamptr, 875 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 876 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x", 877 (u32) & ugeth->p_rx_glbl_pram->l2qt, 878 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 879 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x", 880 (u32) & ugeth->p_rx_glbl_pram->l3qt[0], 881 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 882 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x", 883 (u32) & ugeth->p_rx_glbl_pram->l3qt[1], 884 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 885 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x", 886 (u32) & ugeth->p_rx_glbl_pram->l3qt[2], 887 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 888 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x", 889 (u32) & ugeth->p_rx_glbl_pram->l3qt[3], 890 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 891 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x", 892 (u32) & ugeth->p_rx_glbl_pram->l3qt[4], 893 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 894 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x", 895 (u32) & ugeth->p_rx_glbl_pram->l3qt[5], 896 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 897 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x", 898 (u32) & ugeth->p_rx_glbl_pram->l3qt[6], 899 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 900 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x", 901 (u32) & ugeth->p_rx_glbl_pram->l3qt[7], 902 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 903 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x", 904 (u32) & ugeth->p_rx_glbl_pram->vlantype, 905 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 906 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x", 907 (u32) & ugeth->p_rx_glbl_pram->vlantci, 908 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 909 for (i = 0; i < 64; i++) 910 ugeth_info 911 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x", 912 i, 913 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i], 914 ugeth->p_rx_glbl_pram->addressfiltering[i]); 915 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x", 916 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam, 917 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 918 } 919 if (ugeth->p_send_q_mem_reg) { 920 ugeth_info("Send Q memory registers:"); 921 ugeth_info("Base address: 0x%08x", 922 (u32) ugeth->p_send_q_mem_reg); 923 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 924 ugeth_info("SQQD[%d]:", i); 925 ugeth_info("Base address: 0x%08x", 926 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]); 927 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 928 sizeof(struct ucc_geth_send_queue_qd)); 929 } 930 } 931 if (ugeth->p_scheduler) { 932 ugeth_info("Scheduler:"); 933 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler); 934 mem_disp((u8 *) ugeth->p_scheduler, 935 sizeof(*ugeth->p_scheduler)); 936 } 937 if (ugeth->p_tx_fw_statistics_pram) { 938 ugeth_info("TX FW statistics pram:"); 939 ugeth_info("Base address: 0x%08x", 940 (u32) ugeth->p_tx_fw_statistics_pram); 941 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 942 sizeof(*ugeth->p_tx_fw_statistics_pram)); 943 } 944 if (ugeth->p_rx_fw_statistics_pram) { 945 ugeth_info("RX FW statistics pram:"); 946 ugeth_info("Base address: 0x%08x", 947 (u32) ugeth->p_rx_fw_statistics_pram); 948 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 949 sizeof(*ugeth->p_rx_fw_statistics_pram)); 950 } 951 if (ugeth->p_rx_irq_coalescing_tbl) { 952 ugeth_info("RX IRQ coalescing tables:"); 953 ugeth_info("Base address: 0x%08x", 954 (u32) ugeth->p_rx_irq_coalescing_tbl); 955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 956 ugeth_info("RX IRQ coalescing table entry[%d]:", i); 957 ugeth_info("Base address: 0x%08x", 958 (u32) & ugeth->p_rx_irq_coalescing_tbl-> 959 coalescingentry[i]); 960 ugeth_info 961 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x", 962 (u32) & ugeth->p_rx_irq_coalescing_tbl-> 963 coalescingentry[i].interruptcoalescingmaxvalue, 964 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 965 coalescingentry[i]. 966 interruptcoalescingmaxvalue)); 967 ugeth_info 968 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x", 969 (u32) & ugeth->p_rx_irq_coalescing_tbl-> 970 coalescingentry[i].interruptcoalescingcounter, 971 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 972 coalescingentry[i]. 973 interruptcoalescingcounter)); 974 } 975 } 976 if (ugeth->p_rx_bd_qs_tbl) { 977 ugeth_info("RX BD QS tables:"); 978 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl); 979 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 980 ugeth_info("RX BD QS table[%d]:", i); 981 ugeth_info("Base address: 0x%08x", 982 (u32) & ugeth->p_rx_bd_qs_tbl[i]); 983 ugeth_info 984 ("bdbaseptr : addr - 0x%08x, val - 0x%08x", 985 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 986 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 987 ugeth_info 988 ("bdptr : addr - 0x%08x, val - 0x%08x", 989 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr, 990 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 991 ugeth_info 992 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x", 993 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 994 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 995 externalbdbaseptr)); 996 ugeth_info 997 ("externalbdptr : addr - 0x%08x, val - 0x%08x", 998 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 999 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 1000 ugeth_info("ucode RX Prefetched BDs:"); 1001 ugeth_info("Base address: 0x%08x", 1002 (u32) 1003 qe_muram_addr(in_be32 1004 (&ugeth->p_rx_bd_qs_tbl[i]. 1005 bdbaseptr))); 1006 mem_disp((u8 *) 1007 qe_muram_addr(in_be32 1008 (&ugeth->p_rx_bd_qs_tbl[i]. 1009 bdbaseptr)), 1010 sizeof(struct ucc_geth_rx_prefetched_bds)); 1011 } 1012 } 1013 if (ugeth->p_init_enet_param_shadow) { 1014 int size; 1015 ugeth_info("Init enet param shadow:"); 1016 ugeth_info("Base address: 0x%08x", 1017 (u32) ugeth->p_init_enet_param_shadow); 1018 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 1019 sizeof(*ugeth->p_init_enet_param_shadow)); 1020 1021 size = sizeof(struct ucc_geth_thread_rx_pram); 1022 if (ugeth->ug_info->rxExtendedFiltering) { 1023 size += 1024 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 1025 if (ugeth->ug_info->largestexternallookupkeysize == 1026 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 1027 size += 1028 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 1029 if (ugeth->ug_info->largestexternallookupkeysize == 1030 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 1031 size += 1032 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 1033 } 1034 1035 dump_init_enet_entries(ugeth, 1036 &(ugeth->p_init_enet_param_shadow-> 1037 txthread[0]), 1038 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1039 sizeof(struct ucc_geth_thread_tx_pram), 1040 ugeth->ug_info->riscTx, 0); 1041 dump_init_enet_entries(ugeth, 1042 &(ugeth->p_init_enet_param_shadow-> 1043 rxthread[0]), 1044 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1045 ugeth->ug_info->riscRx, 1); 1046 } 1047} 1048#endif /* DEBUG */ 1049 1050static void init_default_reg_vals(u32 __iomem *upsmr_register, 1051 u32 __iomem *maccfg1_register, 1052 u32 __iomem *maccfg2_register) 1053{ 1054 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1055 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1056 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1057} 1058 1059static int init_half_duplex_params(int alt_beb, 1060 int back_pressure_no_backoff, 1061 int no_backoff, 1062 int excess_defer, 1063 u8 alt_beb_truncation, 1064 u8 max_retransmissions, 1065 u8 collision_window, 1066 u32 __iomem *hafdup_register) 1067{ 1068 u32 value = 0; 1069 1070 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1071 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1072 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1073 return -EINVAL; 1074 1075 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1076 1077 if (alt_beb) 1078 value |= HALFDUP_ALT_BEB; 1079 if (back_pressure_no_backoff) 1080 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1081 if (no_backoff) 1082 value |= HALFDUP_NO_BACKOFF; 1083 if (excess_defer) 1084 value |= HALFDUP_EXCESSIVE_DEFER; 1085 1086 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1087 1088 value |= collision_window; 1089 1090 out_be32(hafdup_register, value); 1091 return 0; 1092} 1093 1094static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1095 u8 non_btb_ipg, 1096 u8 min_ifg, 1097 u8 btb_ipg, 1098 u32 __iomem *ipgifg_register) 1099{ 1100 u32 value = 0; 1101 1102 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1103 IPG part 2 */ 1104 if (non_btb_cs_ipg > non_btb_ipg) 1105 return -EINVAL; 1106 1107 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1108 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1109 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1110 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1111 return -EINVAL; 1112 1113 value |= 1114 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1115 IPGIFG_NBTB_CS_IPG_MASK); 1116 value |= 1117 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1118 IPGIFG_NBTB_IPG_MASK); 1119 value |= 1120 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1121 IPGIFG_MIN_IFG_MASK); 1122 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1123 1124 out_be32(ipgifg_register, value); 1125 return 0; 1126} 1127 1128int init_flow_control_params(u32 automatic_flow_control_mode, 1129 int rx_flow_control_enable, 1130 int tx_flow_control_enable, 1131 u16 pause_period, 1132 u16 extension_field, 1133 u32 __iomem *upsmr_register, 1134 u32 __iomem *uempr_register, 1135 u32 __iomem *maccfg1_register) 1136{ 1137 u32 value = 0; 1138 1139 /* Set UEMPR register */ 1140 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1141 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1142 out_be32(uempr_register, value); 1143 1144 /* Set UPSMR register */ 1145 setbits32(upsmr_register, automatic_flow_control_mode); 1146 1147 value = in_be32(maccfg1_register); 1148 if (rx_flow_control_enable) 1149 value |= MACCFG1_FLOW_RX; 1150 if (tx_flow_control_enable) 1151 value |= MACCFG1_FLOW_TX; 1152 out_be32(maccfg1_register, value); 1153 1154 return 0; 1155} 1156 1157static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1158 int auto_zero_hardware_statistics, 1159 u32 __iomem *upsmr_register, 1160 u16 __iomem *uescr_register) 1161{ 1162 u16 uescr_value = 0; 1163 1164 /* Enable hardware statistics gathering if requested */ 1165 if (enable_hardware_statistics) 1166 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1167 1168 /* Clear hardware statistics counters */ 1169 uescr_value = in_be16(uescr_register); 1170 uescr_value |= UESCR_CLRCNT; 1171 /* Automatically zero hardware statistics counters on read, 1172 if requested */ 1173 if (auto_zero_hardware_statistics) 1174 uescr_value |= UESCR_AUTOZ; 1175 out_be16(uescr_register, uescr_value); 1176 1177 return 0; 1178} 1179 1180static int init_firmware_statistics_gathering_mode(int 1181 enable_tx_firmware_statistics, 1182 int enable_rx_firmware_statistics, 1183 u32 __iomem *tx_rmon_base_ptr, 1184 u32 tx_firmware_statistics_structure_address, 1185 u32 __iomem *rx_rmon_base_ptr, 1186 u32 rx_firmware_statistics_structure_address, 1187 u16 __iomem *temoder_register, 1188 u32 __iomem *remoder_register) 1189{ 1190 /* Note: this function does not check if */ 1191 /* the parameters it receives are NULL */ 1192 1193 if (enable_tx_firmware_statistics) { 1194 out_be32(tx_rmon_base_ptr, 1195 tx_firmware_statistics_structure_address); 1196 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1197 } 1198 1199 if (enable_rx_firmware_statistics) { 1200 out_be32(rx_rmon_base_ptr, 1201 rx_firmware_statistics_structure_address); 1202 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1203 } 1204 1205 return 0; 1206} 1207 1208static int init_mac_station_addr_regs(u8 address_byte_0, 1209 u8 address_byte_1, 1210 u8 address_byte_2, 1211 u8 address_byte_3, 1212 u8 address_byte_4, 1213 u8 address_byte_5, 1214 u32 __iomem *macstnaddr1_register, 1215 u32 __iomem *macstnaddr2_register) 1216{ 1217 u32 value = 0; 1218 1219 /* Example: for a station address of 0x12345678ABCD, */ 1220 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1221 1222 /* MACSTNADDR1 Register: */ 1223 1224 /* 0 7 8 15 */ 1225 /* station address byte 5 station address byte 4 */ 1226 /* 16 23 24 31 */ 1227 /* station address byte 3 station address byte 2 */ 1228 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1229 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1230 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1231 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1232 1233 out_be32(macstnaddr1_register, value); 1234 1235 /* MACSTNADDR2 Register: */ 1236 1237 /* 0 7 8 15 */ 1238 /* station address byte 1 station address byte 0 */ 1239 /* 16 23 24 31 */ 1240 /* reserved reserved */ 1241 value = 0; 1242 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1243 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1244 1245 out_be32(macstnaddr2_register, value); 1246 1247 return 0; 1248} 1249 1250static int init_check_frame_length_mode(int length_check, 1251 u32 __iomem *maccfg2_register) 1252{ 1253 u32 value = 0; 1254 1255 value = in_be32(maccfg2_register); 1256 1257 if (length_check) 1258 value |= MACCFG2_LC; 1259 else 1260 value &= ~MACCFG2_LC; 1261 1262 out_be32(maccfg2_register, value); 1263 return 0; 1264} 1265 1266static int init_preamble_length(u8 preamble_length, 1267 u32 __iomem *maccfg2_register) 1268{ 1269 if ((preamble_length < 3) || (preamble_length > 7)) 1270 return -EINVAL; 1271 1272 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1273 preamble_length << MACCFG2_PREL_SHIFT); 1274 1275 return 0; 1276} 1277 1278static int init_rx_parameters(int reject_broadcast, 1279 int receive_short_frames, 1280 int promiscuous, u32 __iomem *upsmr_register) 1281{ 1282 u32 value = 0; 1283 1284 value = in_be32(upsmr_register); 1285 1286 if (reject_broadcast) 1287 value |= UCC_GETH_UPSMR_BRO; 1288 else 1289 value &= ~UCC_GETH_UPSMR_BRO; 1290 1291 if (receive_short_frames) 1292 value |= UCC_GETH_UPSMR_RSH; 1293 else 1294 value &= ~UCC_GETH_UPSMR_RSH; 1295 1296 if (promiscuous) 1297 value |= UCC_GETH_UPSMR_PRO; 1298 else 1299 value &= ~UCC_GETH_UPSMR_PRO; 1300 1301 out_be32(upsmr_register, value); 1302 1303 return 0; 1304} 1305 1306static int init_max_rx_buff_len(u16 max_rx_buf_len, 1307 u16 __iomem *mrblr_register) 1308{ 1309 /* max_rx_buf_len value must be a multiple of 128 */ 1310 if ((max_rx_buf_len == 0) || 1311 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1312 return -EINVAL; 1313 1314 out_be16(mrblr_register, max_rx_buf_len); 1315 return 0; 1316} 1317 1318static int init_min_frame_len(u16 min_frame_length, 1319 u16 __iomem *minflr_register, 1320 u16 __iomem *mrblr_register) 1321{ 1322 u16 mrblr_value = 0; 1323 1324 mrblr_value = in_be16(mrblr_register); 1325 if (min_frame_length >= (mrblr_value - 4)) 1326 return -EINVAL; 1327 1328 out_be16(minflr_register, min_frame_length); 1329 return 0; 1330} 1331 1332static int adjust_enet_interface(struct ucc_geth_private *ugeth) 1333{ 1334 struct ucc_geth_info *ug_info; 1335 struct ucc_geth __iomem *ug_regs; 1336 struct ucc_fast __iomem *uf_regs; 1337 int ret_val; 1338 u32 upsmr, maccfg2; 1339 u16 value; 1340 1341 ugeth_vdbg("%s: IN", __func__); 1342 1343 ug_info = ugeth->ug_info; 1344 ug_regs = ugeth->ug_regs; 1345 uf_regs = ugeth->uccf->uf_regs; 1346 1347 /* Set MACCFG2 */ 1348 maccfg2 = in_be32(&ug_regs->maccfg2); 1349 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1350 if ((ugeth->max_speed == SPEED_10) || 1351 (ugeth->max_speed == SPEED_100)) 1352 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1353 else if (ugeth->max_speed == SPEED_1000) 1354 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1355 maccfg2 |= ug_info->padAndCrc; 1356 out_be32(&ug_regs->maccfg2, maccfg2); 1357 1358 /* Set UPSMR */ 1359 upsmr = in_be32(&uf_regs->upsmr); 1360 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1361 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1362 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1363 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1367 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1368 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII) 1369 upsmr |= UCC_GETH_UPSMR_RPM; 1370 switch (ugeth->max_speed) { 1371 case SPEED_10: 1372 upsmr |= UCC_GETH_UPSMR_R10M; 1373 /* FALLTHROUGH */ 1374 case SPEED_100: 1375 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1376 upsmr |= UCC_GETH_UPSMR_RMM; 1377 } 1378 } 1379 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1380 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1381 upsmr |= UCC_GETH_UPSMR_TBIM; 1382 } 1383 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) 1384 upsmr |= UCC_GETH_UPSMR_SGMM; 1385 1386 out_be32(&uf_regs->upsmr, upsmr); 1387 1388 /* Disable autonegotiation in tbi mode, because by default it 1389 comes up in autonegotiation mode. */ 1390 /* Note that this depends on proper setting in utbipar register. */ 1391 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1392 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1393 struct ucc_geth_info *ug_info = ugeth->ug_info; 1394 struct phy_device *tbiphy; 1395 1396 if (!ug_info->tbi_node) 1397 ugeth_warn("TBI mode requires that the device " 1398 "tree specify a tbi-handle\n"); 1399 1400 tbiphy = of_phy_find_device(ug_info->tbi_node); 1401 if (!tbiphy) 1402 ugeth_warn("Could not get TBI device\n"); 1403 1404 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1405 value &= ~0x1000; /* Turn off autonegotiation */ 1406 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1407 } 1408 1409 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); 1410 1411 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); 1412 if (ret_val != 0) { 1413 if (netif_msg_probe(ugeth)) 1414 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.", 1415 __func__); 1416 return ret_val; 1417 } 1418 1419 return 0; 1420} 1421 1422static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1423{ 1424 struct ucc_fast_private *uccf; 1425 u32 cecr_subblock; 1426 u32 temp; 1427 int i = 10; 1428 1429 uccf = ugeth->uccf; 1430 1431 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1432 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1433 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1434 1435 /* Issue host command */ 1436 cecr_subblock = 1437 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1438 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1439 QE_CR_PROTOCOL_ETHERNET, 0); 1440 1441 /* Wait for command to complete */ 1442 do { 1443 msleep(10); 1444 temp = in_be32(uccf->p_ucce); 1445 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1446 1447 uccf->stopped_tx = 1; 1448 1449 return 0; 1450} 1451 1452static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1453{ 1454 struct ucc_fast_private *uccf; 1455 u32 cecr_subblock; 1456 u8 temp; 1457 int i = 10; 1458 1459 uccf = ugeth->uccf; 1460 1461 /* Clear acknowledge bit */ 1462 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1463 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1464 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1465 1466 /* Keep issuing command and checking acknowledge bit until 1467 it is asserted, according to spec */ 1468 do { 1469 /* Issue host command */ 1470 cecr_subblock = 1471 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1472 ucc_num); 1473 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1474 QE_CR_PROTOCOL_ETHERNET, 0); 1475 msleep(10); 1476 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1477 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1478 1479 uccf->stopped_rx = 1; 1480 1481 return 0; 1482} 1483 1484static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1485{ 1486 struct ucc_fast_private *uccf; 1487 u32 cecr_subblock; 1488 1489 uccf = ugeth->uccf; 1490 1491 cecr_subblock = 1492 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1493 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1494 uccf->stopped_tx = 0; 1495 1496 return 0; 1497} 1498 1499static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1500{ 1501 struct ucc_fast_private *uccf; 1502 u32 cecr_subblock; 1503 1504 uccf = ugeth->uccf; 1505 1506 cecr_subblock = 1507 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1508 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1509 0); 1510 uccf->stopped_rx = 0; 1511 1512 return 0; 1513} 1514 1515static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1516{ 1517 struct ucc_fast_private *uccf; 1518 int enabled_tx, enabled_rx; 1519 1520 uccf = ugeth->uccf; 1521 1522 /* check if the UCC number is in range. */ 1523 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1524 if (netif_msg_probe(ugeth)) 1525 ugeth_err("%s: ucc_num out of range.", __func__); 1526 return -EINVAL; 1527 } 1528 1529 enabled_tx = uccf->enabled_tx; 1530 enabled_rx = uccf->enabled_rx; 1531 1532 /* Get Tx and Rx going again, in case this channel was actively 1533 disabled. */ 1534 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1535 ugeth_restart_tx(ugeth); 1536 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1537 ugeth_restart_rx(ugeth); 1538 1539 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1540 1541 return 0; 1542 1543} 1544 1545static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1546{ 1547 struct ucc_fast_private *uccf; 1548 1549 uccf = ugeth->uccf; 1550 1551 /* check if the UCC number is in range. */ 1552 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1553 if (netif_msg_probe(ugeth)) 1554 ugeth_err("%s: ucc_num out of range.", __func__); 1555 return -EINVAL; 1556 } 1557 1558 /* Stop any transmissions */ 1559 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1560 ugeth_graceful_stop_tx(ugeth); 1561 1562 /* Stop any receptions */ 1563 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1564 ugeth_graceful_stop_rx(ugeth); 1565 1566 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1567 1568 return 0; 1569} 1570 1571static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1572{ 1573 /* Prevent any further xmits, plus detach the device. */ 1574 netif_device_detach(ugeth->ndev); 1575 1576 /* Wait for any current xmits to finish. */ 1577 netif_tx_disable(ugeth->ndev); 1578 1579 /* Disable the interrupt to avoid NAPI rescheduling. */ 1580 disable_irq(ugeth->ug_info->uf_info.irq); 1581 1582 /* Stop NAPI, and possibly wait for its completion. */ 1583 napi_disable(&ugeth->napi); 1584} 1585 1586static void ugeth_activate(struct ucc_geth_private *ugeth) 1587{ 1588 napi_enable(&ugeth->napi); 1589 enable_irq(ugeth->ug_info->uf_info.irq); 1590 netif_device_attach(ugeth->ndev); 1591} 1592 1593/* Called every time the controller might need to be made 1594 * aware of new link state. The PHY code conveys this 1595 * information through variables in the ugeth structure, and this 1596 * function converts those variables into the appropriate 1597 * register values, and can bring down the device if needed. 1598 */ 1599 1600static void adjust_link(struct net_device *dev) 1601{ 1602 struct ucc_geth_private *ugeth = netdev_priv(dev); 1603 struct ucc_geth __iomem *ug_regs; 1604 struct ucc_fast __iomem *uf_regs; 1605 struct phy_device *phydev = ugeth->phydev; 1606 int new_state = 0; 1607 1608 ug_regs = ugeth->ug_regs; 1609 uf_regs = ugeth->uccf->uf_regs; 1610 1611 if (phydev->link) { 1612 u32 tempval = in_be32(&ug_regs->maccfg2); 1613 u32 upsmr = in_be32(&uf_regs->upsmr); 1614 /* Now we make sure that we can be in full duplex mode. 1615 * If not, we operate in half-duplex mode. */ 1616 if (phydev->duplex != ugeth->oldduplex) { 1617 new_state = 1; 1618 if (!(phydev->duplex)) 1619 tempval &= ~(MACCFG2_FDX); 1620 else 1621 tempval |= MACCFG2_FDX; 1622 ugeth->oldduplex = phydev->duplex; 1623 } 1624 1625 if (phydev->speed != ugeth->oldspeed) { 1626 new_state = 1; 1627 switch (phydev->speed) { 1628 case SPEED_1000: 1629 tempval = ((tempval & 1630 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1631 MACCFG2_INTERFACE_MODE_BYTE); 1632 break; 1633 case SPEED_100: 1634 case SPEED_10: 1635 tempval = ((tempval & 1636 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1637 MACCFG2_INTERFACE_MODE_NIBBLE); 1638 /* if reduced mode, re-set UPSMR.R10M */ 1639 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1640 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1641 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1642 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1643 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1644 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1645 if (phydev->speed == SPEED_10) 1646 upsmr |= UCC_GETH_UPSMR_R10M; 1647 else 1648 upsmr &= ~UCC_GETH_UPSMR_R10M; 1649 } 1650 break; 1651 default: 1652 if (netif_msg_link(ugeth)) 1653 ugeth_warn( 1654 "%s: Ack! Speed (%d) is not 10/100/1000!", 1655 dev->name, phydev->speed); 1656 break; 1657 } 1658 ugeth->oldspeed = phydev->speed; 1659 } 1660 1661 if (!ugeth->oldlink) { 1662 new_state = 1; 1663 ugeth->oldlink = 1; 1664 } 1665 1666 if (new_state) { 1667 /* 1668 * To change the MAC configuration we need to disable 1669 * the controller. To do so, we have to either grab 1670 * ugeth->lock, which is a bad idea since 'graceful 1671 * stop' commands might take quite a while, or we can 1672 * quiesce driver's activity. 1673 */ 1674 ugeth_quiesce(ugeth); 1675 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1676 1677 out_be32(&ug_regs->maccfg2, tempval); 1678 out_be32(&uf_regs->upsmr, upsmr); 1679 1680 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1681 ugeth_activate(ugeth); 1682 } 1683 } else if (ugeth->oldlink) { 1684 new_state = 1; 1685 ugeth->oldlink = 0; 1686 ugeth->oldspeed = 0; 1687 ugeth->oldduplex = -1; 1688 } 1689 1690 if (new_state && netif_msg_link(ugeth)) 1691 phy_print_status(phydev); 1692} 1693 1694/* Initialize TBI PHY interface for communicating with the 1695 * SERDES lynx PHY on the chip. We communicate with this PHY 1696 * through the MDIO bus on each controller, treating it as a 1697 * "normal" PHY at the address found in the UTBIPA register. We assume 1698 * that the UTBIPA register is valid. Either the MDIO bus code will set 1699 * it to a value that doesn't conflict with other PHYs on the bus, or the 1700 * value doesn't matter, as there are no other PHYs on the bus. 1701 */ 1702static void uec_configure_serdes(struct net_device *dev) 1703{ 1704 struct ucc_geth_private *ugeth = netdev_priv(dev); 1705 struct ucc_geth_info *ug_info = ugeth->ug_info; 1706 struct phy_device *tbiphy; 1707 1708 if (!ug_info->tbi_node) { 1709 dev_warn(&dev->dev, "SGMII mode requires that the device " 1710 "tree specify a tbi-handle\n"); 1711 return; 1712 } 1713 1714 tbiphy = of_phy_find_device(ug_info->tbi_node); 1715 if (!tbiphy) { 1716 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1717 return; 1718 } 1719 1720 /* 1721 * If the link is already up, we must already be ok, and don't need to 1722 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1723 * everything for us? Resetting it takes the link down and requires 1724 * several seconds for it to come back. 1725 */ 1726 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) 1727 return; 1728 1729 /* Single clk mode, mii mode off(for serdes communication) */ 1730 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1731 1732 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1733 1734 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1735} 1736 1737/* Configure the PHY for dev. 1738 * returns 0 if success. -1 if failure 1739 */ 1740static int init_phy(struct net_device *dev) 1741{ 1742 struct ucc_geth_private *priv = netdev_priv(dev); 1743 struct ucc_geth_info *ug_info = priv->ug_info; 1744 struct phy_device *phydev; 1745 1746 priv->oldlink = 0; 1747 priv->oldspeed = 0; 1748 priv->oldduplex = -1; 1749 1750 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0, 1751 priv->phy_interface); 1752 if (!phydev) 1753 phydev = of_phy_connect_fixed_link(dev, &adjust_link, 1754 priv->phy_interface); 1755 if (!phydev) { 1756 dev_err(&dev->dev, "Could not attach to PHY\n"); 1757 return -ENODEV; 1758 } 1759 1760 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) 1761 uec_configure_serdes(dev); 1762 1763 phydev->supported &= (ADVERTISED_10baseT_Half | 1764 ADVERTISED_10baseT_Full | 1765 ADVERTISED_100baseT_Half | 1766 ADVERTISED_100baseT_Full); 1767 1768 if (priv->max_speed == SPEED_1000) 1769 phydev->supported |= ADVERTISED_1000baseT_Full; 1770 1771 phydev->advertising = phydev->supported; 1772 1773 priv->phydev = phydev; 1774 1775 return 0; 1776} 1777 1778static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1779{ 1780#ifdef DEBUG 1781 ucc_fast_dump_regs(ugeth->uccf); 1782 dump_regs(ugeth); 1783 dump_bds(ugeth); 1784#endif 1785} 1786 1787static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1788 ugeth, 1789 enum enet_addr_type 1790 enet_addr_type) 1791{ 1792 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1793 struct ucc_fast_private *uccf; 1794 enum comm_dir comm_dir; 1795 struct list_head *p_lh; 1796 u16 i, num; 1797 u32 __iomem *addr_h; 1798 u32 __iomem *addr_l; 1799 u8 *p_counter; 1800 1801 uccf = ugeth->uccf; 1802 1803 p_82xx_addr_filt = 1804 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1805 ugeth->p_rx_glbl_pram->addressfiltering; 1806 1807 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1808 addr_h = &(p_82xx_addr_filt->gaddr_h); 1809 addr_l = &(p_82xx_addr_filt->gaddr_l); 1810 p_lh = &ugeth->group_hash_q; 1811 p_counter = &(ugeth->numGroupAddrInHash); 1812 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1813 addr_h = &(p_82xx_addr_filt->iaddr_h); 1814 addr_l = &(p_82xx_addr_filt->iaddr_l); 1815 p_lh = &ugeth->ind_hash_q; 1816 p_counter = &(ugeth->numIndAddrInHash); 1817 } else 1818 return -EINVAL; 1819 1820 comm_dir = 0; 1821 if (uccf->enabled_tx) 1822 comm_dir |= COMM_DIR_TX; 1823 if (uccf->enabled_rx) 1824 comm_dir |= COMM_DIR_RX; 1825 if (comm_dir) 1826 ugeth_disable(ugeth, comm_dir); 1827 1828 /* Clear the hash table. */ 1829 out_be32(addr_h, 0x00000000); 1830 out_be32(addr_l, 0x00000000); 1831 1832 if (!p_lh) 1833 return 0; 1834 1835 num = *p_counter; 1836 1837 /* Delete all remaining CQ elements */ 1838 for (i = 0; i < num; i++) 1839 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1840 1841 *p_counter = 0; 1842 1843 if (comm_dir) 1844 ugeth_enable(ugeth, comm_dir); 1845 1846 return 0; 1847} 1848 1849static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1850 u8 paddr_num) 1851{ 1852 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1853 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1854} 1855 1856static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1857{ 1858 u16 i, j; 1859 u8 __iomem *bd; 1860 1861 if (!ugeth) 1862 return; 1863 1864 if (ugeth->uccf) { 1865 ucc_fast_free(ugeth->uccf); 1866 ugeth->uccf = NULL; 1867 } 1868 1869 if (ugeth->p_thread_data_tx) { 1870 qe_muram_free(ugeth->thread_dat_tx_offset); 1871 ugeth->p_thread_data_tx = NULL; 1872 } 1873 if (ugeth->p_thread_data_rx) { 1874 qe_muram_free(ugeth->thread_dat_rx_offset); 1875 ugeth->p_thread_data_rx = NULL; 1876 } 1877 if (ugeth->p_exf_glbl_param) { 1878 qe_muram_free(ugeth->exf_glbl_param_offset); 1879 ugeth->p_exf_glbl_param = NULL; 1880 } 1881 if (ugeth->p_rx_glbl_pram) { 1882 qe_muram_free(ugeth->rx_glbl_pram_offset); 1883 ugeth->p_rx_glbl_pram = NULL; 1884 } 1885 if (ugeth->p_tx_glbl_pram) { 1886 qe_muram_free(ugeth->tx_glbl_pram_offset); 1887 ugeth->p_tx_glbl_pram = NULL; 1888 } 1889 if (ugeth->p_send_q_mem_reg) { 1890 qe_muram_free(ugeth->send_q_mem_reg_offset); 1891 ugeth->p_send_q_mem_reg = NULL; 1892 } 1893 if (ugeth->p_scheduler) { 1894 qe_muram_free(ugeth->scheduler_offset); 1895 ugeth->p_scheduler = NULL; 1896 } 1897 if (ugeth->p_tx_fw_statistics_pram) { 1898 qe_muram_free(ugeth->tx_fw_statistics_pram_offset); 1899 ugeth->p_tx_fw_statistics_pram = NULL; 1900 } 1901 if (ugeth->p_rx_fw_statistics_pram) { 1902 qe_muram_free(ugeth->rx_fw_statistics_pram_offset); 1903 ugeth->p_rx_fw_statistics_pram = NULL; 1904 } 1905 if (ugeth->p_rx_irq_coalescing_tbl) { 1906 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); 1907 ugeth->p_rx_irq_coalescing_tbl = NULL; 1908 } 1909 if (ugeth->p_rx_bd_qs_tbl) { 1910 qe_muram_free(ugeth->rx_bd_qs_tbl_offset); 1911 ugeth->p_rx_bd_qs_tbl = NULL; 1912 } 1913 if (ugeth->p_init_enet_param_shadow) { 1914 return_init_enet_entries(ugeth, 1915 &(ugeth->p_init_enet_param_shadow-> 1916 rxthread[0]), 1917 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1918 ugeth->ug_info->riscRx, 1); 1919 return_init_enet_entries(ugeth, 1920 &(ugeth->p_init_enet_param_shadow-> 1921 txthread[0]), 1922 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1923 ugeth->ug_info->riscTx, 0); 1924 kfree(ugeth->p_init_enet_param_shadow); 1925 ugeth->p_init_enet_param_shadow = NULL; 1926 } 1927 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 1928 bd = ugeth->p_tx_bd_ring[i]; 1929 if (!bd) 1930 continue; 1931 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1932 if (ugeth->tx_skbuff[i][j]) { 1933 dma_unmap_single(ugeth->dev, 1934 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1935 (in_be32((u32 __iomem *)bd) & 1936 BD_LENGTH_MASK), 1937 DMA_TO_DEVICE); 1938 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1939 ugeth->tx_skbuff[i][j] = NULL; 1940 } 1941 } 1942 1943 kfree(ugeth->tx_skbuff[i]); 1944 1945 if (ugeth->p_tx_bd_ring[i]) { 1946 if (ugeth->ug_info->uf_info.bd_mem_part == 1947 MEM_PART_SYSTEM) 1948 kfree((void *)ugeth->tx_bd_ring_offset[i]); 1949 else if (ugeth->ug_info->uf_info.bd_mem_part == 1950 MEM_PART_MURAM) 1951 qe_muram_free(ugeth->tx_bd_ring_offset[i]); 1952 ugeth->p_tx_bd_ring[i] = NULL; 1953 } 1954 } 1955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 1956 if (ugeth->p_rx_bd_ring[i]) { 1957 /* Return existing data buffers in ring */ 1958 bd = ugeth->p_rx_bd_ring[i]; 1959 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1960 if (ugeth->rx_skbuff[i][j]) { 1961 dma_unmap_single(ugeth->dev, 1962 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1963 ugeth->ug_info-> 1964 uf_info.max_rx_buf_length + 1965 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1966 DMA_FROM_DEVICE); 1967 dev_kfree_skb_any( 1968 ugeth->rx_skbuff[i][j]); 1969 ugeth->rx_skbuff[i][j] = NULL; 1970 } 1971 bd += sizeof(struct qe_bd); 1972 } 1973 1974 kfree(ugeth->rx_skbuff[i]); 1975 1976 if (ugeth->ug_info->uf_info.bd_mem_part == 1977 MEM_PART_SYSTEM) 1978 kfree((void *)ugeth->rx_bd_ring_offset[i]); 1979 else if (ugeth->ug_info->uf_info.bd_mem_part == 1980 MEM_PART_MURAM) 1981 qe_muram_free(ugeth->rx_bd_ring_offset[i]); 1982 ugeth->p_rx_bd_ring[i] = NULL; 1983 } 1984 } 1985 while (!list_empty(&ugeth->group_hash_q)) 1986 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1987 (dequeue(&ugeth->group_hash_q))); 1988 while (!list_empty(&ugeth->ind_hash_q)) 1989 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1990 (dequeue(&ugeth->ind_hash_q))); 1991 if (ugeth->ug_regs) { 1992 iounmap(ugeth->ug_regs); 1993 ugeth->ug_regs = NULL; 1994 } 1995 1996 skb_queue_purge(&ugeth->rx_recycle); 1997} 1998 1999static void ucc_geth_set_multi(struct net_device *dev) 2000{ 2001 struct ucc_geth_private *ugeth; 2002 struct netdev_hw_addr *ha; 2003 struct ucc_fast __iomem *uf_regs; 2004 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2005 2006 ugeth = netdev_priv(dev); 2007 2008 uf_regs = ugeth->uccf->uf_regs; 2009 2010 if (dev->flags & IFF_PROMISC) { 2011 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2012 } else { 2013 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2014 2015 p_82xx_addr_filt = 2016 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2017 p_rx_glbl_pram->addressfiltering; 2018 2019 if (dev->flags & IFF_ALLMULTI) { 2020 /* Catch all multicast addresses, so set the 2021 * filter to all 1's. 2022 */ 2023 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 2024 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 2025 } else { 2026 /* Clear filter and add the addresses in the list. 2027 */ 2028 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 2029 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 2030 2031 netdev_for_each_mc_addr(ha, dev) { 2032 /* Only support group multicast for now. 2033 */ 2034 if (!(ha->addr[0] & 1)) 2035 continue; 2036 2037 /* Ask CPM to run CRC and set bit in 2038 * filter mask. 2039 */ 2040 hw_add_addr_in_hash(ugeth, ha->addr); 2041 } 2042 } 2043 } 2044} 2045 2046static void ucc_geth_stop(struct ucc_geth_private *ugeth) 2047{ 2048 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 2049 struct phy_device *phydev = ugeth->phydev; 2050 2051 ugeth_vdbg("%s: IN", __func__); 2052 2053 /* 2054 * Tell the kernel the link is down. 2055 * Must be done before disabling the controller 2056 * or deadlock may happen. 2057 */ 2058 phy_stop(phydev); 2059 2060 /* Disable the controller */ 2061 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 2062 2063 /* Mask all interrupts */ 2064 out_be32(ugeth->uccf->p_uccm, 0x00000000); 2065 2066 /* Clear all interrupts */ 2067 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2068 2069 /* Disable Rx and Tx */ 2070 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2071 2072 ucc_geth_memclean(ugeth); 2073} 2074 2075static int ucc_struct_init(struct ucc_geth_private *ugeth) 2076{ 2077 struct ucc_geth_info *ug_info; 2078 struct ucc_fast_info *uf_info; 2079 int i; 2080 2081 ug_info = ugeth->ug_info; 2082 uf_info = &ug_info->uf_info; 2083 2084 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || 2085 (uf_info->bd_mem_part == MEM_PART_MURAM))) { 2086 if (netif_msg_probe(ugeth)) 2087 ugeth_err("%s: Bad memory partition value.", 2088 __func__); 2089 return -EINVAL; 2090 } 2091 2092 /* Rx BD lengths */ 2093 for (i = 0; i < ug_info->numQueuesRx; i++) { 2094 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 2095 (ug_info->bdRingLenRx[i] % 2096 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 2097 if (netif_msg_probe(ugeth)) 2098 ugeth_err 2099 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.", 2100 __func__); 2101 return -EINVAL; 2102 } 2103 } 2104 2105 /* Tx BD lengths */ 2106 for (i = 0; i < ug_info->numQueuesTx; i++) { 2107 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 2108 if (netif_msg_probe(ugeth)) 2109 ugeth_err 2110 ("%s: Tx BD ring length must be no smaller than 2.", 2111 __func__); 2112 return -EINVAL; 2113 } 2114 } 2115 2116 /* mrblr */ 2117 if ((uf_info->max_rx_buf_length == 0) || 2118 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 2119 if (netif_msg_probe(ugeth)) 2120 ugeth_err 2121 ("%s: max_rx_buf_length must be non-zero multiple of 128.", 2122 __func__); 2123 return -EINVAL; 2124 } 2125 2126 /* num Tx queues */ 2127 if (ug_info->numQueuesTx > NUM_TX_QUEUES) { 2128 if (netif_msg_probe(ugeth)) 2129 ugeth_err("%s: number of tx queues too large.", __func__); 2130 return -EINVAL; 2131 } 2132 2133 /* num Rx queues */ 2134 if (ug_info->numQueuesRx > NUM_RX_QUEUES) { 2135 if (netif_msg_probe(ugeth)) 2136 ugeth_err("%s: number of rx queues too large.", __func__); 2137 return -EINVAL; 2138 } 2139 2140 /* l2qt */ 2141 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 2142 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { 2143 if (netif_msg_probe(ugeth)) 2144 ugeth_err 2145 ("%s: VLAN priority table entry must not be" 2146 " larger than number of Rx queues.", 2147 __func__); 2148 return -EINVAL; 2149 } 2150 } 2151 2152 /* l3qt */ 2153 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 2154 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { 2155 if (netif_msg_probe(ugeth)) 2156 ugeth_err 2157 ("%s: IP priority table entry must not be" 2158 " larger than number of Rx queues.", 2159 __func__); 2160 return -EINVAL; 2161 } 2162 } 2163 2164 if (ug_info->cam && !ug_info->ecamptr) { 2165 if (netif_msg_probe(ugeth)) 2166 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.", 2167 __func__); 2168 return -EINVAL; 2169 } 2170 2171 if ((ug_info->numStationAddresses != 2172 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2173 ug_info->rxExtendedFiltering) { 2174 if (netif_msg_probe(ugeth)) 2175 ugeth_err("%s: Number of station addresses greater than 1 " 2176 "not allowed in extended parsing mode.", 2177 __func__); 2178 return -EINVAL; 2179 } 2180 2181 /* Generate uccm_mask for receive */ 2182 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2183 for (i = 0; i < ug_info->numQueuesRx; i++) 2184 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2185 2186 for (i = 0; i < ug_info->numQueuesTx; i++) 2187 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2188 /* Initialize the general fast UCC block. */ 2189 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2190 if (netif_msg_probe(ugeth)) 2191 ugeth_err("%s: Failed to init uccf.", __func__); 2192 return -ENOMEM; 2193 } 2194 2195 /* read the number of risc engines, update the riscTx and riscRx 2196 * if there are 4 riscs in QE 2197 */ 2198 if (qe_get_num_of_risc() == 4) { 2199 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2200 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2201 } 2202 2203 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2204 if (!ugeth->ug_regs) { 2205 if (netif_msg_probe(ugeth)) 2206 ugeth_err("%s: Failed to ioremap regs.", __func__); 2207 return -ENOMEM; 2208 } 2209 2210 skb_queue_head_init(&ugeth->rx_recycle); 2211 2212 return 0; 2213} 2214 2215static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2216{ 2217 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2218 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2219 struct ucc_fast_private *uccf; 2220 struct ucc_geth_info *ug_info; 2221 struct ucc_fast_info *uf_info; 2222 struct ucc_fast __iomem *uf_regs; 2223 struct ucc_geth __iomem *ug_regs; 2224 int ret_val = -EINVAL; 2225 u32 remoder = UCC_GETH_REMODER_INIT; 2226 u32 init_enet_pram_offset, cecr_subblock, command; 2227 u32 ifstat, i, j, size, l2qt, l3qt, length; 2228 u16 temoder = UCC_GETH_TEMODER_INIT; 2229 u16 test; 2230 u8 function_code = 0; 2231 u8 __iomem *bd; 2232 u8 __iomem *endOfRing; 2233 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2234 2235 ugeth_vdbg("%s: IN", __func__); 2236 uccf = ugeth->uccf; 2237 ug_info = ugeth->ug_info; 2238 uf_info = &ug_info->uf_info; 2239 uf_regs = uccf->uf_regs; 2240 ug_regs = ugeth->ug_regs; 2241 2242 switch (ug_info->numThreadsRx) { 2243 case UCC_GETH_NUM_OF_THREADS_1: 2244 numThreadsRxNumerical = 1; 2245 break; 2246 case UCC_GETH_NUM_OF_THREADS_2: 2247 numThreadsRxNumerical = 2; 2248 break; 2249 case UCC_GETH_NUM_OF_THREADS_4: 2250 numThreadsRxNumerical = 4; 2251 break; 2252 case UCC_GETH_NUM_OF_THREADS_6: 2253 numThreadsRxNumerical = 6; 2254 break; 2255 case UCC_GETH_NUM_OF_THREADS_8: 2256 numThreadsRxNumerical = 8; 2257 break; 2258 default: 2259 if (netif_msg_ifup(ugeth)) 2260 ugeth_err("%s: Bad number of Rx threads value.", 2261 __func__); 2262 return -EINVAL; 2263 break; 2264 } 2265 2266 switch (ug_info->numThreadsTx) { 2267 case UCC_GETH_NUM_OF_THREADS_1: 2268 numThreadsTxNumerical = 1; 2269 break; 2270 case UCC_GETH_NUM_OF_THREADS_2: 2271 numThreadsTxNumerical = 2; 2272 break; 2273 case UCC_GETH_NUM_OF_THREADS_4: 2274 numThreadsTxNumerical = 4; 2275 break; 2276 case UCC_GETH_NUM_OF_THREADS_6: 2277 numThreadsTxNumerical = 6; 2278 break; 2279 case UCC_GETH_NUM_OF_THREADS_8: 2280 numThreadsTxNumerical = 8; 2281 break; 2282 default: 2283 if (netif_msg_ifup(ugeth)) 2284 ugeth_err("%s: Bad number of Tx threads value.", 2285 __func__); 2286 return -EINVAL; 2287 break; 2288 } 2289 2290 /* Calculate rx_extended_features */ 2291 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2292 ug_info->ipAddressAlignment || 2293 (ug_info->numStationAddresses != 2294 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2295 2296 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2297 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2298 (ug_info->vlanOperationNonTagged != 2299 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2300 2301 init_default_reg_vals(&uf_regs->upsmr, 2302 &ug_regs->maccfg1, &ug_regs->maccfg2); 2303 2304 /* Set UPSMR */ 2305 /* For more details see the hardware spec. */ 2306 init_rx_parameters(ug_info->bro, 2307 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2308 2309 /* We're going to ignore other registers for now, */ 2310 /* except as needed to get up and running */ 2311 2312 /* Set MACCFG1 */ 2313 /* For more details see the hardware spec. */ 2314 init_flow_control_params(ug_info->aufc, 2315 ug_info->receiveFlowControl, 2316 ug_info->transmitFlowControl, 2317 ug_info->pausePeriod, 2318 ug_info->extensionField, 2319 &uf_regs->upsmr, 2320 &ug_regs->uempr, &ug_regs->maccfg1); 2321 2322 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2323 2324 /* Set IPGIFG */ 2325 /* For more details see the hardware spec. */ 2326 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2327 ug_info->nonBackToBackIfgPart2, 2328 ug_info-> 2329 miminumInterFrameGapEnforcement, 2330 ug_info->backToBackInterFrameGap, 2331 &ug_regs->ipgifg); 2332 if (ret_val != 0) { 2333 if (netif_msg_ifup(ugeth)) 2334 ugeth_err("%s: IPGIFG initialization parameter too large.", 2335 __func__); 2336 return ret_val; 2337 } 2338 2339 /* Set HAFDUP */ 2340 /* For more details see the hardware spec. */ 2341 ret_val = init_half_duplex_params(ug_info->altBeb, 2342 ug_info->backPressureNoBackoff, 2343 ug_info->noBackoff, 2344 ug_info->excessDefer, 2345 ug_info->altBebTruncation, 2346 ug_info->maxRetransmission, 2347 ug_info->collisionWindow, 2348 &ug_regs->hafdup); 2349 if (ret_val != 0) { 2350 if (netif_msg_ifup(ugeth)) 2351 ugeth_err("%s: Half Duplex initialization parameter too large.", 2352 __func__); 2353 return ret_val; 2354 } 2355 2356 /* Set IFSTAT */ 2357 /* For more details see the hardware spec. */ 2358 /* Read only - resets upon read */ 2359 ifstat = in_be32(&ug_regs->ifstat); 2360 2361 /* Clear UEMPR */ 2362 /* For more details see the hardware spec. */ 2363 out_be32(&ug_regs->uempr, 0); 2364 2365 /* Set UESCR */ 2366 /* For more details see the hardware spec. */ 2367 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2368 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2369 0, &uf_regs->upsmr, &ug_regs->uescr); 2370 2371 /* Allocate Tx bds */ 2372 for (j = 0; j < ug_info->numQueuesTx; j++) { 2373 /* Allocate in multiple of 2374 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, 2375 according to spec */ 2376 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) 2377 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2378 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2379 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % 2380 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2381 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2382 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2383 u32 align = 4; 2384 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) 2385 align = UCC_GETH_TX_BD_RING_ALIGNMENT; 2386 ugeth->tx_bd_ring_offset[j] = 2387 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2388 2389 if (ugeth->tx_bd_ring_offset[j] != 0) 2390 ugeth->p_tx_bd_ring[j] = 2391 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] + 2392 align) & ~(align - 1)); 2393 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2394 ugeth->tx_bd_ring_offset[j] = 2395 qe_muram_alloc(length, 2396 UCC_GETH_TX_BD_RING_ALIGNMENT); 2397 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j])) 2398 ugeth->p_tx_bd_ring[j] = 2399 (u8 __iomem *) qe_muram_addr(ugeth-> 2400 tx_bd_ring_offset[j]); 2401 } 2402 if (!ugeth->p_tx_bd_ring[j]) { 2403 if (netif_msg_ifup(ugeth)) 2404 ugeth_err 2405 ("%s: Can not allocate memory for Tx bd rings.", 2406 __func__); 2407 return -ENOMEM; 2408 } 2409 /* Zero unused end of bd ring, according to spec */ 2410 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] + 2411 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0, 2412 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); 2413 } 2414 2415 /* Allocate Rx bds */ 2416 for (j = 0; j < ug_info->numQueuesRx; j++) { 2417 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2418 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2419 u32 align = 4; 2420 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) 2421 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2422 ugeth->rx_bd_ring_offset[j] = 2423 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2424 if (ugeth->rx_bd_ring_offset[j] != 0) 2425 ugeth->p_rx_bd_ring[j] = 2426 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] + 2427 align) & ~(align - 1)); 2428 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2429 ugeth->rx_bd_ring_offset[j] = 2430 qe_muram_alloc(length, 2431 UCC_GETH_RX_BD_RING_ALIGNMENT); 2432 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j])) 2433 ugeth->p_rx_bd_ring[j] = 2434 (u8 __iomem *) qe_muram_addr(ugeth-> 2435 rx_bd_ring_offset[j]); 2436 } 2437 if (!ugeth->p_rx_bd_ring[j]) { 2438 if (netif_msg_ifup(ugeth)) 2439 ugeth_err 2440 ("%s: Can not allocate memory for Rx bd rings.", 2441 __func__); 2442 return -ENOMEM; 2443 } 2444 } 2445 2446 /* Init Tx bds */ 2447 for (j = 0; j < ug_info->numQueuesTx; j++) { 2448 /* Setup the skbuff rings */ 2449 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) * 2450 ugeth->ug_info->bdRingLenTx[j], 2451 GFP_KERNEL); 2452 2453 if (ugeth->tx_skbuff[j] == NULL) { 2454 if (netif_msg_ifup(ugeth)) 2455 ugeth_err("%s: Could not allocate tx_skbuff", 2456 __func__); 2457 return -ENOMEM; 2458 } 2459 2460 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) 2461 ugeth->tx_skbuff[j][i] = NULL; 2462 2463 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2464 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2465 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2466 /* clear bd buffer */ 2467 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2468 /* set bd status and length */ 2469 out_be32((u32 __iomem *)bd, 0); 2470 bd += sizeof(struct qe_bd); 2471 } 2472 bd -= sizeof(struct qe_bd); 2473 /* set bd status and length */ 2474 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2475 } 2476 2477 /* Init Rx bds */ 2478 for (j = 0; j < ug_info->numQueuesRx; j++) { 2479 /* Setup the skbuff rings */ 2480 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) * 2481 ugeth->ug_info->bdRingLenRx[j], 2482 GFP_KERNEL); 2483 2484 if (ugeth->rx_skbuff[j] == NULL) { 2485 if (netif_msg_ifup(ugeth)) 2486 ugeth_err("%s: Could not allocate rx_skbuff", 2487 __func__); 2488 return -ENOMEM; 2489 } 2490 2491 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) 2492 ugeth->rx_skbuff[j][i] = NULL; 2493 2494 ugeth->skb_currx[j] = 0; 2495 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2496 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2497 /* set bd status and length */ 2498 out_be32((u32 __iomem *)bd, R_I); 2499 /* clear bd buffer */ 2500 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2501 bd += sizeof(struct qe_bd); 2502 } 2503 bd -= sizeof(struct qe_bd); 2504 /* set bd status and length */ 2505 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2506 } 2507 2508 /* 2509 * Global PRAM 2510 */ 2511 /* Tx global PRAM */ 2512 /* Allocate global tx parameter RAM page */ 2513 ugeth->tx_glbl_pram_offset = 2514 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2515 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2516 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) { 2517 if (netif_msg_ifup(ugeth)) 2518 ugeth_err 2519 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.", 2520 __func__); 2521 return -ENOMEM; 2522 } 2523 ugeth->p_tx_glbl_pram = 2524 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth-> 2525 tx_glbl_pram_offset); 2526 /* Zero out p_tx_glbl_pram */ 2527 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); 2528 2529 /* Fill global PRAM */ 2530 2531 /* TQPTR */ 2532 /* Size varies with number of Tx threads */ 2533 ugeth->thread_dat_tx_offset = 2534 qe_muram_alloc(numThreadsTxNumerical * 2535 sizeof(struct ucc_geth_thread_data_tx) + 2536 32 * (numThreadsTxNumerical == 1), 2537 UCC_GETH_THREAD_DATA_ALIGNMENT); 2538 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2539 if (netif_msg_ifup(ugeth)) 2540 ugeth_err 2541 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.", 2542 __func__); 2543 return -ENOMEM; 2544 } 2545 2546 ugeth->p_thread_data_tx = 2547 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2548 thread_dat_tx_offset); 2549 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2550 2551 /* vtagtable */ 2552 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2553 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2554 ug_info->vtagtable[i]); 2555 2556 /* iphoffset */ 2557 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2558 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2559 ug_info->iphoffset[i]); 2560 2561 /* SQPTR */ 2562 /* Size varies with number of Tx queues */ 2563 ugeth->send_q_mem_reg_offset = 2564 qe_muram_alloc(ug_info->numQueuesTx * 2565 sizeof(struct ucc_geth_send_queue_qd), 2566 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2567 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2568 if (netif_msg_ifup(ugeth)) 2569 ugeth_err 2570 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.", 2571 __func__); 2572 return -ENOMEM; 2573 } 2574 2575 ugeth->p_send_q_mem_reg = 2576 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2577 send_q_mem_reg_offset); 2578 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2579 2580 /* Setup the table */ 2581 /* Assume BD rings are already established */ 2582 for (i = 0; i < ug_info->numQueuesTx; i++) { 2583 endOfRing = 2584 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2585 1) * sizeof(struct qe_bd); 2586 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2587 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2588 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2589 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2590 last_bd_completed_address, 2591 (u32) virt_to_phys(endOfRing)); 2592 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2593 MEM_PART_MURAM) { 2594 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2595 (u32) immrbar_virt_to_phys(ugeth-> 2596 p_tx_bd_ring[i])); 2597 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2598 last_bd_completed_address, 2599 (u32) immrbar_virt_to_phys(endOfRing)); 2600 } 2601 } 2602 2603 /* schedulerbasepointer */ 2604 2605 if (ug_info->numQueuesTx > 1) { 2606 /* scheduler exists only if more than 1 tx queue */ 2607 ugeth->scheduler_offset = 2608 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2609 UCC_GETH_SCHEDULER_ALIGNMENT); 2610 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2611 if (netif_msg_ifup(ugeth)) 2612 ugeth_err 2613 ("%s: Can not allocate DPRAM memory for p_scheduler.", 2614 __func__); 2615 return -ENOMEM; 2616 } 2617 2618 ugeth->p_scheduler = 2619 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2620 scheduler_offset); 2621 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2622 ugeth->scheduler_offset); 2623 /* Zero out p_scheduler */ 2624 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); 2625 2626 /* Set values in scheduler */ 2627 out_be32(&ugeth->p_scheduler->mblinterval, 2628 ug_info->mblinterval); 2629 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2630 ug_info->nortsrbytetime); 2631 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2632 out_8(&ugeth->p_scheduler->strictpriorityq, 2633 ug_info->strictpriorityq); 2634 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2635 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2636 for (i = 0; i < NUM_TX_QUEUES; i++) 2637 out_8(&ugeth->p_scheduler->weightfactor[i], 2638 ug_info->weightfactor[i]); 2639 2640 /* Set pointers to cpucount registers in scheduler */ 2641 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2642 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2643 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2644 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2645 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2646 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2647 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2648 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2649 } 2650 2651 /* schedulerbasepointer */ 2652 /* TxRMON_PTR (statistics) */ 2653 if (ug_info-> 2654 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2655 ugeth->tx_fw_statistics_pram_offset = 2656 qe_muram_alloc(sizeof 2657 (struct ucc_geth_tx_firmware_statistics_pram), 2658 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2659 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2660 if (netif_msg_ifup(ugeth)) 2661 ugeth_err 2662 ("%s: Can not allocate DPRAM memory for" 2663 " p_tx_fw_statistics_pram.", 2664 __func__); 2665 return -ENOMEM; 2666 } 2667 ugeth->p_tx_fw_statistics_pram = 2668 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2669 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2670 /* Zero out p_tx_fw_statistics_pram */ 2671 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram, 2672 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); 2673 } 2674 2675 /* temoder */ 2676 /* Already has speed set */ 2677 2678 if (ug_info->numQueuesTx > 1) 2679 temoder |= TEMODER_SCHEDULER_ENABLE; 2680 if (ug_info->ipCheckSumGenerate) 2681 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2682 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2683 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2684 2685 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2686 2687 /* Function code register value to be used later */ 2688 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2689 /* Required for QE */ 2690 2691 /* function code register */ 2692 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2693 2694 /* Rx global PRAM */ 2695 /* Allocate global rx parameter RAM page */ 2696 ugeth->rx_glbl_pram_offset = 2697 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2698 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2699 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) { 2700 if (netif_msg_ifup(ugeth)) 2701 ugeth_err 2702 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.", 2703 __func__); 2704 return -ENOMEM; 2705 } 2706 ugeth->p_rx_glbl_pram = 2707 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth-> 2708 rx_glbl_pram_offset); 2709 /* Zero out p_rx_glbl_pram */ 2710 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); 2711 2712 /* Fill global PRAM */ 2713 2714 /* RQPTR */ 2715 /* Size varies with number of Rx threads */ 2716 ugeth->thread_dat_rx_offset = 2717 qe_muram_alloc(numThreadsRxNumerical * 2718 sizeof(struct ucc_geth_thread_data_rx), 2719 UCC_GETH_THREAD_DATA_ALIGNMENT); 2720 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2721 if (netif_msg_ifup(ugeth)) 2722 ugeth_err 2723 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.", 2724 __func__); 2725 return -ENOMEM; 2726 } 2727 2728 ugeth->p_thread_data_rx = 2729 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2730 thread_dat_rx_offset); 2731 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2732 2733 /* typeorlen */ 2734 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2735 2736 /* rxrmonbaseptr (statistics) */ 2737 if (ug_info-> 2738 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2739 ugeth->rx_fw_statistics_pram_offset = 2740 qe_muram_alloc(sizeof 2741 (struct ucc_geth_rx_firmware_statistics_pram), 2742 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2743 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2744 if (netif_msg_ifup(ugeth)) 2745 ugeth_err 2746 ("%s: Can not allocate DPRAM memory for" 2747 " p_rx_fw_statistics_pram.", __func__); 2748 return -ENOMEM; 2749 } 2750 ugeth->p_rx_fw_statistics_pram = 2751 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2752 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2753 /* Zero out p_rx_fw_statistics_pram */ 2754 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0, 2755 sizeof(struct ucc_geth_rx_firmware_statistics_pram)); 2756 } 2757 2758 /* intCoalescingPtr */ 2759 2760 /* Size varies with number of Rx queues */ 2761 ugeth->rx_irq_coalescing_tbl_offset = 2762 qe_muram_alloc(ug_info->numQueuesRx * 2763 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2764 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2765 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2766 if (netif_msg_ifup(ugeth)) 2767 ugeth_err 2768 ("%s: Can not allocate DPRAM memory for" 2769 " p_rx_irq_coalescing_tbl.", __func__); 2770 return -ENOMEM; 2771 } 2772 2773 ugeth->p_rx_irq_coalescing_tbl = 2774 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2775 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2776 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2777 ugeth->rx_irq_coalescing_tbl_offset); 2778 2779 /* Fill interrupt coalescing table */ 2780 for (i = 0; i < ug_info->numQueuesRx; i++) { 2781 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2782 interruptcoalescingmaxvalue, 2783 ug_info->interruptcoalescingmaxvalue[i]); 2784 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2785 interruptcoalescingcounter, 2786 ug_info->interruptcoalescingmaxvalue[i]); 2787 } 2788 2789 /* MRBLR */ 2790 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2791 &ugeth->p_rx_glbl_pram->mrblr); 2792 /* MFLR */ 2793 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2794 /* MINFLR */ 2795 init_min_frame_len(ug_info->minFrameLength, 2796 &ugeth->p_rx_glbl_pram->minflr, 2797 &ugeth->p_rx_glbl_pram->mrblr); 2798 /* MAXD1 */ 2799 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2800 /* MAXD2 */ 2801 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2802 2803 /* l2qt */ 2804 l2qt = 0; 2805 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2806 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2807 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2808 2809 /* l3qt */ 2810 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2811 l3qt = 0; 2812 for (i = 0; i < 8; i++) 2813 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2814 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2815 } 2816 2817 /* vlantype */ 2818 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2819 2820 /* vlantci */ 2821 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2822 2823 /* ecamptr */ 2824 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2825 2826 /* RBDQPTR */ 2827 /* Size varies with number of Rx queues */ 2828 ugeth->rx_bd_qs_tbl_offset = 2829 qe_muram_alloc(ug_info->numQueuesRx * 2830 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2831 sizeof(struct ucc_geth_rx_prefetched_bds)), 2832 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2833 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2834 if (netif_msg_ifup(ugeth)) 2835 ugeth_err 2836 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.", 2837 __func__); 2838 return -ENOMEM; 2839 } 2840 2841 ugeth->p_rx_bd_qs_tbl = 2842 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2843 rx_bd_qs_tbl_offset); 2844 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2845 /* Zero out p_rx_bd_qs_tbl */ 2846 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl, 2847 0, 2848 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2849 sizeof(struct ucc_geth_rx_prefetched_bds))); 2850 2851 /* Setup the table */ 2852 /* Assume BD rings are already established */ 2853 for (i = 0; i < ug_info->numQueuesRx; i++) { 2854 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2855 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2856 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2857 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2858 MEM_PART_MURAM) { 2859 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2860 (u32) immrbar_virt_to_phys(ugeth-> 2861 p_rx_bd_ring[i])); 2862 } 2863 /* rest of fields handled by QE */ 2864 } 2865 2866 /* remoder */ 2867 /* Already has speed set */ 2868 2869 if (ugeth->rx_extended_features) 2870 remoder |= REMODER_RX_EXTENDED_FEATURES; 2871 if (ug_info->rxExtendedFiltering) 2872 remoder |= REMODER_RX_EXTENDED_FILTERING; 2873 if (ug_info->dynamicMaxFrameLength) 2874 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2875 if (ug_info->dynamicMinFrameLength) 2876 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2877 remoder |= 2878 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2879 remoder |= 2880 ug_info-> 2881 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2882 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2883 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2884 if (ug_info->ipCheckSumCheck) 2885 remoder |= REMODER_IP_CHECKSUM_CHECK; 2886 if (ug_info->ipAddressAlignment) 2887 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2888 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2889 2890 /* Note that this function must be called */ 2891 /* ONLY AFTER p_tx_fw_statistics_pram */ 2892 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2893 init_firmware_statistics_gathering_mode((ug_info-> 2894 statisticsMode & 2895 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2896 (ug_info->statisticsMode & 2897 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2898 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2899 ugeth->tx_fw_statistics_pram_offset, 2900 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2901 ugeth->rx_fw_statistics_pram_offset, 2902 &ugeth->p_tx_glbl_pram->temoder, 2903 &ugeth->p_rx_glbl_pram->remoder); 2904 2905 /* function code register */ 2906 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2907 2908 /* initialize extended filtering */ 2909 if (ug_info->rxExtendedFiltering) { 2910 if (!ug_info->extendedFilteringChainPointer) { 2911 if (netif_msg_ifup(ugeth)) 2912 ugeth_err("%s: Null Extended Filtering Chain Pointer.", 2913 __func__); 2914 return -EINVAL; 2915 } 2916 2917 /* Allocate memory for extended filtering Mode Global 2918 Parameters */ 2919 ugeth->exf_glbl_param_offset = 2920 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2921 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2922 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2923 if (netif_msg_ifup(ugeth)) 2924 ugeth_err 2925 ("%s: Can not allocate DPRAM memory for" 2926 " p_exf_glbl_param.", __func__); 2927 return -ENOMEM; 2928 } 2929 2930 ugeth->p_exf_glbl_param = 2931 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2932 exf_glbl_param_offset); 2933 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2934 ugeth->exf_glbl_param_offset); 2935 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2936 (u32) ug_info->extendedFilteringChainPointer); 2937 2938 } else { /* initialize 82xx style address filtering */ 2939 2940 /* Init individual address recognition registers to disabled */ 2941 2942 for (j = 0; j < NUM_OF_PADDRS; j++) 2943 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2944 2945 p_82xx_addr_filt = 2946 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2947 p_rx_glbl_pram->addressfiltering; 2948 2949 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2950 ENET_ADDR_TYPE_GROUP); 2951 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2952 ENET_ADDR_TYPE_INDIVIDUAL); 2953 } 2954 2955 /* 2956 * Initialize UCC at QE level 2957 */ 2958 2959 command = QE_INIT_TX_RX; 2960 2961 /* Allocate shadow InitEnet command parameter structure. 2962 * This is needed because after the InitEnet command is executed, 2963 * the structure in DPRAM is released, because DPRAM is a premium 2964 * resource. 2965 * This shadow structure keeps a copy of what was done so that the 2966 * allocated resources can be released when the channel is freed. 2967 */ 2968 if (!(ugeth->p_init_enet_param_shadow = 2969 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2970 if (netif_msg_ifup(ugeth)) 2971 ugeth_err 2972 ("%s: Can not allocate memory for" 2973 " p_UccInitEnetParamShadows.", __func__); 2974 return -ENOMEM; 2975 } 2976 /* Zero out *p_init_enet_param_shadow */ 2977 memset((char *)ugeth->p_init_enet_param_shadow, 2978 0, sizeof(struct ucc_geth_init_pram)); 2979 2980 /* Fill shadow InitEnet command parameter structure */ 2981 2982 ugeth->p_init_enet_param_shadow->resinit1 = 2983 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2984 ugeth->p_init_enet_param_shadow->resinit2 = 2985 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2986 ugeth->p_init_enet_param_shadow->resinit3 = 2987 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2988 ugeth->p_init_enet_param_shadow->resinit4 = 2989 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2990 ugeth->p_init_enet_param_shadow->resinit5 = 2991 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2992 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2993 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2994 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2995 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2996 2997 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2998 ugeth->rx_glbl_pram_offset | ug_info->riscRx; 2999 if ((ug_info->largestexternallookupkeysize != 3000 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 3001 (ug_info->largestexternallookupkeysize != 3002 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 3003 (ug_info->largestexternallookupkeysize != 3004 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 3005 if (netif_msg_ifup(ugeth)) 3006 ugeth_err("%s: Invalid largest External Lookup Key Size.", 3007 __func__); 3008 return -EINVAL; 3009 } 3010 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 3011 ug_info->largestexternallookupkeysize; 3012 size = sizeof(struct ucc_geth_thread_rx_pram); 3013 if (ug_info->rxExtendedFiltering) { 3014 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 3015 if (ug_info->largestexternallookupkeysize == 3016 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 3017 size += 3018 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 3019 if (ug_info->largestexternallookupkeysize == 3020 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 3021 size += 3022 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 3023 } 3024 3025 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 3026 p_init_enet_param_shadow->rxthread[0]), 3027 (u8) (numThreadsRxNumerical + 1) 3028 /* Rx needs one extra for terminator */ 3029 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 3030 ug_info->riscRx, 1)) != 0) { 3031 if (netif_msg_ifup(ugeth)) 3032 ugeth_err("%s: Can not fill p_init_enet_param_shadow.", 3033 __func__); 3034 return ret_val; 3035 } 3036 3037 ugeth->p_init_enet_param_shadow->txglobal = 3038 ugeth->tx_glbl_pram_offset | ug_info->riscTx; 3039 if ((ret_val = 3040 fill_init_enet_entries(ugeth, 3041 &(ugeth->p_init_enet_param_shadow-> 3042 txthread[0]), numThreadsTxNumerical, 3043 sizeof(struct ucc_geth_thread_tx_pram), 3044 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 3045 ug_info->riscTx, 0)) != 0) { 3046 if (netif_msg_ifup(ugeth)) 3047 ugeth_err("%s: Can not fill p_init_enet_param_shadow.", 3048 __func__); 3049 return ret_val; 3050 } 3051 3052 /* Load Rx bds with buffers */ 3053 for (i = 0; i < ug_info->numQueuesRx; i++) { 3054 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 3055 if (netif_msg_ifup(ugeth)) 3056 ugeth_err("%s: Can not fill Rx bds with buffers.", 3057 __func__); 3058 return ret_val; 3059 } 3060 } 3061 3062 /* Allocate InitEnet command parameter structure */ 3063 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 3064 if (IS_ERR_VALUE(init_enet_pram_offset)) { 3065 if (netif_msg_ifup(ugeth)) 3066 ugeth_err 3067 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.", 3068 __func__); 3069 return -ENOMEM; 3070 } 3071 p_init_enet_pram = 3072 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 3073 3074 /* Copy shadow InitEnet command parameter structure into PRAM */ 3075 out_8(&p_init_enet_pram->resinit1, 3076 ugeth->p_init_enet_param_shadow->resinit1); 3077 out_8(&p_init_enet_pram->resinit2, 3078 ugeth->p_init_enet_param_shadow->resinit2); 3079 out_8(&p_init_enet_pram->resinit3, 3080 ugeth->p_init_enet_param_shadow->resinit3); 3081 out_8(&p_init_enet_pram->resinit4, 3082 ugeth->p_init_enet_param_shadow->resinit4); 3083 out_be16(&p_init_enet_pram->resinit5, 3084 ugeth->p_init_enet_param_shadow->resinit5); 3085 out_8(&p_init_enet_pram->largestexternallookupkeysize, 3086 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 3087 out_be32(&p_init_enet_pram->rgftgfrxglobal, 3088 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 3089 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 3090 out_be32(&p_init_enet_pram->rxthread[i], 3091 ugeth->p_init_enet_param_shadow->rxthread[i]); 3092 out_be32(&p_init_enet_pram->txglobal, 3093 ugeth->p_init_enet_param_shadow->txglobal); 3094 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 3095 out_be32(&p_init_enet_pram->txthread[i], 3096 ugeth->p_init_enet_param_shadow->txthread[i]); 3097 3098 /* Issue QE command */ 3099 cecr_subblock = 3100 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 3101 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 3102 init_enet_pram_offset); 3103 3104 /* Free InitEnet command parameter */ 3105 qe_muram_free(init_enet_pram_offset); 3106 3107 return 0; 3108} 3109 3110/* This is called by the kernel when a frame is ready for transmission. */ 3111/* It is pointed to by the dev->hard_start_xmit function pointer */ 3112static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 3113{ 3114 struct ucc_geth_private *ugeth = netdev_priv(dev); 3115#ifdef CONFIG_UGETH_TX_ON_DEMAND 3116 struct ucc_fast_private *uccf; 3117#endif 3118 u8 __iomem *bd; /* BD pointer */ 3119 u32 bd_status; 3120 u8 txQ = 0; 3121 unsigned long flags; 3122 3123 ugeth_vdbg("%s: IN", __func__); 3124 3125 spin_lock_irqsave(&ugeth->lock, flags); 3126 3127 dev->stats.tx_bytes += skb->len; 3128 3129 /* Start from the next BD that should be filled */ 3130 bd = ugeth->txBd[txQ]; 3131 bd_status = in_be32((u32 __iomem *)bd); 3132 /* Save the skb pointer so we can free it later */ 3133 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 3134 3135 /* Update the current skb pointer (wrapping if this was the last) */ 3136 ugeth->skb_curtx[txQ] = 3137 (ugeth->skb_curtx[txQ] + 3138 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3139 3140 /* set up the buffer descriptor */ 3141 out_be32(&((struct qe_bd __iomem *)bd)->buf, 3142 dma_map_single(ugeth->dev, skb->data, 3143 skb->len, DMA_TO_DEVICE)); 3144 3145 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 3146 3147 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 3148 3149 /* set bd status and length */ 3150 out_be32((u32 __iomem *)bd, bd_status); 3151 3152 /* Move to next BD in the ring */ 3153 if (!(bd_status & T_W)) 3154 bd += sizeof(struct qe_bd); 3155 else 3156 bd = ugeth->p_tx_bd_ring[txQ]; 3157 3158 /* If the next BD still needs to be cleaned up, then the bds 3159 are full. We need to tell the kernel to stop sending us stuff. */ 3160 if (bd == ugeth->confBd[txQ]) { 3161 if (!netif_queue_stopped(dev)) 3162 netif_stop_queue(dev); 3163 } 3164 3165 ugeth->txBd[txQ] = bd; 3166 3167 if (ugeth->p_scheduler) { 3168 ugeth->cpucount[txQ]++; 3169 /* Indicate to QE that there are more Tx bds ready for 3170 transmission */ 3171 /* This is done by writing a running counter of the bd 3172 count to the scheduler PRAM. */ 3173 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 3174 } 3175 3176#ifdef CONFIG_UGETH_TX_ON_DEMAND 3177 uccf = ugeth->uccf; 3178 out_be16(uccf->p_utodr, UCC_FAST_TOD); 3179#endif 3180 spin_unlock_irqrestore(&ugeth->lock, flags); 3181 3182 return NETDEV_TX_OK; 3183} 3184 3185static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3186{ 3187 struct sk_buff *skb; 3188 u8 __iomem *bd; 3189 u16 length, howmany = 0; 3190 u32 bd_status; 3191 u8 *bdBuffer; 3192 struct net_device *dev; 3193 3194 ugeth_vdbg("%s: IN", __func__); 3195 3196 dev = ugeth->ndev; 3197 3198 /* collect received buffers */ 3199 bd = ugeth->rxBd[rxQ]; 3200 3201 bd_status = in_be32((u32 __iomem *)bd); 3202 3203 /* while there are received buffers and BD is full (~R_E) */ 3204 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 3205 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 3206 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 3207 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 3208 3209 /* determine whether buffer is first, last, first and last 3210 (single buffer frame) or middle (not first and not last) */ 3211 if (!skb || 3212 (!(bd_status & (R_F | R_L))) || 3213 (bd_status & R_ERRORS_FATAL)) { 3214 if (netif_msg_rx_err(ugeth)) 3215 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x", 3216 __func__, __LINE__, (u32) skb); 3217 if (skb) { 3218 skb->data = skb->head + NET_SKB_PAD; 3219 skb->len = 0; 3220 skb_reset_tail_pointer(skb); 3221 __skb_queue_head(&ugeth->rx_recycle, skb); 3222 } 3223 3224 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 3225 dev->stats.rx_dropped++; 3226 } else { 3227 dev->stats.rx_packets++; 3228 howmany++; 3229 3230 /* Prep the skb for the packet */ 3231 skb_put(skb, length); 3232 3233 /* Tell the skb what kind of packet this is */ 3234 skb->protocol = eth_type_trans(skb, ugeth->ndev); 3235 3236 dev->stats.rx_bytes += length; 3237 /* Send the packet up the stack */ 3238 netif_receive_skb(skb); 3239 } 3240 3241 skb = get_new_skb(ugeth, bd); 3242 if (!skb) { 3243 if (netif_msg_rx_err(ugeth)) 3244 ugeth_warn("%s: No Rx Data Buffer", __func__); 3245 dev->stats.rx_dropped++; 3246 break; 3247 } 3248 3249 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 3250 3251 /* update to point at the next skb */ 3252 ugeth->skb_currx[rxQ] = 3253 (ugeth->skb_currx[rxQ] + 3254 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 3255 3256 if (bd_status & R_W) 3257 bd = ugeth->p_rx_bd_ring[rxQ]; 3258 else 3259 bd += sizeof(struct qe_bd); 3260 3261 bd_status = in_be32((u32 __iomem *)bd); 3262 } 3263 3264 ugeth->rxBd[rxQ] = bd; 3265 return howmany; 3266} 3267 3268static int ucc_geth_tx(struct net_device *dev, u8 txQ) 3269{ 3270 /* Start from the next BD that should be filled */ 3271 struct ucc_geth_private *ugeth = netdev_priv(dev); 3272 u8 __iomem *bd; /* BD pointer */ 3273 u32 bd_status; 3274 3275 bd = ugeth->confBd[txQ]; 3276 bd_status = in_be32((u32 __iomem *)bd); 3277 3278 /* Normal processing. */ 3279 while ((bd_status & T_R) == 0) { 3280 struct sk_buff *skb; 3281 3282 /* BD contains already transmitted buffer. */ 3283 /* Handle the transmitted buffer and release */ 3284 /* the BD to be used with the current frame */ 3285 3286 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 3287 if (!skb) 3288 break; 3289 3290 dev->stats.tx_packets++; 3291 3292 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN && 3293 skb_recycle_check(skb, 3294 ugeth->ug_info->uf_info.max_rx_buf_length + 3295 UCC_GETH_RX_DATA_BUF_ALIGNMENT)) 3296 __skb_queue_head(&ugeth->rx_recycle, skb); 3297 else 3298 dev_kfree_skb(skb); 3299 3300 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 3301 ugeth->skb_dirtytx[txQ] = 3302 (ugeth->skb_dirtytx[txQ] + 3303 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3304 3305 /* We freed a buffer, so now we can restart transmission */ 3306 if (netif_queue_stopped(dev)) 3307 netif_wake_queue(dev); 3308 3309 /* Advance the confirmation BD pointer */ 3310 if (!(bd_status & T_W)) 3311 bd += sizeof(struct qe_bd); 3312 else 3313 bd = ugeth->p_tx_bd_ring[txQ]; 3314 bd_status = in_be32((u32 __iomem *)bd); 3315 } 3316 ugeth->confBd[txQ] = bd; 3317 return 0; 3318} 3319 3320static int ucc_geth_poll(struct napi_struct *napi, int budget) 3321{ 3322 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3323 struct ucc_geth_info *ug_info; 3324 int howmany, i; 3325 3326 ug_info = ugeth->ug_info; 3327 3328 /* Tx event processing */ 3329 spin_lock(&ugeth->lock); 3330 for (i = 0; i < ug_info->numQueuesTx; i++) 3331 ucc_geth_tx(ugeth->ndev, i); 3332 spin_unlock(&ugeth->lock); 3333 3334 howmany = 0; 3335 for (i = 0; i < ug_info->numQueuesRx; i++) 3336 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3337 3338 if (howmany < budget) { 3339 napi_complete(napi); 3340 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3341 } 3342 3343 return howmany; 3344} 3345 3346static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3347{ 3348 struct net_device *dev = info; 3349 struct ucc_geth_private *ugeth = netdev_priv(dev); 3350 struct ucc_fast_private *uccf; 3351 struct ucc_geth_info *ug_info; 3352 register u32 ucce; 3353 register u32 uccm; 3354 3355 ugeth_vdbg("%s: IN", __func__); 3356 3357 uccf = ugeth->uccf; 3358 ug_info = ugeth->ug_info; 3359 3360 /* read and clear events */ 3361 ucce = (u32) in_be32(uccf->p_ucce); 3362 uccm = (u32) in_be32(uccf->p_uccm); 3363 ucce &= uccm; 3364 out_be32(uccf->p_ucce, ucce); 3365 3366 /* check for receive events that require processing */ 3367 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3368 if (napi_schedule_prep(&ugeth->napi)) { 3369 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3370 out_be32(uccf->p_uccm, uccm); 3371 __napi_schedule(&ugeth->napi); 3372 } 3373 } 3374 3375 /* Errors and other events */ 3376 if (ucce & UCCE_OTHER) { 3377 if (ucce & UCC_GETH_UCCE_BSY) 3378 dev->stats.rx_errors++; 3379 if (ucce & UCC_GETH_UCCE_TXE) 3380 dev->stats.tx_errors++; 3381 } 3382 3383 return IRQ_HANDLED; 3384} 3385 3386#ifdef CONFIG_NET_POLL_CONTROLLER 3387/* 3388 * Polling 'interrupt' - used by things like netconsole to send skbs 3389 * without having to re-enable interrupts. It's not called while 3390 * the interrupt routine is executing. 3391 */ 3392static void ucc_netpoll(struct net_device *dev) 3393{ 3394 struct ucc_geth_private *ugeth = netdev_priv(dev); 3395 int irq = ugeth->ug_info->uf_info.irq; 3396 3397 disable_irq(irq); 3398 ucc_geth_irq_handler(irq, dev); 3399 enable_irq(irq); 3400} 3401#endif /* CONFIG_NET_POLL_CONTROLLER */ 3402 3403static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3404{ 3405 struct ucc_geth_private *ugeth = netdev_priv(dev); 3406 struct sockaddr *addr = p; 3407 3408 if (!is_valid_ether_addr(addr->sa_data)) 3409 return -EADDRNOTAVAIL; 3410 3411 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3412 3413 /* 3414 * If device is not running, we will set mac addr register 3415 * when opening the device. 3416 */ 3417 if (!netif_running(dev)) 3418 return 0; 3419 3420 spin_lock_irq(&ugeth->lock); 3421 init_mac_station_addr_regs(dev->dev_addr[0], 3422 dev->dev_addr[1], 3423 dev->dev_addr[2], 3424 dev->dev_addr[3], 3425 dev->dev_addr[4], 3426 dev->dev_addr[5], 3427 &ugeth->ug_regs->macstnaddr1, 3428 &ugeth->ug_regs->macstnaddr2); 3429 spin_unlock_irq(&ugeth->lock); 3430 3431 return 0; 3432} 3433 3434static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3435{ 3436 struct net_device *dev = ugeth->ndev; 3437 int err; 3438 3439 err = ucc_struct_init(ugeth); 3440 if (err) { 3441 if (netif_msg_ifup(ugeth)) 3442 ugeth_err("%s: Cannot configure internal struct, " 3443 "aborting.", dev->name); 3444 goto err; 3445 } 3446 3447 err = ucc_geth_startup(ugeth); 3448 if (err) { 3449 if (netif_msg_ifup(ugeth)) 3450 ugeth_err("%s: Cannot configure net device, aborting.", 3451 dev->name); 3452 goto err; 3453 } 3454 3455 err = adjust_enet_interface(ugeth); 3456 if (err) { 3457 if (netif_msg_ifup(ugeth)) 3458 ugeth_err("%s: Cannot configure net device, aborting.", 3459 dev->name); 3460 goto err; 3461 } 3462 3463 /* Set MACSTNADDR1, MACSTNADDR2 */ 3464 /* For more details see the hardware spec. */ 3465 init_mac_station_addr_regs(dev->dev_addr[0], 3466 dev->dev_addr[1], 3467 dev->dev_addr[2], 3468 dev->dev_addr[3], 3469 dev->dev_addr[4], 3470 dev->dev_addr[5], 3471 &ugeth->ug_regs->macstnaddr1, 3472 &ugeth->ug_regs->macstnaddr2); 3473 3474 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3475 if (err) { 3476 if (netif_msg_ifup(ugeth)) 3477 ugeth_err("%s: Cannot enable net device, aborting.", dev->name); 3478 goto err; 3479 } 3480 3481 return 0; 3482err: 3483 ucc_geth_stop(ugeth); 3484 return err; 3485} 3486 3487/* Called when something needs to use the ethernet device */ 3488/* Returns 0 for success. */ 3489static int ucc_geth_open(struct net_device *dev) 3490{ 3491 struct ucc_geth_private *ugeth = netdev_priv(dev); 3492 int err; 3493 3494 ugeth_vdbg("%s: IN", __func__); 3495 3496 /* Test station address */ 3497 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3498 if (netif_msg_ifup(ugeth)) 3499 ugeth_err("%s: Multicast address used for station " 3500 "address - is this what you wanted?", 3501 __func__); 3502 return -EINVAL; 3503 } 3504 3505 err = init_phy(dev); 3506 if (err) { 3507 if (netif_msg_ifup(ugeth)) 3508 ugeth_err("%s: Cannot initialize PHY, aborting.", 3509 dev->name); 3510 return err; 3511 } 3512 3513 err = ucc_geth_init_mac(ugeth); 3514 if (err) { 3515 if (netif_msg_ifup(ugeth)) 3516 ugeth_err("%s: Cannot initialize MAC, aborting.", 3517 dev->name); 3518 goto err; 3519 } 3520 3521 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3522 0, "UCC Geth", dev); 3523 if (err) { 3524 if (netif_msg_ifup(ugeth)) 3525 ugeth_err("%s: Cannot get IRQ for net device, aborting.", 3526 dev->name); 3527 goto err; 3528 } 3529 3530 phy_start(ugeth->phydev); 3531 napi_enable(&ugeth->napi); 3532 netif_start_queue(dev); 3533 3534 device_set_wakeup_capable(&dev->dev, 3535 qe_alive_during_sleep() || ugeth->phydev->irq); 3536 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3537 3538 return err; 3539 3540err: 3541 ucc_geth_stop(ugeth); 3542 return err; 3543} 3544 3545/* Stops the kernel queue, and halts the controller */ 3546static int ucc_geth_close(struct net_device *dev) 3547{ 3548 struct ucc_geth_private *ugeth = netdev_priv(dev); 3549 3550 ugeth_vdbg("%s: IN", __func__); 3551 3552 napi_disable(&ugeth->napi); 3553 3554 cancel_work_sync(&ugeth->timeout_work); 3555 ucc_geth_stop(ugeth); 3556 phy_disconnect(ugeth->phydev); 3557 ugeth->phydev = NULL; 3558 3559 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3560 3561 netif_stop_queue(dev); 3562 3563 return 0; 3564} 3565 3566/* Reopen device. This will reset the MAC and PHY. */ 3567static void ucc_geth_timeout_work(struct work_struct *work) 3568{ 3569 struct ucc_geth_private *ugeth; 3570 struct net_device *dev; 3571 3572 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3573 dev = ugeth->ndev; 3574 3575 ugeth_vdbg("%s: IN", __func__); 3576 3577 dev->stats.tx_errors++; 3578 3579 ugeth_dump_regs(ugeth); 3580 3581 if (dev->flags & IFF_UP) { 3582 /* 3583 * Must reset MAC *and* PHY. This is done by reopening 3584 * the device. 3585 */ 3586 netif_tx_stop_all_queues(dev); 3587 ucc_geth_stop(ugeth); 3588 ucc_geth_init_mac(ugeth); 3589 /* Must start PHY here */ 3590 phy_start(ugeth->phydev); 3591 netif_tx_start_all_queues(dev); 3592 } 3593 3594 netif_tx_schedule_all(dev); 3595} 3596 3597/* 3598 * ucc_geth_timeout gets called when a packet has not been 3599 * transmitted after a set amount of time. 3600 */ 3601static void ucc_geth_timeout(struct net_device *dev) 3602{ 3603 struct ucc_geth_private *ugeth = netdev_priv(dev); 3604 3605 schedule_work(&ugeth->timeout_work); 3606} 3607 3608 3609#ifdef CONFIG_PM 3610 3611static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3612{ 3613 struct net_device *ndev = dev_get_drvdata(&ofdev->dev); 3614 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3615 3616 if (!netif_running(ndev)) 3617 return 0; 3618 3619 netif_device_detach(ndev); 3620 napi_disable(&ugeth->napi); 3621 3622 /* 3623 * Disable the controller, otherwise we'll wakeup on any network 3624 * activity. 3625 */ 3626 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3627 3628 if (ugeth->wol_en & WAKE_MAGIC) { 3629 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3630 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3631 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3632 } else if (!(ugeth->wol_en & WAKE_PHY)) { 3633 phy_stop(ugeth->phydev); 3634 } 3635 3636 return 0; 3637} 3638 3639static int ucc_geth_resume(struct platform_device *ofdev) 3640{ 3641 struct net_device *ndev = dev_get_drvdata(&ofdev->dev); 3642 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3643 int err; 3644 3645 if (!netif_running(ndev)) 3646 return 0; 3647 3648 if (qe_alive_during_sleep()) { 3649 if (ugeth->wol_en & WAKE_MAGIC) { 3650 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3651 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3652 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3653 } 3654 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3655 } else { 3656 /* 3657 * Full reinitialization is required if QE shuts down 3658 * during sleep. 3659 */ 3660 ucc_geth_memclean(ugeth); 3661 3662 err = ucc_geth_init_mac(ugeth); 3663 if (err) { 3664 ugeth_err("%s: Cannot initialize MAC, aborting.", 3665 ndev->name); 3666 return err; 3667 } 3668 } 3669 3670 ugeth->oldlink = 0; 3671 ugeth->oldspeed = 0; 3672 ugeth->oldduplex = -1; 3673 3674 phy_stop(ugeth->phydev); 3675 phy_start(ugeth->phydev); 3676 3677 napi_enable(&ugeth->napi); 3678 netif_device_attach(ndev); 3679 3680 return 0; 3681} 3682 3683#else 3684#define ucc_geth_suspend NULL 3685#define ucc_geth_resume NULL 3686#endif 3687 3688static phy_interface_t to_phy_interface(const char *phy_connection_type) 3689{ 3690 if (strcasecmp(phy_connection_type, "mii") == 0) 3691 return PHY_INTERFACE_MODE_MII; 3692 if (strcasecmp(phy_connection_type, "gmii") == 0) 3693 return PHY_INTERFACE_MODE_GMII; 3694 if (strcasecmp(phy_connection_type, "tbi") == 0) 3695 return PHY_INTERFACE_MODE_TBI; 3696 if (strcasecmp(phy_connection_type, "rmii") == 0) 3697 return PHY_INTERFACE_MODE_RMII; 3698 if (strcasecmp(phy_connection_type, "rgmii") == 0) 3699 return PHY_INTERFACE_MODE_RGMII; 3700 if (strcasecmp(phy_connection_type, "rgmii-id") == 0) 3701 return PHY_INTERFACE_MODE_RGMII_ID; 3702 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0) 3703 return PHY_INTERFACE_MODE_RGMII_TXID; 3704 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0) 3705 return PHY_INTERFACE_MODE_RGMII_RXID; 3706 if (strcasecmp(phy_connection_type, "rtbi") == 0) 3707 return PHY_INTERFACE_MODE_RTBI; 3708 if (strcasecmp(phy_connection_type, "sgmii") == 0) 3709 return PHY_INTERFACE_MODE_SGMII; 3710 3711 return PHY_INTERFACE_MODE_MII; 3712} 3713 3714static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3715{ 3716 struct ucc_geth_private *ugeth = netdev_priv(dev); 3717 3718 if (!netif_running(dev)) 3719 return -EINVAL; 3720 3721 if (!ugeth->phydev) 3722 return -ENODEV; 3723 3724 return phy_mii_ioctl(ugeth->phydev, rq, cmd); 3725} 3726 3727static const struct net_device_ops ucc_geth_netdev_ops = { 3728 .ndo_open = ucc_geth_open, 3729 .ndo_stop = ucc_geth_close, 3730 .ndo_start_xmit = ucc_geth_start_xmit, 3731 .ndo_validate_addr = eth_validate_addr, 3732 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3733 .ndo_change_mtu = eth_change_mtu, 3734 .ndo_set_multicast_list = ucc_geth_set_multi, 3735 .ndo_tx_timeout = ucc_geth_timeout, 3736 .ndo_do_ioctl = ucc_geth_ioctl, 3737#ifdef CONFIG_NET_POLL_CONTROLLER 3738 .ndo_poll_controller = ucc_netpoll, 3739#endif 3740}; 3741 3742static int ucc_geth_probe(struct platform_device* ofdev, const struct of_device_id *match) 3743{ 3744 struct device *device = &ofdev->dev; 3745 struct device_node *np = ofdev->dev.of_node; 3746 struct net_device *dev = NULL; 3747 struct ucc_geth_private *ugeth = NULL; 3748 struct ucc_geth_info *ug_info; 3749 struct resource res; 3750 int err, ucc_num, max_speed = 0; 3751 const unsigned int *prop; 3752 const char *sprop; 3753 const void *mac_addr; 3754 phy_interface_t phy_interface; 3755 static const int enet_to_speed[] = { 3756 SPEED_10, SPEED_10, SPEED_10, 3757 SPEED_100, SPEED_100, SPEED_100, 3758 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000, 3759 }; 3760 static const phy_interface_t enet_to_phy_interface[] = { 3761 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII, 3762 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII, 3763 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, 3764 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, 3765 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, 3766 PHY_INTERFACE_MODE_SGMII, 3767 }; 3768 3769 ugeth_vdbg("%s: IN", __func__); 3770 3771 prop = of_get_property(np, "cell-index", NULL); 3772 if (!prop) { 3773 prop = of_get_property(np, "device-id", NULL); 3774 if (!prop) 3775 return -ENODEV; 3776 } 3777 3778 ucc_num = *prop - 1; 3779 if ((ucc_num < 0) || (ucc_num > 7)) 3780 return -ENODEV; 3781 3782 ug_info = &ugeth_info[ucc_num]; 3783 if (ug_info == NULL) { 3784 if (netif_msg_probe(&debug)) 3785 ugeth_err("%s: [%d] Missing additional data!", 3786 __func__, ucc_num); 3787 return -ENODEV; 3788 } 3789 3790 ug_info->uf_info.ucc_num = ucc_num; 3791 3792 sprop = of_get_property(np, "rx-clock-name", NULL); 3793 if (sprop) { 3794 ug_info->uf_info.rx_clock = qe_clock_source(sprop); 3795 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) || 3796 (ug_info->uf_info.rx_clock > QE_CLK24)) { 3797 printk(KERN_ERR 3798 "ucc_geth: invalid rx-clock-name property\n"); 3799 return -EINVAL; 3800 } 3801 } else { 3802 prop = of_get_property(np, "rx-clock", NULL); 3803 if (!prop) { 3804 /* If both rx-clock-name and rx-clock are missing, 3805 we want to tell people to use rx-clock-name. */ 3806 printk(KERN_ERR 3807 "ucc_geth: missing rx-clock-name property\n"); 3808 return -EINVAL; 3809 } 3810 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3811 printk(KERN_ERR 3812 "ucc_geth: invalid rx-clock propperty\n"); 3813 return -EINVAL; 3814 } 3815 ug_info->uf_info.rx_clock = *prop; 3816 } 3817 3818 sprop = of_get_property(np, "tx-clock-name", NULL); 3819 if (sprop) { 3820 ug_info->uf_info.tx_clock = qe_clock_source(sprop); 3821 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) || 3822 (ug_info->uf_info.tx_clock > QE_CLK24)) { 3823 printk(KERN_ERR 3824 "ucc_geth: invalid tx-clock-name property\n"); 3825 return -EINVAL; 3826 } 3827 } else { 3828 prop = of_get_property(np, "tx-clock", NULL); 3829 if (!prop) { 3830 printk(KERN_ERR 3831 "ucc_geth: missing tx-clock-name property\n"); 3832 return -EINVAL; 3833 } 3834 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3835 printk(KERN_ERR 3836 "ucc_geth: invalid tx-clock property\n"); 3837 return -EINVAL; 3838 } 3839 ug_info->uf_info.tx_clock = *prop; 3840 } 3841 3842 err = of_address_to_resource(np, 0, &res); 3843 if (err) 3844 return -EINVAL; 3845 3846 ug_info->uf_info.regs = res.start; 3847 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3848 3849 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0); 3850 3851 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3852 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3853 3854 /* get the phy interface type, or default to MII */ 3855 prop = of_get_property(np, "phy-connection-type", NULL); 3856 if (!prop) { 3857 /* handle interface property present in old trees */ 3858 prop = of_get_property(ug_info->phy_node, "interface", NULL); 3859 if (prop != NULL) { 3860 phy_interface = enet_to_phy_interface[*prop]; 3861 max_speed = enet_to_speed[*prop]; 3862 } else 3863 phy_interface = PHY_INTERFACE_MODE_MII; 3864 } else { 3865 phy_interface = to_phy_interface((const char *)prop); 3866 } 3867 3868 /* get speed, or derive from PHY interface */ 3869 if (max_speed == 0) 3870 switch (phy_interface) { 3871 case PHY_INTERFACE_MODE_GMII: 3872 case PHY_INTERFACE_MODE_RGMII: 3873 case PHY_INTERFACE_MODE_RGMII_ID: 3874 case PHY_INTERFACE_MODE_RGMII_RXID: 3875 case PHY_INTERFACE_MODE_RGMII_TXID: 3876 case PHY_INTERFACE_MODE_TBI: 3877 case PHY_INTERFACE_MODE_RTBI: 3878 case PHY_INTERFACE_MODE_SGMII: 3879 max_speed = SPEED_1000; 3880 break; 3881 default: 3882 max_speed = SPEED_100; 3883 break; 3884 } 3885 3886 if (max_speed == SPEED_1000) { 3887 /* configure muram FIFOs for gigabit operation */ 3888 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3889 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3890 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3891 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3892 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3893 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3894 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3895 3896 /* If QE's snum number is 46 which means we need to support 3897 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3898 * more Threads to Rx. 3899 */ 3900 if (qe_get_num_of_snums() == 46) 3901 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3902 else 3903 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3904 } 3905 3906 if (netif_msg_probe(&debug)) 3907 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d)\n", 3908 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs, 3909 ug_info->uf_info.irq); 3910 3911 /* Create an ethernet device instance */ 3912 dev = alloc_etherdev(sizeof(*ugeth)); 3913 3914 if (dev == NULL) 3915 return -ENOMEM; 3916 3917 ugeth = netdev_priv(dev); 3918 spin_lock_init(&ugeth->lock); 3919 3920 /* Create CQs for hash tables */ 3921 INIT_LIST_HEAD(&ugeth->group_hash_q); 3922 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3923 3924 dev_set_drvdata(device, dev); 3925 3926 /* Set the dev->base_addr to the gfar reg region */ 3927 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3928 3929 SET_NETDEV_DEV(dev, device); 3930 3931 /* Fill in the dev structure */ 3932 uec_set_ethtool_ops(dev); 3933 dev->netdev_ops = &ucc_geth_netdev_ops; 3934 dev->watchdog_timeo = TX_TIMEOUT; 3935 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3936 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64); 3937 dev->mtu = 1500; 3938 3939 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3940 ugeth->phy_interface = phy_interface; 3941 ugeth->max_speed = max_speed; 3942 3943 err = register_netdev(dev); 3944 if (err) { 3945 if (netif_msg_probe(ugeth)) 3946 ugeth_err("%s: Cannot register net device, aborting.", 3947 dev->name); 3948 free_netdev(dev); 3949 return err; 3950 } 3951 3952 mac_addr = of_get_mac_address(np); 3953 if (mac_addr) 3954 memcpy(dev->dev_addr, mac_addr, 6); 3955 3956 ugeth->ug_info = ug_info; 3957 ugeth->dev = device; 3958 ugeth->ndev = dev; 3959 ugeth->node = np; 3960 3961 return 0; 3962} 3963 3964static int ucc_geth_remove(struct platform_device* ofdev) 3965{ 3966 struct device *device = &ofdev->dev; 3967 struct net_device *dev = dev_get_drvdata(device); 3968 struct ucc_geth_private *ugeth = netdev_priv(dev); 3969 3970 unregister_netdev(dev); 3971 free_netdev(dev); 3972 ucc_geth_memclean(ugeth); 3973 dev_set_drvdata(device, NULL); 3974 3975 return 0; 3976} 3977 3978static struct of_device_id ucc_geth_match[] = { 3979 { 3980 .type = "network", 3981 .compatible = "ucc_geth", 3982 }, 3983 {}, 3984}; 3985 3986MODULE_DEVICE_TABLE(of, ucc_geth_match); 3987 3988static struct of_platform_driver ucc_geth_driver = { 3989 .driver = { 3990 .name = DRV_NAME, 3991 .owner = THIS_MODULE, 3992 .of_match_table = ucc_geth_match, 3993 }, 3994 .probe = ucc_geth_probe, 3995 .remove = ucc_geth_remove, 3996 .suspend = ucc_geth_suspend, 3997 .resume = ucc_geth_resume, 3998}; 3999 4000static int __init ucc_geth_init(void) 4001{ 4002 int i, ret; 4003 4004 if (netif_msg_drv(&debug)) 4005 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n"); 4006 for (i = 0; i < 8; i++) 4007 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 4008 sizeof(ugeth_primary_info)); 4009 4010 ret = of_register_platform_driver(&ucc_geth_driver); 4011 4012 return ret; 4013} 4014 4015static void __exit ucc_geth_exit(void) 4016{ 4017 of_unregister_platform_driver(&ucc_geth_driver); 4018} 4019 4020module_init(ucc_geth_init); 4021module_exit(ucc_geth_exit); 4022 4023MODULE_AUTHOR("Freescale Semiconductor, Inc"); 4024MODULE_DESCRIPTION(DRV_DESC); 4025MODULE_VERSION(DRV_VERSION); 4026MODULE_LICENSE("GPL");