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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/compiler.h>
38#include <linux/list.h>
39#include <linux/mutex.h>
40#include <linux/netdevice.h>
41#include <linux/inet_lro.h>
42
43#include <linux/mlx4/device.h>
44#include <linux/mlx4/qp.h>
45#include <linux/mlx4/cq.h>
46#include <linux/mlx4/srq.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "en_port.h"
50
51#define DRV_NAME "mlx4_en"
52#define DRV_VERSION "1.4.1.1"
53#define DRV_RELDATE "June 2009"
54
55#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
56
57/*
58 * Device constants
59 */
60
61
62#define MLX4_EN_PAGE_SHIFT 12
63#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
64#define MAX_TX_RINGS 16
65#define MAX_RX_RINGS 16
66#define TXBB_SIZE 64
67#define HEADROOM (2048 / TXBB_SIZE + 1)
68#define STAMP_STRIDE 64
69#define STAMP_DWORDS (STAMP_STRIDE / 4)
70#define STAMP_SHIFT 31
71#define STAMP_VAL 0x7fffffff
72#define STATS_DELAY (HZ / 4)
73
74/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
75#define MAX_DESC_SIZE 512
76#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
77
78/*
79 * OS related constants and tunables
80 */
81
82#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
83
84#define MLX4_EN_ALLOC_ORDER 2
85#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
86
87#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
88
89/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
90 * and 4K allocations) */
91enum {
92 FRAG_SZ0 = 512 - NET_IP_ALIGN,
93 FRAG_SZ1 = 1024,
94 FRAG_SZ2 = 4096,
95 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
96};
97#define MLX4_EN_MAX_RX_FRAGS 4
98
99/* Maximum ring sizes */
100#define MLX4_EN_MAX_TX_SIZE 8192
101#define MLX4_EN_MAX_RX_SIZE 8192
102
103/* Minimum ring size for our page-allocation sceme to work */
104#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
105#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
106
107#define MLX4_EN_SMALL_PKT_SIZE 64
108#define MLX4_EN_NUM_TX_RINGS 8
109#define MLX4_EN_NUM_PPP_RINGS 8
110#define MLX4_EN_DEF_TX_RING_SIZE 512
111#define MLX4_EN_DEF_RX_RING_SIZE 1024
112
113/* Target number of packets to coalesce with interrupt moderation */
114#define MLX4_EN_RX_COAL_TARGET 44
115#define MLX4_EN_RX_COAL_TIME 0x10
116
117#define MLX4_EN_TX_COAL_PKTS 5
118#define MLX4_EN_TX_COAL_TIME 0x80
119
120#define MLX4_EN_RX_RATE_LOW 400000
121#define MLX4_EN_RX_COAL_TIME_LOW 0
122#define MLX4_EN_RX_RATE_HIGH 450000
123#define MLX4_EN_RX_COAL_TIME_HIGH 128
124#define MLX4_EN_RX_SIZE_THRESH 1024
125#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
126#define MLX4_EN_SAMPLE_INTERVAL 0
127
128#define MLX4_EN_AUTO_CONF 0xffff
129
130#define MLX4_EN_DEF_RX_PAUSE 1
131#define MLX4_EN_DEF_TX_PAUSE 1
132
133/* Interval between successive polls in the Tx routine when polling is used
134 instead of interrupts (in per-core Tx rings) - should be power of 2 */
135#define MLX4_EN_TX_POLL_MODER 16
136#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
137
138#define ETH_LLC_SNAP_SIZE 8
139
140#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
141#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
142
143#define MLX4_EN_MIN_MTU 46
144#define ETH_BCAST 0xffffffffffffULL
145
146#ifdef MLX4_EN_PERF_STAT
147/* Number of samples to 'average' */
148#define AVG_SIZE 128
149#define AVG_FACTOR 1024
150#define NUM_PERF_STATS NUM_PERF_COUNTERS
151
152#define INC_PERF_COUNTER(cnt) (++(cnt))
153#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
154#define AVG_PERF_COUNTER(cnt, sample) \
155 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
156#define GET_PERF_COUNTER(cnt) (cnt)
157#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
158
159#else
160
161#define NUM_PERF_STATS 0
162#define INC_PERF_COUNTER(cnt) do {} while (0)
163#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
164#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
165#define GET_PERF_COUNTER(cnt) (0)
166#define GET_AVG_PERF_COUNTER(cnt) (0)
167#endif /* MLX4_EN_PERF_STAT */
168
169/*
170 * Configurables
171 */
172
173enum cq_type {
174 RX = 0,
175 TX = 1,
176};
177
178
179/*
180 * Useful macros
181 */
182#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
183#define XNOR(x, y) (!(x) == !(y))
184#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
185
186
187struct mlx4_en_tx_info {
188 struct sk_buff *skb;
189 u32 nr_txbb;
190 u8 linear;
191 u8 data_offset;
192 u8 inl;
193};
194
195
196#define MLX4_EN_BIT_DESC_OWN 0x80000000
197#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
198#define MLX4_EN_MEMTYPE_PAD 0x100
199#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
200
201
202struct mlx4_en_tx_desc {
203 struct mlx4_wqe_ctrl_seg ctrl;
204 union {
205 struct mlx4_wqe_data_seg data; /* at least one data segment */
206 struct mlx4_wqe_lso_seg lso;
207 struct mlx4_wqe_inline_seg inl;
208 };
209};
210
211#define MLX4_EN_USE_SRQ 0x01000000
212
213struct mlx4_en_rx_alloc {
214 struct page *page;
215 u16 offset;
216};
217
218struct mlx4_en_tx_ring {
219 struct mlx4_hwq_resources wqres;
220 u32 size ; /* number of TXBBs */
221 u32 size_mask;
222 u16 stride;
223 u16 cqn; /* index of port CQ associated with this ring */
224 u32 prod;
225 u32 cons;
226 u32 buf_size;
227 u32 doorbell_qpn;
228 void *buf;
229 u16 poll_cnt;
230 int blocked;
231 struct mlx4_en_tx_info *tx_info;
232 u8 *bounce_buf;
233 u32 last_nr_txbb;
234 struct mlx4_qp qp;
235 struct mlx4_qp_context context;
236 int qpn;
237 enum mlx4_qp_state qp_state;
238 struct mlx4_srq dummy;
239 unsigned long bytes;
240 unsigned long packets;
241 spinlock_t comp_lock;
242};
243
244struct mlx4_en_rx_desc {
245 /* actual number of entries depends on rx ring stride */
246 struct mlx4_wqe_data_seg data[0];
247};
248
249struct mlx4_en_rx_ring {
250 struct mlx4_hwq_resources wqres;
251 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
252 struct net_lro_mgr lro;
253 u32 size ; /* number of Rx descs*/
254 u32 actual_size;
255 u32 size_mask;
256 u16 stride;
257 u16 log_stride;
258 u16 cqn; /* index of port CQ associated with this ring */
259 u32 prod;
260 u32 cons;
261 u32 buf_size;
262 void *buf;
263 void *rx_info;
264 unsigned long bytes;
265 unsigned long packets;
266};
267
268
269static inline int mlx4_en_can_lro(__be16 status)
270{
271 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
272 MLX4_CQE_STATUS_IPV4F |
273 MLX4_CQE_STATUS_IPV6 |
274 MLX4_CQE_STATUS_IPV4OPT |
275 MLX4_CQE_STATUS_TCP |
276 MLX4_CQE_STATUS_UDP |
277 MLX4_CQE_STATUS_IPOK)) ==
278 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
279 MLX4_CQE_STATUS_IPOK |
280 MLX4_CQE_STATUS_TCP);
281}
282
283struct mlx4_en_cq {
284 struct mlx4_cq mcq;
285 struct mlx4_hwq_resources wqres;
286 int ring;
287 spinlock_t lock;
288 struct net_device *dev;
289 struct napi_struct napi;
290 /* Per-core Tx cq processing support */
291 struct timer_list timer;
292 int size;
293 int buf_size;
294 unsigned vector;
295 enum cq_type is_tx;
296 u16 moder_time;
297 u16 moder_cnt;
298 struct mlx4_cqe *buf;
299#define MLX4_EN_OPCODE_ERROR 0x1e
300};
301
302struct mlx4_en_port_profile {
303 u32 flags;
304 u32 tx_ring_num;
305 u32 rx_ring_num;
306 u32 tx_ring_size;
307 u32 rx_ring_size;
308 u8 rx_pause;
309 u8 rx_ppp;
310 u8 tx_pause;
311 u8 tx_ppp;
312};
313
314struct mlx4_en_profile {
315 int rss_xor;
316 int num_lro;
317 u8 rss_mask;
318 u32 active_ports;
319 u32 small_pkt_int;
320 u8 no_reset;
321 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
322};
323
324struct mlx4_en_dev {
325 struct mlx4_dev *dev;
326 struct pci_dev *pdev;
327 struct mutex state_lock;
328 struct net_device *pndev[MLX4_MAX_PORTS + 1];
329 u32 port_cnt;
330 bool device_up;
331 struct mlx4_en_profile profile;
332 u32 LSO_support;
333 struct workqueue_struct *workqueue;
334 struct device *dma_device;
335 void __iomem *uar_map;
336 struct mlx4_uar priv_uar;
337 struct mlx4_mr mr;
338 u32 priv_pdn;
339 spinlock_t uar_lock;
340};
341
342
343struct mlx4_en_rss_map {
344 int base_qpn;
345 struct mlx4_qp qps[MAX_RX_RINGS];
346 enum mlx4_qp_state state[MAX_RX_RINGS];
347 struct mlx4_qp indir_qp;
348 enum mlx4_qp_state indir_state;
349};
350
351struct mlx4_en_rss_context {
352 __be32 base_qpn;
353 __be32 default_qpn;
354 u16 reserved;
355 u8 hash_fn;
356 u8 flags;
357 __be32 rss_key[10];
358};
359
360struct mlx4_en_pkt_stats {
361 unsigned long broadcast;
362 unsigned long rx_prio[8];
363 unsigned long tx_prio[8];
364#define NUM_PKT_STATS 17
365};
366
367struct mlx4_en_port_stats {
368 unsigned long lro_aggregated;
369 unsigned long lro_flushed;
370 unsigned long lro_no_desc;
371 unsigned long tso_packets;
372 unsigned long queue_stopped;
373 unsigned long wake_queue;
374 unsigned long tx_timeout;
375 unsigned long rx_alloc_failed;
376 unsigned long rx_chksum_good;
377 unsigned long rx_chksum_none;
378 unsigned long tx_chksum_offload;
379#define NUM_PORT_STATS 11
380};
381
382struct mlx4_en_perf_stats {
383 u32 tx_poll;
384 u64 tx_pktsz_avg;
385 u32 inflight_avg;
386 u16 tx_coal_avg;
387 u16 rx_coal_avg;
388 u32 napi_quota;
389#define NUM_PERF_COUNTERS 6
390};
391
392struct mlx4_en_frag_info {
393 u16 frag_size;
394 u16 frag_prefix_size;
395 u16 frag_stride;
396 u16 frag_align;
397 u16 last_offset;
398
399};
400
401struct mlx4_en_priv {
402 struct mlx4_en_dev *mdev;
403 struct mlx4_en_port_profile *prof;
404 struct net_device *dev;
405 struct vlan_group *vlgrp;
406 struct net_device_stats stats;
407 struct net_device_stats ret_stats;
408 spinlock_t stats_lock;
409
410 unsigned long last_moder_packets;
411 unsigned long last_moder_tx_packets;
412 unsigned long last_moder_bytes;
413 unsigned long last_moder_jiffies;
414 int last_moder_time;
415 u16 rx_usecs;
416 u16 rx_frames;
417 u16 tx_usecs;
418 u16 tx_frames;
419 u32 pkt_rate_low;
420 u16 rx_usecs_low;
421 u32 pkt_rate_high;
422 u16 rx_usecs_high;
423 u16 sample_interval;
424 u16 adaptive_rx_coal;
425 u32 msg_enable;
426
427 struct mlx4_hwq_resources res;
428 int link_state;
429 int last_link_state;
430 bool port_up;
431 int port;
432 int registered;
433 int allocated;
434 int stride;
435 int rx_csum;
436 u64 mac;
437 int mac_index;
438 unsigned max_mtu;
439 int base_qpn;
440
441 struct mlx4_en_rss_map rss_map;
442 u32 flags;
443#define MLX4_EN_FLAG_PROMISC 0x1
444 u32 tx_ring_num;
445 u32 rx_ring_num;
446 u32 rx_skb_size;
447 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
448 u16 num_frags;
449 u16 log_rx_info;
450
451 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
452 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
453 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
454 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
455 struct work_struct mcast_task;
456 struct work_struct mac_task;
457 struct work_struct watchdog_task;
458 struct work_struct linkstate_task;
459 struct delayed_work stats_task;
460 struct mlx4_en_perf_stats pstats;
461 struct mlx4_en_pkt_stats pkstats;
462 struct mlx4_en_port_stats port_stats;
463 char *mc_addrs;
464 int mc_addrs_cnt;
465 struct mlx4_en_stat_out_mbox hw_stats;
466};
467
468
469void mlx4_en_destroy_netdev(struct net_device *dev);
470int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
471 struct mlx4_en_port_profile *prof);
472
473int mlx4_en_start_port(struct net_device *dev);
474void mlx4_en_stop_port(struct net_device *dev);
475
476void mlx4_en_free_resources(struct mlx4_en_priv *priv);
477int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
478
479int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
480 int entries, int ring, enum cq_type mode);
481void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
482int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
483void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
484int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
485int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
486
487void mlx4_en_poll_tx_cq(unsigned long data);
488void mlx4_en_tx_irq(struct mlx4_cq *mcq);
489u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
490netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
491
492int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
493 u32 size, u16 stride);
494void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
495int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
496 struct mlx4_en_tx_ring *ring,
497 int cq);
498void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
499 struct mlx4_en_tx_ring *ring);
500
501int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
502 struct mlx4_en_rx_ring *ring,
503 u32 size, u16 stride);
504void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
505 struct mlx4_en_rx_ring *ring);
506int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
507void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
508 struct mlx4_en_rx_ring *ring);
509int mlx4_en_process_rx_cq(struct net_device *dev,
510 struct mlx4_en_cq *cq,
511 int budget);
512int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
513void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
514 int is_tx, int rss, int qpn, int cqn,
515 struct mlx4_qp_context *context);
516void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
517int mlx4_en_map_buffer(struct mlx4_buf *buf);
518void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
519
520void mlx4_en_calc_rx_buf(struct net_device *dev);
521int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
522void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
523int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
524void mlx4_en_rx_irq(struct mlx4_cq *mcq);
525
526int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
527int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
528int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
529 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
530int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
531 u8 promisc);
532
533int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
534
535/*
536 * Globals
537 */
538extern const struct ethtool_ops mlx4_en_ethtool_ops;
539
540
541
542/*
543 * printk / logging functions
544 */
545
546int en_print(const char *level, const struct mlx4_en_priv *priv,
547 const char *format, ...) __attribute__ ((format (printf, 3, 4)));
548
549#define en_dbg(mlevel, priv, format, arg...) \
550do { \
551 if (NETIF_MSG_##mlevel & priv->msg_enable) \
552 en_print(KERN_DEBUG, priv, format, ##arg); \
553} while (0)
554#define en_warn(priv, format, arg...) \
555 en_print(KERN_WARNING, priv, format, ##arg)
556#define en_err(priv, format, arg...) \
557 en_print(KERN_ERR, priv, format, ##arg)
558
559#define mlx4_err(mdev, format, arg...) \
560 pr_err("%s %s: " format, DRV_NAME, \
561 dev_name(&mdev->pdev->dev), ##arg)
562#define mlx4_info(mdev, format, arg...) \
563 pr_info("%s %s: " format, DRV_NAME, \
564 dev_name(&mdev->pdev->dev), ##arg)
565#define mlx4_warn(mdev, format, arg...) \
566 pr_warning("%s %s: " format, DRV_NAME, \
567 dev_name(&mdev->pdev->dev), ##arg)
568
569#endif