tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11#ifndef __SDHCI_H
12#define __SDHCI_H
13
14#include <linux/scatterlist.h>
15#include <linux/compiler.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19/*
20 * Controller registers
21 */
22
23#define SDHCI_DMA_ADDRESS 0x00
24
25#define SDHCI_BLOCK_SIZE 0x04
26#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
27
28#define SDHCI_BLOCK_COUNT 0x06
29
30#define SDHCI_ARGUMENT 0x08
31
32#define SDHCI_TRANSFER_MODE 0x0C
33#define SDHCI_TRNS_DMA 0x01
34#define SDHCI_TRNS_BLK_CNT_EN 0x02
35#define SDHCI_TRNS_ACMD12 0x04
36#define SDHCI_TRNS_READ 0x10
37#define SDHCI_TRNS_MULTI 0x20
38
39#define SDHCI_COMMAND 0x0E
40#define SDHCI_CMD_RESP_MASK 0x03
41#define SDHCI_CMD_CRC 0x08
42#define SDHCI_CMD_INDEX 0x10
43#define SDHCI_CMD_DATA 0x20
44
45#define SDHCI_CMD_RESP_NONE 0x00
46#define SDHCI_CMD_RESP_LONG 0x01
47#define SDHCI_CMD_RESP_SHORT 0x02
48#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
49
50#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
51
52#define SDHCI_RESPONSE 0x10
53
54#define SDHCI_BUFFER 0x20
55
56#define SDHCI_PRESENT_STATE 0x24
57#define SDHCI_CMD_INHIBIT 0x00000001
58#define SDHCI_DATA_INHIBIT 0x00000002
59#define SDHCI_DOING_WRITE 0x00000100
60#define SDHCI_DOING_READ 0x00000200
61#define SDHCI_SPACE_AVAILABLE 0x00000400
62#define SDHCI_DATA_AVAILABLE 0x00000800
63#define SDHCI_CARD_PRESENT 0x00010000
64#define SDHCI_WRITE_PROTECT 0x00080000
65
66#define SDHCI_HOST_CONTROL 0x28
67#define SDHCI_CTRL_LED 0x01
68#define SDHCI_CTRL_4BITBUS 0x02
69#define SDHCI_CTRL_HISPD 0x04
70#define SDHCI_CTRL_DMA_MASK 0x18
71#define SDHCI_CTRL_SDMA 0x00
72#define SDHCI_CTRL_ADMA1 0x08
73#define SDHCI_CTRL_ADMA32 0x10
74#define SDHCI_CTRL_ADMA64 0x18
75#define SDHCI_CTRL_8BITBUS 0x20
76
77#define SDHCI_POWER_CONTROL 0x29
78#define SDHCI_POWER_ON 0x01
79#define SDHCI_POWER_180 0x0A
80#define SDHCI_POWER_300 0x0C
81#define SDHCI_POWER_330 0x0E
82
83#define SDHCI_BLOCK_GAP_CONTROL 0x2A
84
85#define SDHCI_WAKE_UP_CONTROL 0x2B
86
87#define SDHCI_CLOCK_CONTROL 0x2C
88#define SDHCI_DIVIDER_SHIFT 8
89#define SDHCI_CLOCK_CARD_EN 0x0004
90#define SDHCI_CLOCK_INT_STABLE 0x0002
91#define SDHCI_CLOCK_INT_EN 0x0001
92
93#define SDHCI_TIMEOUT_CONTROL 0x2E
94
95#define SDHCI_SOFTWARE_RESET 0x2F
96#define SDHCI_RESET_ALL 0x01
97#define SDHCI_RESET_CMD 0x02
98#define SDHCI_RESET_DATA 0x04
99
100#define SDHCI_INT_STATUS 0x30
101#define SDHCI_INT_ENABLE 0x34
102#define SDHCI_SIGNAL_ENABLE 0x38
103#define SDHCI_INT_RESPONSE 0x00000001
104#define SDHCI_INT_DATA_END 0x00000002
105#define SDHCI_INT_DMA_END 0x00000008
106#define SDHCI_INT_SPACE_AVAIL 0x00000010
107#define SDHCI_INT_DATA_AVAIL 0x00000020
108#define SDHCI_INT_CARD_INSERT 0x00000040
109#define SDHCI_INT_CARD_REMOVE 0x00000080
110#define SDHCI_INT_CARD_INT 0x00000100
111#define SDHCI_INT_ERROR 0x00008000
112#define SDHCI_INT_TIMEOUT 0x00010000
113#define SDHCI_INT_CRC 0x00020000
114#define SDHCI_INT_END_BIT 0x00040000
115#define SDHCI_INT_INDEX 0x00080000
116#define SDHCI_INT_DATA_TIMEOUT 0x00100000
117#define SDHCI_INT_DATA_CRC 0x00200000
118#define SDHCI_INT_DATA_END_BIT 0x00400000
119#define SDHCI_INT_BUS_POWER 0x00800000
120#define SDHCI_INT_ACMD12ERR 0x01000000
121#define SDHCI_INT_ADMA_ERROR 0x02000000
122
123#define SDHCI_INT_NORMAL_MASK 0x00007FFF
124#define SDHCI_INT_ERROR_MASK 0xFFFF8000
125
126#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
127 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
128#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
129 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
130 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
131 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
132#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
133
134#define SDHCI_ACMD12_ERR 0x3C
135
136/* 3E-3F reserved */
137
138#define SDHCI_CAPABILITIES 0x40
139#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
140#define SDHCI_TIMEOUT_CLK_SHIFT 0
141#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
142#define SDHCI_CLOCK_BASE_MASK 0x00003F00
143#define SDHCI_CLOCK_BASE_SHIFT 8
144#define SDHCI_MAX_BLOCK_MASK 0x00030000
145#define SDHCI_MAX_BLOCK_SHIFT 16
146#define SDHCI_CAN_DO_ADMA2 0x00080000
147#define SDHCI_CAN_DO_ADMA1 0x00100000
148#define SDHCI_CAN_DO_HISPD 0x00200000
149#define SDHCI_CAN_DO_SDMA 0x00400000
150#define SDHCI_CAN_VDD_330 0x01000000
151#define SDHCI_CAN_VDD_300 0x02000000
152#define SDHCI_CAN_VDD_180 0x04000000
153#define SDHCI_CAN_64BIT 0x10000000
154
155/* 44-47 reserved for more caps */
156
157#define SDHCI_MAX_CURRENT 0x48
158
159/* 4C-4F reserved for more max current */
160
161#define SDHCI_SET_ACMD12_ERROR 0x50
162#define SDHCI_SET_INT_ERROR 0x52
163
164#define SDHCI_ADMA_ERROR 0x54
165
166/* 55-57 reserved */
167
168#define SDHCI_ADMA_ADDRESS 0x58
169
170/* 60-FB reserved */
171
172#define SDHCI_SLOT_INT_STATUS 0xFC
173
174#define SDHCI_HOST_VERSION 0xFE
175#define SDHCI_VENDOR_VER_MASK 0xFF00
176#define SDHCI_VENDOR_VER_SHIFT 8
177#define SDHCI_SPEC_VER_MASK 0x00FF
178#define SDHCI_SPEC_VER_SHIFT 0
179#define SDHCI_SPEC_100 0
180#define SDHCI_SPEC_200 1
181
182struct sdhci_ops;
183
184struct sdhci_host {
185 /* Data set by hardware interface driver */
186 const char *hw_name; /* Hardware bus name */
187
188 unsigned int quirks; /* Deviations from spec. */
189
190/* Controller doesn't honor resets unless we touch the clock register */
191#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
192/* Controller has bad caps bits, but really supports DMA */
193#define SDHCI_QUIRK_FORCE_DMA (1<<1)
194/* Controller doesn't like to be reset when there is no card inserted. */
195#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
196/* Controller doesn't like clearing the power reg before a change */
197#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
198/* Controller has flaky internal state so reset it on each ios change */
199#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
200/* Controller has an unusable DMA engine */
201#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
202/* Controller has an unusable ADMA engine */
203#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
204/* Controller can only DMA from 32-bit aligned addresses */
205#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
206/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
207#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
208/* Controller can only ADMA chunks that are a multiple of 32 bits */
209#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
210/* Controller needs to be reset after each request to stay stable */
211#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
212/* Controller needs voltage and power writes to happen separately */
213#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
214/* Controller provides an incorrect timeout value for transfers */
215#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
216/* Controller has an issue with buffer bits for small transfers */
217#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
218/* Controller does not provide transfer-complete interrupt when not busy */
219#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
220/* Controller has unreliable card detection */
221#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
222/* Controller reports inverted write-protect state */
223#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
224/* Controller has nonstandard clock management */
225#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
226/* Controller does not like fast PIO transfers */
227#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
228/* Controller losing signal/interrupt enable states after reset */
229#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
230/* Controller has to be forced to use block size of 2048 bytes */
231#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
232/* Controller cannot do multi-block transfers */
233#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
234/* Controller can only handle 1-bit data transfers */
235#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
236/* Controller needs 10ms delay between applying power and clock */
237#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
238/* Controller uses SDCLK instead of TMCLK for data timeouts */
239#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
240/* Controller reports wrong base clock capability */
241#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
242/* Controller cannot support End Attribute in NOP ADMA descriptor */
243#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
244/* Controller is missing device caps. Use caps provided by host */
245#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
246/* Controller uses Auto CMD12 command to stop the transfer */
247#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
248/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
249#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
250
251 int irq; /* Device IRQ */
252 void __iomem * ioaddr; /* Mapped address */
253
254 const struct sdhci_ops *ops; /* Low level hw interface */
255
256 struct regulator *vmmc; /* Power regulator */
257
258 /* Internal data */
259 struct mmc_host *mmc; /* MMC structure */
260 u64 dma_mask; /* custom DMA mask */
261
262#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
263 struct led_classdev led; /* LED control */
264 char led_name[32];
265#endif
266
267 spinlock_t lock; /* Mutex */
268
269 int flags; /* Host attributes */
270#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
271#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
272#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
273#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
274
275 unsigned int version; /* SDHCI spec. version */
276
277 unsigned int max_clk; /* Max possible freq (MHz) */
278 unsigned int timeout_clk; /* Timeout freq (KHz) */
279
280 unsigned int clock; /* Current clock (MHz) */
281 u8 pwr; /* Current voltage */
282
283 struct mmc_request *mrq; /* Current request */
284 struct mmc_command *cmd; /* Current command */
285 struct mmc_data *data; /* Current data request */
286 unsigned int data_early:1; /* Data finished before cmd */
287
288 struct sg_mapping_iter sg_miter; /* SG state for PIO */
289 unsigned int blocks; /* remaining PIO blocks */
290
291 int sg_count; /* Mapped sg entries */
292
293 u8 *adma_desc; /* ADMA descriptor table */
294 u8 *align_buffer; /* Bounce buffer */
295
296 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
297 dma_addr_t align_addr; /* Mapped bounce buffer */
298
299 struct tasklet_struct card_tasklet; /* Tasklet structures */
300 struct tasklet_struct finish_tasklet;
301
302 struct timer_list timer; /* Timer for timeouts */
303
304 unsigned int caps; /* Alternative capabilities */
305
306 unsigned long private[0] ____cacheline_aligned;
307};
308
309
310struct sdhci_ops {
311#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
312 u32 (*read_l)(struct sdhci_host *host, int reg);
313 u16 (*read_w)(struct sdhci_host *host, int reg);
314 u8 (*read_b)(struct sdhci_host *host, int reg);
315 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
316 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
317 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
318#endif
319
320 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
321
322 int (*enable_dma)(struct sdhci_host *host);
323 unsigned int (*get_max_clock)(struct sdhci_host *host);
324 unsigned int (*get_min_clock)(struct sdhci_host *host);
325 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
326};
327
328#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
329
330static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
331{
332 if (unlikely(host->ops->write_l))
333 host->ops->write_l(host, val, reg);
334 else
335 writel(val, host->ioaddr + reg);
336}
337
338static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
339{
340 if (unlikely(host->ops->write_w))
341 host->ops->write_w(host, val, reg);
342 else
343 writew(val, host->ioaddr + reg);
344}
345
346static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
347{
348 if (unlikely(host->ops->write_b))
349 host->ops->write_b(host, val, reg);
350 else
351 writeb(val, host->ioaddr + reg);
352}
353
354static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
355{
356 if (unlikely(host->ops->read_l))
357 return host->ops->read_l(host, reg);
358 else
359 return readl(host->ioaddr + reg);
360}
361
362static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
363{
364 if (unlikely(host->ops->read_w))
365 return host->ops->read_w(host, reg);
366 else
367 return readw(host->ioaddr + reg);
368}
369
370static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
371{
372 if (unlikely(host->ops->read_b))
373 return host->ops->read_b(host, reg);
374 else
375 return readb(host->ioaddr + reg);
376}
377
378#else
379
380static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
381{
382 writel(val, host->ioaddr + reg);
383}
384
385static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
386{
387 writew(val, host->ioaddr + reg);
388}
389
390static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
391{
392 writeb(val, host->ioaddr + reg);
393}
394
395static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
396{
397 return readl(host->ioaddr + reg);
398}
399
400static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
401{
402 return readw(host->ioaddr + reg);
403}
404
405static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
406{
407 return readb(host->ioaddr + reg);
408}
409
410#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
411
412extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
413 size_t priv_size);
414extern void sdhci_free_host(struct sdhci_host *host);
415
416static inline void *sdhci_priv(struct sdhci_host *host)
417{
418 return (void *)host->private;
419}
420
421extern void sdhci_card_detect(struct sdhci_host *host);
422extern int sdhci_add_host(struct sdhci_host *host);
423extern void sdhci_remove_host(struct sdhci_host *host, int dead);
424
425#ifdef CONFIG_PM
426extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
427extern int sdhci_resume_host(struct sdhci_host *host);
428#endif
429
430#endif /* __SDHCI_H */