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1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
15#define PPC_FEATURE_NO_TB 0x00100000
16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
20#define PPC_FEATURE_BOOKE 0x00008000
21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
23#define PPC_FEATURE_ARCH_2_05 0x00001000
24#define PPC_FEATURE_PA6T 0x00000800
25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
27#define PPC_FEATURE_ARCH_2_06 0x00000100
28#define PPC_FEATURE_HAS_VSX 0x00000080
29
30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
36#ifdef __KERNEL__
37
38#include <asm/asm-compat.h>
39#include <asm/feature-fixups.h>
40
41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
47
48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
49typedef void (*cpu_restore_t)(void);
50
51enum powerpc_oprofile_type {
52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
56 PPC_OPROFILE_FSL_EMB = 4,
57 PPC_OPROFILE_CELL = 5,
58 PPC_OPROFILE_PA6T = 6,
59};
60
61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
65 PPC_PMC_G4 = 3,
66};
67
68struct pt_regs;
69
70extern int machine_check_generic(struct pt_regs *regs);
71extern int machine_check_4xx(struct pt_regs *regs);
72extern int machine_check_440A(struct pt_regs *regs);
73extern int machine_check_e500mc(struct pt_regs *regs);
74extern int machine_check_e500(struct pt_regs *regs);
75extern int machine_check_e200(struct pt_regs *regs);
76extern int machine_check_47x(struct pt_regs *regs);
77
78/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
79struct cpu_spec {
80 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
81 unsigned int pvr_mask;
82 unsigned int pvr_value;
83
84 char *cpu_name;
85 unsigned long cpu_features; /* Kernel features */
86 unsigned int cpu_user_features; /* Userland features */
87 unsigned int mmu_features; /* MMU features */
88
89 /* cache line sizes */
90 unsigned int icache_bsize;
91 unsigned int dcache_bsize;
92
93 /* number of performance monitor counters */
94 unsigned int num_pmcs;
95 enum powerpc_pmc_type pmc_type;
96
97 /* this is called to initialize various CPU bits like L1 cache,
98 * BHT, SPD, etc... from head.S before branching to identify_machine
99 */
100 cpu_setup_t cpu_setup;
101 /* Used to restore cpu setup on secondary processors and at resume */
102 cpu_restore_t cpu_restore;
103
104 /* Used by oprofile userspace to select the right counters */
105 char *oprofile_cpu_type;
106
107 /* Processor specific oprofile operations */
108 enum powerpc_oprofile_type oprofile_type;
109
110 /* Bit locations inside the mmcra change */
111 unsigned long oprofile_mmcra_sihv;
112 unsigned long oprofile_mmcra_sipr;
113
114 /* Bits to clear during an oprofile exception */
115 unsigned long oprofile_mmcra_clear;
116
117 /* Name of processor class, for the ELF AT_PLATFORM entry */
118 char *platform;
119
120 /* Processor specific machine check handling. Return negative
121 * if the error is fatal, 1 if it was fully recovered and 0 to
122 * pass up (not CPU originated) */
123 int (*machine_check)(struct pt_regs *regs);
124};
125
126extern struct cpu_spec *cur_cpu_spec;
127
128extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
129
130extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
131extern void do_feature_fixups(unsigned long value, void *fixup_start,
132 void *fixup_end);
133
134extern const char *powerpc_base_platform;
135
136#endif /* __ASSEMBLY__ */
137
138/* CPU kernel features */
139
140/* Retain the 32b definitions all use bottom half of word */
141#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
142#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
143#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
144#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
145#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
146#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
147#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
148#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
149#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
150#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
151#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
152#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
153#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
154#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
155#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
156#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
157#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
158#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
159#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
160#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
161#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
162#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
163#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
164#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
165#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
166#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
167#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
168#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
169
170/*
171 * Add the 64-bit processor unique features in the top half of the word;
172 * on 32-bit, make the names available but defined to be 0.
173 */
174#ifdef __powerpc64__
175#define LONG_ASM_CONST(x) ASM_CONST(x)
176#else
177#define LONG_ASM_CONST(x) 0
178#endif
179
180#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
181#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
182#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
183#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
184#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
185#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
186#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
187#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
188#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
189#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
190#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
191#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
192#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
193#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
194#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
195#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
196#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
197#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
198#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
199#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
200#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
201
202#ifndef __ASSEMBLY__
203
204#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
205 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
206 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
207
208/* We only set the altivec features if the kernel was compiled with altivec
209 * support
210 */
211#ifdef CONFIG_ALTIVEC
212#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
213#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
214#else
215#define CPU_FTR_ALTIVEC_COMP 0
216#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
217#endif
218
219/* We only set the VSX features if the kernel was compiled with VSX
220 * support
221 */
222#ifdef CONFIG_VSX
223#define CPU_FTR_VSX_COMP CPU_FTR_VSX
224#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
225#else
226#define CPU_FTR_VSX_COMP 0
227#define PPC_FEATURE_HAS_VSX_COMP 0
228#endif
229
230/* We only set the spe features if the kernel was compiled with spe
231 * support
232 */
233#ifdef CONFIG_SPE
234#define CPU_FTR_SPE_COMP CPU_FTR_SPE
235#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
236#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
237#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
238#else
239#define CPU_FTR_SPE_COMP 0
240#define PPC_FEATURE_HAS_SPE_COMP 0
241#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
242#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
243#endif
244
245/* We need to mark all pages as being coherent if we're SMP or we have a
246 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
247 * require it for PCI "streaming/prefetch" to work properly.
248 * This is also required by 52xx family.
249 */
250#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
251 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
252 || defined(CONFIG_PPC_MPC52xx)
253#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
254#else
255#define CPU_FTR_COMMON 0
256#endif
257
258/* The powersave features NAP & DOZE seems to confuse BDI when
259 debugging. So if a BDI is used, disable theses
260 */
261#ifndef CONFIG_BDI_SWITCH
262#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
263#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
264#else
265#define CPU_FTR_MAYBE_CAN_DOZE 0
266#define CPU_FTR_MAYBE_CAN_NAP 0
267#endif
268
269#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
270 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
271 !defined(CONFIG_BOOKE))
272
273#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
274 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
275#define CPU_FTRS_603 (CPU_FTR_COMMON | \
276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
277 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
278#define CPU_FTRS_604 (CPU_FTR_COMMON | \
279 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
280#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
281 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
283#define CPU_FTRS_740 (CPU_FTR_COMMON | \
284 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
285 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
286 CPU_FTR_PPC_LE)
287#define CPU_FTRS_750 (CPU_FTR_COMMON | \
288 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
289 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
290 CPU_FTR_PPC_LE)
291#define CPU_FTRS_750CL (CPU_FTRS_750)
292#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
293#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
294#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
295#define CPU_FTRS_750GX (CPU_FTRS_750FX)
296#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
297 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
298 CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
300#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
301 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
302 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
304#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
305 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
306 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
307 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
308#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
309 CPU_FTR_USE_TB | \
310 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
311 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
312 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
313 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
314#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
315 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
316 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
317 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
318 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
319#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
320 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
321 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
322 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
323#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
324 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
327 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
329#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
330 CPU_FTR_USE_TB | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
333 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
334#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
335 CPU_FTR_USE_TB | \
336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
338 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
339 CPU_FTR_NEED_PAIRED_STWCX)
340#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
341 CPU_FTR_USE_TB | \
342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
343 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
344 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
345#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
346 CPU_FTR_USE_TB | \
347 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
348 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
349 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
350#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
351 CPU_FTR_USE_TB | \
352 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
353 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
354 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
355#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
356 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
357#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
358 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
359#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
360 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
361 CPU_FTR_COMMON)
362#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
363 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
364 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
365#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
366#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
367#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
368#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
369#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
370 CPU_FTR_INDEXED_DCR)
371#define CPU_FTRS_47X (CPU_FTRS_440x6)
372#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
373 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
374 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
375#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
376 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
377 CPU_FTR_NOEXECUTE)
378#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
379 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
380 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
381#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
382 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
383 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
384 CPU_FTR_DBELL)
385#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
386
387/* 64-bit CPUs */
388#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
389 CPU_FTR_IABR | CPU_FTR_PPC_LE)
390#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
391 CPU_FTR_IABR | \
392 CPU_FTR_MMCRA | CPU_FTR_CTRL)
393#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
394 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
395 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
396#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
397 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
398 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
399 CPU_FTR_CP_USE_DCBTZ)
400#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
401 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
402 CPU_FTR_MMCRA | CPU_FTR_SMT | \
403 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
404 CPU_FTR_PURR)
405#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
406 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
407 CPU_FTR_MMCRA | CPU_FTR_SMT | \
408 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
409 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
410 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)
411#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
412 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
413 CPU_FTR_MMCRA | CPU_FTR_SMT | \
414 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
415 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
416 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT)
417#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
419 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
420 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
421 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
422 CPU_FTR_UNALIGNED_LD_STD)
423#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
424 CPU_FTR_PPCAS_ARCH_V2 | \
425 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
426 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
427#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
428
429#ifdef __powerpc64__
430#define CPU_FTRS_POSSIBLE \
431 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
432 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
433 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
434 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
435#else
436enum {
437 CPU_FTRS_POSSIBLE =
438#if CLASSIC_PPC
439 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
440 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
441 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
442 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
443 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
444 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
445 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
446 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
447 CPU_FTRS_CLASSIC32 |
448#else
449 CPU_FTRS_GENERIC_32 |
450#endif
451#ifdef CONFIG_8xx
452 CPU_FTRS_8XX |
453#endif
454#ifdef CONFIG_40x
455 CPU_FTRS_40X |
456#endif
457#ifdef CONFIG_44x
458 CPU_FTRS_44X | CPU_FTRS_440x6 |
459#endif
460#ifdef CONFIG_PPC_47x
461 CPU_FTRS_47X |
462#endif
463#ifdef CONFIG_E200
464 CPU_FTRS_E200 |
465#endif
466#ifdef CONFIG_E500
467 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
468#endif
469 0,
470};
471#endif /* __powerpc64__ */
472
473#ifdef __powerpc64__
474#define CPU_FTRS_ALWAYS \
475 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
476 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
477 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
478#else
479enum {
480 CPU_FTRS_ALWAYS =
481#if CLASSIC_PPC
482 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
483 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
484 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
485 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
486 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
487 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
488 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
489 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
490 CPU_FTRS_CLASSIC32 &
491#else
492 CPU_FTRS_GENERIC_32 &
493#endif
494#ifdef CONFIG_8xx
495 CPU_FTRS_8XX &
496#endif
497#ifdef CONFIG_40x
498 CPU_FTRS_40X &
499#endif
500#ifdef CONFIG_44x
501 CPU_FTRS_44X & CPU_FTRS_440x6 &
502#endif
503#ifdef CONFIG_E200
504 CPU_FTRS_E200 &
505#endif
506#ifdef CONFIG_E500
507 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
508#endif
509 CPU_FTRS_POSSIBLE,
510};
511#endif /* __powerpc64__ */
512
513static inline int cpu_has_feature(unsigned long feature)
514{
515 return (CPU_FTRS_ALWAYS & feature) ||
516 (CPU_FTRS_POSSIBLE
517 & cur_cpu_spec->cpu_features
518 & feature);
519}
520
521#ifdef CONFIG_HAVE_HW_BREAKPOINT
522#define HBP_NUM 1
523#endif /* CONFIG_HAVE_HW_BREAKPOINT */
524
525#endif /* !__ASSEMBLY__ */
526
527#endif /* __KERNEL__ */
528#endif /* __ASM_POWERPC_CPUTABLE_H */