tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/crc32.h>
42#include <linux/spinlock.h>
43#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/irq.h>
46#include <linux/uaccess.h>
47#include <linux/phy.h>
48
49#include <asm/processor.h>
50
51#define DRV_NAME "r6040"
52#define DRV_VERSION "0.26"
53#define DRV_RELDATE "30May2010"
54
55/* PHY CHIP Address */
56#define PHY1_ADDR 1 /* For MAC1 */
57#define PHY2_ADDR 3 /* For MAC2 */
58#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61/* Time in jiffies before concluding the transmitter is hung. */
62#define TX_TIMEOUT (6000 * HZ / 1000)
63
64/* RDC MAC I/O Size */
65#define R6040_IO_SIZE 256
66
67/* MAX RDC MAC */
68#define MAX_MAC 2
69
70/* MAC registers */
71#define MCR0 0x00 /* Control register 0 */
72#define MCR1 0x04 /* Control register 1 */
73#define MAC_RST 0x0001 /* Reset the MAC */
74#define MBCR 0x08 /* Bus control */
75#define MT_ICR 0x0C /* TX interrupt control */
76#define MR_ICR 0x10 /* RX interrupt control */
77#define MTPR 0x14 /* TX poll command register */
78#define MR_BSR 0x18 /* RX buffer size */
79#define MR_DCR 0x1A /* RX descriptor control */
80#define MLSR 0x1C /* Last status */
81#define MMDIO 0x20 /* MDIO control register */
82#define MDIO_WRITE 0x4000 /* MDIO write */
83#define MDIO_READ 0x2000 /* MDIO read */
84#define MMRD 0x24 /* MDIO read data register */
85#define MMWD 0x28 /* MDIO write data register */
86#define MTD_SA0 0x2C /* TX descriptor start address 0 */
87#define MTD_SA1 0x30 /* TX descriptor start address 1 */
88#define MRD_SA0 0x34 /* RX descriptor start address 0 */
89#define MRD_SA1 0x38 /* RX descriptor start address 1 */
90#define MISR 0x3C /* Status register */
91#define MIER 0x40 /* INT enable register */
92#define MSK_INT 0x0000 /* Mask off interrupts */
93#define RX_FINISH 0x0001 /* RX finished */
94#define RX_NO_DESC 0x0002 /* No RX descriptor available */
95#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96#define RX_EARLY 0x0008 /* RX early */
97#define TX_FINISH 0x0010 /* TX finished */
98#define TX_EARLY 0x0080 /* TX early */
99#define EVENT_OVRFL 0x0100 /* Event counter overflow */
100#define LINK_CHANGED 0x0200 /* PHY link changed */
101#define ME_CISR 0x44 /* Event counter INT status */
102#define ME_CIER 0x48 /* Event counter INT enable */
103#define MR_CNT 0x50 /* Successfully received packet counter */
104#define ME_CNT0 0x52 /* Event counter 0 */
105#define ME_CNT1 0x54 /* Event counter 1 */
106#define ME_CNT2 0x56 /* Event counter 2 */
107#define ME_CNT3 0x58 /* Event counter 3 */
108#define MT_CNT 0x5A /* Successfully transmit packet counter */
109#define ME_CNT4 0x5C /* Event counter 4 */
110#define MP_CNT 0x5E /* Pause frame counter register */
111#define MAR0 0x60 /* Hash table 0 */
112#define MAR1 0x62 /* Hash table 1 */
113#define MAR2 0x64 /* Hash table 2 */
114#define MAR3 0x66 /* Hash table 3 */
115#define MID_0L 0x68 /* Multicast address MID0 Low */
116#define MID_0M 0x6A /* Multicast address MID0 Medium */
117#define MID_0H 0x6C /* Multicast address MID0 High */
118#define MID_1L 0x70 /* MID1 Low */
119#define MID_1M 0x72 /* MID1 Medium */
120#define MID_1H 0x74 /* MID1 High */
121#define MID_2L 0x78 /* MID2 Low */
122#define MID_2M 0x7A /* MID2 Medium */
123#define MID_2H 0x7C /* MID2 High */
124#define MID_3L 0x80 /* MID3 Low */
125#define MID_3M 0x82 /* MID3 Medium */
126#define MID_3H 0x84 /* MID3 High */
127#define PHY_CC 0x88 /* PHY status change configuration register */
128#define PHY_ST 0x8A /* PHY status register */
129#define MAC_SM 0xAC /* MAC status machine */
130#define MAC_ID 0xBE /* Identifier register */
131
132#define TX_DCNT 0x80 /* TX descriptor count */
133#define RX_DCNT 0x80 /* RX descriptor count */
134#define MAX_BUF_SIZE 0x600
135#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
137#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138#define MCAST_MAX 3 /* Max number multicast addresses to filter */
139
140/* Descriptor status */
141#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142#define DSC_RX_OK 0x4000 /* RX was successful */
143#define DSC_RX_ERR 0x0800 /* RX PHY error */
144#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
155/* PHY settings */
156#define ICPLUS_PHY_ID 0x0243
157
158MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161MODULE_LICENSE("GPL");
162MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
163MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
164
165/* RX and TX interrupts that we handle */
166#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167#define TX_INTS (TX_FINISH)
168#define INT_MASK (RX_INTS | TX_INTS)
169
170struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179} __attribute__((aligned(32)));
180
181struct r6040_private {
182 spinlock_t lock; /* driver lock */
183 struct pci_dev *pdev;
184 struct r6040_descriptor *rx_insert_ptr;
185 struct r6040_descriptor *rx_remove_ptr;
186 struct r6040_descriptor *tx_insert_ptr;
187 struct r6040_descriptor *tx_remove_ptr;
188 struct r6040_descriptor *rx_ring;
189 struct r6040_descriptor *tx_ring;
190 dma_addr_t rx_ring_dma;
191 dma_addr_t tx_ring_dma;
192 u16 tx_free_desc, phy_addr;
193 u16 mcr0, mcr1;
194 struct net_device *dev;
195 struct mii_bus *mii_bus;
196 struct napi_struct napi;
197 void __iomem *base;
198 struct phy_device *phydev;
199 int old_link;
200 int old_duplex;
201};
202
203static char version[] __devinitdata = KERN_INFO DRV_NAME
204 ": RDC R6040 NAPI net driver,"
205 "version "DRV_VERSION " (" DRV_RELDATE ")";
206
207static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
208
209/* Read a word data from PHY Chip */
210static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
211{
212 int limit = 2048;
213 u16 cmd;
214
215 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
216 /* Wait for the read bit to be cleared */
217 while (limit--) {
218 cmd = ioread16(ioaddr + MMDIO);
219 if (!(cmd & MDIO_READ))
220 break;
221 }
222
223 return ioread16(ioaddr + MMRD);
224}
225
226/* Write a word data from PHY Chip */
227static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
228{
229 int limit = 2048;
230 u16 cmd;
231
232 iowrite16(val, ioaddr + MMWD);
233 /* Write the command to the MDIO bus */
234 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
235 /* Wait for the write bit to be cleared */
236 while (limit--) {
237 cmd = ioread16(ioaddr + MMDIO);
238 if (!(cmd & MDIO_WRITE))
239 break;
240 }
241}
242
243static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
244{
245 struct net_device *dev = bus->priv;
246 struct r6040_private *lp = netdev_priv(dev);
247 void __iomem *ioaddr = lp->base;
248
249 return r6040_phy_read(ioaddr, phy_addr, reg);
250}
251
252static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
253 int reg, u16 value)
254{
255 struct net_device *dev = bus->priv;
256 struct r6040_private *lp = netdev_priv(dev);
257 void __iomem *ioaddr = lp->base;
258
259 r6040_phy_write(ioaddr, phy_addr, reg, value);
260
261 return 0;
262}
263
264static int r6040_mdiobus_reset(struct mii_bus *bus)
265{
266 return 0;
267}
268
269static void r6040_free_txbufs(struct net_device *dev)
270{
271 struct r6040_private *lp = netdev_priv(dev);
272 int i;
273
274 for (i = 0; i < TX_DCNT; i++) {
275 if (lp->tx_insert_ptr->skb_ptr) {
276 pci_unmap_single(lp->pdev,
277 le32_to_cpu(lp->tx_insert_ptr->buf),
278 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
279 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
280 lp->tx_insert_ptr->skb_ptr = NULL;
281 }
282 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
283 }
284}
285
286static void r6040_free_rxbufs(struct net_device *dev)
287{
288 struct r6040_private *lp = netdev_priv(dev);
289 int i;
290
291 for (i = 0; i < RX_DCNT; i++) {
292 if (lp->rx_insert_ptr->skb_ptr) {
293 pci_unmap_single(lp->pdev,
294 le32_to_cpu(lp->rx_insert_ptr->buf),
295 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
296 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
297 lp->rx_insert_ptr->skb_ptr = NULL;
298 }
299 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
300 }
301}
302
303static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
304 dma_addr_t desc_dma, int size)
305{
306 struct r6040_descriptor *desc = desc_ring;
307 dma_addr_t mapping = desc_dma;
308
309 while (size-- > 0) {
310 mapping += sizeof(*desc);
311 desc->ndesc = cpu_to_le32(mapping);
312 desc->vndescp = desc + 1;
313 desc++;
314 }
315 desc--;
316 desc->ndesc = cpu_to_le32(desc_dma);
317 desc->vndescp = desc_ring;
318}
319
320static void r6040_init_txbufs(struct net_device *dev)
321{
322 struct r6040_private *lp = netdev_priv(dev);
323
324 lp->tx_free_desc = TX_DCNT;
325
326 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
327 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
328}
329
330static int r6040_alloc_rxbufs(struct net_device *dev)
331{
332 struct r6040_private *lp = netdev_priv(dev);
333 struct r6040_descriptor *desc;
334 struct sk_buff *skb;
335 int rc;
336
337 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
338 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
339
340 /* Allocate skbs for the rx descriptors */
341 desc = lp->rx_ring;
342 do {
343 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
344 if (!skb) {
345 netdev_err(dev, "failed to alloc skb for rx\n");
346 rc = -ENOMEM;
347 goto err_exit;
348 }
349 desc->skb_ptr = skb;
350 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
351 desc->skb_ptr->data,
352 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
353 desc->status = DSC_OWNER_MAC;
354 desc = desc->vndescp;
355 } while (desc != lp->rx_ring);
356
357 return 0;
358
359err_exit:
360 /* Deallocate all previously allocated skbs */
361 r6040_free_rxbufs(dev);
362 return rc;
363}
364
365static void r6040_init_mac_regs(struct net_device *dev)
366{
367 struct r6040_private *lp = netdev_priv(dev);
368 void __iomem *ioaddr = lp->base;
369 int limit = 2048;
370 u16 cmd;
371
372 /* Mask Off Interrupt */
373 iowrite16(MSK_INT, ioaddr + MIER);
374
375 /* Reset RDC MAC */
376 iowrite16(MAC_RST, ioaddr + MCR1);
377 while (limit--) {
378 cmd = ioread16(ioaddr + MCR1);
379 if (cmd & 0x1)
380 break;
381 }
382 /* Reset internal state machine */
383 iowrite16(2, ioaddr + MAC_SM);
384 iowrite16(0, ioaddr + MAC_SM);
385 mdelay(5);
386
387 /* MAC Bus Control Register */
388 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
389
390 /* Buffer Size Register */
391 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
392
393 /* Write TX ring start address */
394 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
395 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
396
397 /* Write RX ring start address */
398 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
399 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
400
401 /* Set interrupt waiting time and packet numbers */
402 iowrite16(0, ioaddr + MT_ICR);
403 iowrite16(0, ioaddr + MR_ICR);
404
405 /* Enable interrupts */
406 iowrite16(INT_MASK, ioaddr + MIER);
407
408 /* Enable TX and RX */
409 iowrite16(lp->mcr0 | 0x0002, ioaddr);
410
411 /* Let TX poll the descriptors
412 * we may got called by r6040_tx_timeout which has left
413 * some unsent tx buffers */
414 iowrite16(0x01, ioaddr + MTPR);
415}
416
417static void r6040_tx_timeout(struct net_device *dev)
418{
419 struct r6040_private *priv = netdev_priv(dev);
420 void __iomem *ioaddr = priv->base;
421
422 netdev_warn(dev, "transmit timed out, int enable %4.4x "
423 "status %4.4x\n",
424 ioread16(ioaddr + MIER),
425 ioread16(ioaddr + MISR));
426
427 dev->stats.tx_errors++;
428
429 /* Reset MAC and re-init all registers */
430 r6040_init_mac_regs(dev);
431}
432
433static struct net_device_stats *r6040_get_stats(struct net_device *dev)
434{
435 struct r6040_private *priv = netdev_priv(dev);
436 void __iomem *ioaddr = priv->base;
437 unsigned long flags;
438
439 spin_lock_irqsave(&priv->lock, flags);
440 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
441 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
442 spin_unlock_irqrestore(&priv->lock, flags);
443
444 return &dev->stats;
445}
446
447/* Stop RDC MAC and Free the allocated resource */
448static void r6040_down(struct net_device *dev)
449{
450 struct r6040_private *lp = netdev_priv(dev);
451 void __iomem *ioaddr = lp->base;
452 int limit = 2048;
453 u16 *adrp;
454 u16 cmd;
455
456 /* Stop MAC */
457 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
458 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
459 while (limit--) {
460 cmd = ioread16(ioaddr + MCR1);
461 if (cmd & 0x1)
462 break;
463 }
464
465 /* Restore MAC Address to MIDx */
466 adrp = (u16 *) dev->dev_addr;
467 iowrite16(adrp[0], ioaddr + MID_0L);
468 iowrite16(adrp[1], ioaddr + MID_0M);
469 iowrite16(adrp[2], ioaddr + MID_0H);
470}
471
472static int r6040_close(struct net_device *dev)
473{
474 struct r6040_private *lp = netdev_priv(dev);
475 struct pci_dev *pdev = lp->pdev;
476
477 spin_lock_irq(&lp->lock);
478 napi_disable(&lp->napi);
479 netif_stop_queue(dev);
480 r6040_down(dev);
481
482 free_irq(dev->irq, dev);
483
484 /* Free RX buffer */
485 r6040_free_rxbufs(dev);
486
487 /* Free TX buffer */
488 r6040_free_txbufs(dev);
489
490 spin_unlock_irq(&lp->lock);
491
492 /* Free Descriptor memory */
493 if (lp->rx_ring) {
494 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
495 lp->rx_ring = NULL;
496 }
497
498 if (lp->tx_ring) {
499 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
500 lp->tx_ring = NULL;
501 }
502
503 return 0;
504}
505
506static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
507{
508 struct r6040_private *lp = netdev_priv(dev);
509
510 if (!lp->phydev)
511 return -EINVAL;
512
513 return phy_mii_ioctl(lp->phydev, rq, cmd);
514}
515
516static int r6040_rx(struct net_device *dev, int limit)
517{
518 struct r6040_private *priv = netdev_priv(dev);
519 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
520 struct sk_buff *skb_ptr, *new_skb;
521 int count = 0;
522 u16 err;
523
524 /* Limit not reached and the descriptor belongs to the CPU */
525 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
526 /* Read the descriptor status */
527 err = descptr->status;
528 /* Global error status set */
529 if (err & DSC_RX_ERR) {
530 /* RX dribble */
531 if (err & DSC_RX_ERR_DRI)
532 dev->stats.rx_frame_errors++;
533 /* Buffer lenght exceeded */
534 if (err & DSC_RX_ERR_BUF)
535 dev->stats.rx_length_errors++;
536 /* Packet too long */
537 if (err & DSC_RX_ERR_LONG)
538 dev->stats.rx_length_errors++;
539 /* Packet < 64 bytes */
540 if (err & DSC_RX_ERR_RUNT)
541 dev->stats.rx_length_errors++;
542 /* CRC error */
543 if (err & DSC_RX_ERR_CRC) {
544 spin_lock(&priv->lock);
545 dev->stats.rx_crc_errors++;
546 spin_unlock(&priv->lock);
547 }
548 goto next_descr;
549 }
550
551 /* Packet successfully received */
552 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
553 if (!new_skb) {
554 dev->stats.rx_dropped++;
555 goto next_descr;
556 }
557 skb_ptr = descptr->skb_ptr;
558 skb_ptr->dev = priv->dev;
559
560 /* Do not count the CRC */
561 skb_put(skb_ptr, descptr->len - 4);
562 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
563 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
564 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
565
566 /* Send to upper layer */
567 netif_receive_skb(skb_ptr);
568 dev->stats.rx_packets++;
569 dev->stats.rx_bytes += descptr->len - 4;
570
571 /* put new skb into descriptor */
572 descptr->skb_ptr = new_skb;
573 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
574 descptr->skb_ptr->data,
575 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
576
577next_descr:
578 /* put the descriptor back to the MAC */
579 descptr->status = DSC_OWNER_MAC;
580 descptr = descptr->vndescp;
581 count++;
582 }
583 priv->rx_remove_ptr = descptr;
584
585 return count;
586}
587
588static void r6040_tx(struct net_device *dev)
589{
590 struct r6040_private *priv = netdev_priv(dev);
591 struct r6040_descriptor *descptr;
592 void __iomem *ioaddr = priv->base;
593 struct sk_buff *skb_ptr;
594 u16 err;
595
596 spin_lock(&priv->lock);
597 descptr = priv->tx_remove_ptr;
598 while (priv->tx_free_desc < TX_DCNT) {
599 /* Check for errors */
600 err = ioread16(ioaddr + MLSR);
601
602 if (err & 0x0200)
603 dev->stats.rx_fifo_errors++;
604 if (err & (0x2000 | 0x4000))
605 dev->stats.tx_carrier_errors++;
606
607 if (descptr->status & DSC_OWNER_MAC)
608 break; /* Not complete */
609 skb_ptr = descptr->skb_ptr;
610 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
611 skb_ptr->len, PCI_DMA_TODEVICE);
612 /* Free buffer */
613 dev_kfree_skb_irq(skb_ptr);
614 descptr->skb_ptr = NULL;
615 /* To next descriptor */
616 descptr = descptr->vndescp;
617 priv->tx_free_desc++;
618 }
619 priv->tx_remove_ptr = descptr;
620
621 if (priv->tx_free_desc)
622 netif_wake_queue(dev);
623 spin_unlock(&priv->lock);
624}
625
626static int r6040_poll(struct napi_struct *napi, int budget)
627{
628 struct r6040_private *priv =
629 container_of(napi, struct r6040_private, napi);
630 struct net_device *dev = priv->dev;
631 void __iomem *ioaddr = priv->base;
632 int work_done;
633
634 work_done = r6040_rx(dev, budget);
635
636 if (work_done < budget) {
637 napi_complete(napi);
638 /* Enable RX interrupt */
639 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
640 }
641 return work_done;
642}
643
644/* The RDC interrupt handler. */
645static irqreturn_t r6040_interrupt(int irq, void *dev_id)
646{
647 struct net_device *dev = dev_id;
648 struct r6040_private *lp = netdev_priv(dev);
649 void __iomem *ioaddr = lp->base;
650 u16 misr, status;
651
652 /* Save MIER */
653 misr = ioread16(ioaddr + MIER);
654 /* Mask off RDC MAC interrupt */
655 iowrite16(MSK_INT, ioaddr + MIER);
656 /* Read MISR status and clear */
657 status = ioread16(ioaddr + MISR);
658
659 if (status == 0x0000 || status == 0xffff) {
660 /* Restore RDC MAC interrupt */
661 iowrite16(misr, ioaddr + MIER);
662 return IRQ_NONE;
663 }
664
665 /* RX interrupt request */
666 if (status & RX_INTS) {
667 if (status & RX_NO_DESC) {
668 /* RX descriptor unavailable */
669 dev->stats.rx_dropped++;
670 dev->stats.rx_missed_errors++;
671 }
672 if (status & RX_FIFO_FULL)
673 dev->stats.rx_fifo_errors++;
674
675 /* Mask off RX interrupt */
676 misr &= ~RX_INTS;
677 napi_schedule(&lp->napi);
678 }
679
680 /* TX interrupt request */
681 if (status & TX_INTS)
682 r6040_tx(dev);
683
684 /* Restore RDC MAC interrupt */
685 iowrite16(misr, ioaddr + MIER);
686
687 return IRQ_HANDLED;
688}
689
690#ifdef CONFIG_NET_POLL_CONTROLLER
691static void r6040_poll_controller(struct net_device *dev)
692{
693 disable_irq(dev->irq);
694 r6040_interrupt(dev->irq, dev);
695 enable_irq(dev->irq);
696}
697#endif
698
699/* Init RDC MAC */
700static int r6040_up(struct net_device *dev)
701{
702 struct r6040_private *lp = netdev_priv(dev);
703 void __iomem *ioaddr = lp->base;
704 int ret;
705
706 /* Initialise and alloc RX/TX buffers */
707 r6040_init_txbufs(dev);
708 ret = r6040_alloc_rxbufs(dev);
709 if (ret)
710 return ret;
711
712 /* improve performance (by RDC guys) */
713 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
714 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
715 r6040_phy_write(ioaddr, 0, 19, 0x0000);
716 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
717
718 /* Initialize all MAC registers */
719 r6040_init_mac_regs(dev);
720
721 return 0;
722}
723
724
725/* Read/set MAC address routines */
726static void r6040_mac_address(struct net_device *dev)
727{
728 struct r6040_private *lp = netdev_priv(dev);
729 void __iomem *ioaddr = lp->base;
730 u16 *adrp;
731
732 /* MAC operation register */
733 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
734 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
735 iowrite16(0, ioaddr + MAC_SM);
736 mdelay(5);
737
738 /* Restore MAC Address */
739 adrp = (u16 *) dev->dev_addr;
740 iowrite16(adrp[0], ioaddr + MID_0L);
741 iowrite16(adrp[1], ioaddr + MID_0M);
742 iowrite16(adrp[2], ioaddr + MID_0H);
743}
744
745static int r6040_open(struct net_device *dev)
746{
747 struct r6040_private *lp = netdev_priv(dev);
748 int ret;
749
750 /* Request IRQ and Register interrupt handler */
751 ret = request_irq(dev->irq, r6040_interrupt,
752 IRQF_SHARED, dev->name, dev);
753 if (ret)
754 return ret;
755
756 /* Set MAC address */
757 r6040_mac_address(dev);
758
759 /* Allocate Descriptor memory */
760 lp->rx_ring =
761 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
762 if (!lp->rx_ring)
763 return -ENOMEM;
764
765 lp->tx_ring =
766 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
767 if (!lp->tx_ring) {
768 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
769 lp->rx_ring_dma);
770 return -ENOMEM;
771 }
772
773 ret = r6040_up(dev);
774 if (ret) {
775 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
776 lp->tx_ring_dma);
777 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
778 lp->rx_ring_dma);
779 return ret;
780 }
781
782 napi_enable(&lp->napi);
783 netif_start_queue(dev);
784
785 return 0;
786}
787
788static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
789 struct net_device *dev)
790{
791 struct r6040_private *lp = netdev_priv(dev);
792 struct r6040_descriptor *descptr;
793 void __iomem *ioaddr = lp->base;
794 unsigned long flags;
795
796 /* Critical Section */
797 spin_lock_irqsave(&lp->lock, flags);
798
799 /* TX resource check */
800 if (!lp->tx_free_desc) {
801 spin_unlock_irqrestore(&lp->lock, flags);
802 netif_stop_queue(dev);
803 netdev_err(dev, ": no tx descriptor\n");
804 return NETDEV_TX_BUSY;
805 }
806
807 /* Statistic Counter */
808 dev->stats.tx_packets++;
809 dev->stats.tx_bytes += skb->len;
810 /* Set TX descriptor & Transmit it */
811 lp->tx_free_desc--;
812 descptr = lp->tx_insert_ptr;
813 if (skb->len < MISR)
814 descptr->len = MISR;
815 else
816 descptr->len = skb->len;
817
818 descptr->skb_ptr = skb;
819 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
820 skb->data, skb->len, PCI_DMA_TODEVICE));
821 descptr->status = DSC_OWNER_MAC;
822 /* Trigger the MAC to check the TX descriptor */
823 iowrite16(0x01, ioaddr + MTPR);
824 lp->tx_insert_ptr = descptr->vndescp;
825
826 /* If no tx resource, stop */
827 if (!lp->tx_free_desc)
828 netif_stop_queue(dev);
829
830 spin_unlock_irqrestore(&lp->lock, flags);
831
832 return NETDEV_TX_OK;
833}
834
835static void r6040_multicast_list(struct net_device *dev)
836{
837 struct r6040_private *lp = netdev_priv(dev);
838 void __iomem *ioaddr = lp->base;
839 u16 *adrp;
840 u16 reg;
841 unsigned long flags;
842 struct netdev_hw_addr *ha;
843 int i;
844
845 /* MAC Address */
846 adrp = (u16 *)dev->dev_addr;
847 iowrite16(adrp[0], ioaddr + MID_0L);
848 iowrite16(adrp[1], ioaddr + MID_0M);
849 iowrite16(adrp[2], ioaddr + MID_0H);
850
851 /* Promiscous Mode */
852 spin_lock_irqsave(&lp->lock, flags);
853
854 /* Clear AMCP & PROM bits */
855 reg = ioread16(ioaddr) & ~0x0120;
856 if (dev->flags & IFF_PROMISC) {
857 reg |= 0x0020;
858 lp->mcr0 |= 0x0020;
859 }
860 /* Too many multicast addresses
861 * accept all traffic */
862 else if ((netdev_mc_count(dev) > MCAST_MAX) ||
863 (dev->flags & IFF_ALLMULTI))
864 reg |= 0x0020;
865
866 iowrite16(reg, ioaddr);
867 spin_unlock_irqrestore(&lp->lock, flags);
868
869 /* Build the hash table */
870 if (netdev_mc_count(dev) > MCAST_MAX) {
871 u16 hash_table[4];
872 u32 crc;
873
874 for (i = 0; i < 4; i++)
875 hash_table[i] = 0;
876
877 netdev_for_each_mc_addr(ha, dev) {
878 char *addrs = ha->addr;
879
880 if (!(*addrs & 1))
881 continue;
882
883 crc = ether_crc_le(6, addrs);
884 crc >>= 26;
885 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
886 }
887 /* Fill the MAC hash tables with their values */
888 iowrite16(hash_table[0], ioaddr + MAR0);
889 iowrite16(hash_table[1], ioaddr + MAR1);
890 iowrite16(hash_table[2], ioaddr + MAR2);
891 iowrite16(hash_table[3], ioaddr + MAR3);
892 }
893 /* Multicast Address 1~4 case */
894 i = 0;
895 netdev_for_each_mc_addr(ha, dev) {
896 if (i < MCAST_MAX) {
897 adrp = (u16 *) ha->addr;
898 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
899 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
900 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
901 } else {
902 iowrite16(0xffff, ioaddr + MID_1L + 8 * i);
903 iowrite16(0xffff, ioaddr + MID_1M + 8 * i);
904 iowrite16(0xffff, ioaddr + MID_1H + 8 * i);
905 }
906 i++;
907 }
908}
909
910static void netdev_get_drvinfo(struct net_device *dev,
911 struct ethtool_drvinfo *info)
912{
913 struct r6040_private *rp = netdev_priv(dev);
914
915 strcpy(info->driver, DRV_NAME);
916 strcpy(info->version, DRV_VERSION);
917 strcpy(info->bus_info, pci_name(rp->pdev));
918}
919
920static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
921{
922 struct r6040_private *rp = netdev_priv(dev);
923
924 return phy_ethtool_gset(rp->phydev, cmd);
925}
926
927static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
928{
929 struct r6040_private *rp = netdev_priv(dev);
930
931 return phy_ethtool_sset(rp->phydev, cmd);
932}
933
934static const struct ethtool_ops netdev_ethtool_ops = {
935 .get_drvinfo = netdev_get_drvinfo,
936 .get_settings = netdev_get_settings,
937 .set_settings = netdev_set_settings,
938 .get_link = ethtool_op_get_link,
939};
940
941static const struct net_device_ops r6040_netdev_ops = {
942 .ndo_open = r6040_open,
943 .ndo_stop = r6040_close,
944 .ndo_start_xmit = r6040_start_xmit,
945 .ndo_get_stats = r6040_get_stats,
946 .ndo_set_multicast_list = r6040_multicast_list,
947 .ndo_change_mtu = eth_change_mtu,
948 .ndo_validate_addr = eth_validate_addr,
949 .ndo_set_mac_address = eth_mac_addr,
950 .ndo_do_ioctl = r6040_ioctl,
951 .ndo_tx_timeout = r6040_tx_timeout,
952#ifdef CONFIG_NET_POLL_CONTROLLER
953 .ndo_poll_controller = r6040_poll_controller,
954#endif
955};
956
957static void r6040_adjust_link(struct net_device *dev)
958{
959 struct r6040_private *lp = netdev_priv(dev);
960 struct phy_device *phydev = lp->phydev;
961 int status_changed = 0;
962 void __iomem *ioaddr = lp->base;
963
964 BUG_ON(!phydev);
965
966 if (lp->old_link != phydev->link) {
967 status_changed = 1;
968 lp->old_link = phydev->link;
969 }
970
971 /* reflect duplex change */
972 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
973 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? 0x8000 : 0);
974 iowrite16(lp->mcr0, ioaddr);
975
976 status_changed = 1;
977 lp->old_duplex = phydev->duplex;
978 }
979
980 if (status_changed) {
981 pr_info("%s: link %s", dev->name, phydev->link ?
982 "UP" : "DOWN");
983 if (phydev->link)
984 pr_cont(" - %d/%s", phydev->speed,
985 DUPLEX_FULL == phydev->duplex ? "full" : "half");
986 pr_cont("\n");
987 }
988}
989
990static int r6040_mii_probe(struct net_device *dev)
991{
992 struct r6040_private *lp = netdev_priv(dev);
993 struct phy_device *phydev = NULL;
994
995 phydev = phy_find_first(lp->mii_bus);
996 if (!phydev) {
997 dev_err(&lp->pdev->dev, "no PHY found\n");
998 return -ENODEV;
999 }
1000
1001 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1002 0, PHY_INTERFACE_MODE_MII);
1003
1004 if (IS_ERR(phydev)) {
1005 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1006 return PTR_ERR(phydev);
1007 }
1008
1009 /* mask with MAC supported features */
1010 phydev->supported &= (SUPPORTED_10baseT_Half
1011 | SUPPORTED_10baseT_Full
1012 | SUPPORTED_100baseT_Half
1013 | SUPPORTED_100baseT_Full
1014 | SUPPORTED_Autoneg
1015 | SUPPORTED_MII
1016 | SUPPORTED_TP);
1017
1018 phydev->advertising = phydev->supported;
1019 lp->phydev = phydev;
1020 lp->old_link = 0;
1021 lp->old_duplex = -1;
1022
1023 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1024 "(mii_bus:phy_addr=%s)\n",
1025 phydev->drv->name, dev_name(&phydev->dev));
1026
1027 return 0;
1028}
1029
1030static int __devinit r6040_init_one(struct pci_dev *pdev,
1031 const struct pci_device_id *ent)
1032{
1033 struct net_device *dev;
1034 struct r6040_private *lp;
1035 void __iomem *ioaddr;
1036 int err, io_size = R6040_IO_SIZE;
1037 static int card_idx = -1;
1038 int bar = 0;
1039 u16 *adrp;
1040 int i;
1041
1042 printk("%s\n", version);
1043
1044 err = pci_enable_device(pdev);
1045 if (err)
1046 goto err_out;
1047
1048 /* this should always be supported */
1049 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1050 if (err) {
1051 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1052 "not supported by the card\n");
1053 goto err_out;
1054 }
1055 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1056 if (err) {
1057 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1058 "not supported by the card\n");
1059 goto err_out;
1060 }
1061
1062 /* IO Size check */
1063 if (pci_resource_len(pdev, bar) < io_size) {
1064 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1065 err = -EIO;
1066 goto err_out;
1067 }
1068
1069 pci_set_master(pdev);
1070
1071 dev = alloc_etherdev(sizeof(struct r6040_private));
1072 if (!dev) {
1073 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
1074 err = -ENOMEM;
1075 goto err_out;
1076 }
1077 SET_NETDEV_DEV(dev, &pdev->dev);
1078 lp = netdev_priv(dev);
1079
1080 err = pci_request_regions(pdev, DRV_NAME);
1081
1082 if (err) {
1083 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1084 goto err_out_free_dev;
1085 }
1086
1087 ioaddr = pci_iomap(pdev, bar, io_size);
1088 if (!ioaddr) {
1089 dev_err(&pdev->dev, "ioremap failed for device\n");
1090 err = -EIO;
1091 goto err_out_free_res;
1092 }
1093 /* If PHY status change register is still set to zero it means the
1094 * bootloader didn't initialize it */
1095 if (ioread16(ioaddr + PHY_CC) == 0)
1096 iowrite16(0x9f07, ioaddr + PHY_CC);
1097
1098 /* Init system & device */
1099 lp->base = ioaddr;
1100 dev->irq = pdev->irq;
1101
1102 spin_lock_init(&lp->lock);
1103 pci_set_drvdata(pdev, dev);
1104
1105 /* Set MAC address */
1106 card_idx++;
1107
1108 adrp = (u16 *)dev->dev_addr;
1109 adrp[0] = ioread16(ioaddr + MID_0L);
1110 adrp[1] = ioread16(ioaddr + MID_0M);
1111 adrp[2] = ioread16(ioaddr + MID_0H);
1112
1113 /* Some bootloader/BIOSes do not initialize
1114 * MAC address, warn about that */
1115 if (!(adrp[0] || adrp[1] || adrp[2])) {
1116 netdev_warn(dev, "MAC address not initialized, generating random\n");
1117 random_ether_addr(dev->dev_addr);
1118 }
1119
1120 /* Link new device into r6040_root_dev */
1121 lp->pdev = pdev;
1122 lp->dev = dev;
1123
1124 /* Init RDC private data */
1125 lp->mcr0 = 0x1002;
1126 lp->phy_addr = phy_table[card_idx];
1127
1128 /* The RDC-specific entries in the device structure. */
1129 dev->netdev_ops = &r6040_netdev_ops;
1130 dev->ethtool_ops = &netdev_ethtool_ops;
1131 dev->watchdog_timeo = TX_TIMEOUT;
1132
1133 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1134
1135 lp->mii_bus = mdiobus_alloc();
1136 if (!lp->mii_bus) {
1137 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1138 goto err_out_unmap;
1139 }
1140
1141 lp->mii_bus->priv = dev;
1142 lp->mii_bus->read = r6040_mdiobus_read;
1143 lp->mii_bus->write = r6040_mdiobus_write;
1144 lp->mii_bus->reset = r6040_mdiobus_reset;
1145 lp->mii_bus->name = "r6040_eth_mii";
1146 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", card_idx);
1147 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1148 if (!lp->mii_bus->irq) {
1149 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
1150 goto err_out_mdio;
1151 }
1152
1153 for (i = 0; i < PHY_MAX_ADDR; i++)
1154 lp->mii_bus->irq[i] = PHY_POLL;
1155
1156 err = mdiobus_register(lp->mii_bus);
1157 if (err) {
1158 dev_err(&pdev->dev, "failed to register MII bus\n");
1159 goto err_out_mdio_irq;
1160 }
1161
1162 err = r6040_mii_probe(dev);
1163 if (err) {
1164 dev_err(&pdev->dev, "failed to probe MII bus\n");
1165 goto err_out_mdio_unregister;
1166 }
1167
1168 /* Register net device. After this dev->name assign */
1169 err = register_netdev(dev);
1170 if (err) {
1171 dev_err(&pdev->dev, "Failed to register net device\n");
1172 goto err_out_mdio_unregister;
1173 }
1174 return 0;
1175
1176err_out_mdio_unregister:
1177 mdiobus_unregister(lp->mii_bus);
1178err_out_mdio_irq:
1179 kfree(lp->mii_bus->irq);
1180err_out_mdio:
1181 mdiobus_free(lp->mii_bus);
1182err_out_unmap:
1183 pci_iounmap(pdev, ioaddr);
1184err_out_free_res:
1185 pci_release_regions(pdev);
1186err_out_free_dev:
1187 free_netdev(dev);
1188err_out:
1189 return err;
1190}
1191
1192static void __devexit r6040_remove_one(struct pci_dev *pdev)
1193{
1194 struct net_device *dev = pci_get_drvdata(pdev);
1195 struct r6040_private *lp = netdev_priv(dev);
1196
1197 unregister_netdev(dev);
1198 mdiobus_unregister(lp->mii_bus);
1199 kfree(lp->mii_bus->irq);
1200 mdiobus_free(lp->mii_bus);
1201 pci_release_regions(pdev);
1202 free_netdev(dev);
1203 pci_disable_device(pdev);
1204 pci_set_drvdata(pdev, NULL);
1205}
1206
1207
1208static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1209 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1210 { 0 }
1211};
1212MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1213
1214static struct pci_driver r6040_driver = {
1215 .name = DRV_NAME,
1216 .id_table = r6040_pci_tbl,
1217 .probe = r6040_init_one,
1218 .remove = __devexit_p(r6040_remove_one),
1219};
1220
1221
1222static int __init r6040_init(void)
1223{
1224 return pci_register_driver(&r6040_driver);
1225}
1226
1227
1228static void __exit r6040_cleanup(void)
1229{
1230 pci_unregister_driver(&r6040_driver);
1231}
1232
1233module_init(r6040_init);
1234module_exit(r6040_cleanup);