tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _E1000_DEFINES_H_
29#define _E1000_DEFINES_H_
30
31/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
32#define REQ_TX_DESCRIPTOR_MULTIPLE 8
33#define REQ_RX_DESCRIPTOR_MULTIPLE 8
34
35/* Definitions for power management and wakeup registers */
36/* Wake Up Control */
37#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
38
39/* Wake Up Filter Control */
40#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
41#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
42#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
43#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
44#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
45
46/* Extended Device Control */
47#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
48/* Physical Func Reset Done Indication */
49#define E1000_CTRL_EXT_PFRSTD 0x00004000
50#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
51#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
52#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
53#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
54#define E1000_CTRL_EXT_EIAME 0x01000000
55#define E1000_CTRL_EXT_IRCA 0x00000001
56/* Interrupt delay cancellation */
57/* Driver loaded bit for FW */
58#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
59/* Interrupt acknowledge Auto-mask */
60/* Clear Interrupt timers after IMS clear */
61/* packet buffer parity error detection enabled */
62/* descriptor FIFO parity error detection enable */
63#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
64#define E1000_I2CCMD_REG_ADDR_SHIFT 16
65#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
66#define E1000_I2CCMD_OPCODE_READ 0x08000000
67#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
68#define E1000_I2CCMD_READY 0x20000000
69#define E1000_I2CCMD_ERROR 0x80000000
70#define E1000_MAX_SGMII_PHY_REG_ADDR 255
71#define E1000_I2CCMD_PHY_TIMEOUT 200
72#define E1000_IVAR_VALID 0x80
73#define E1000_GPIE_NSICR 0x00000001
74#define E1000_GPIE_MSIX_MODE 0x00000010
75#define E1000_GPIE_EIAME 0x40000000
76#define E1000_GPIE_PBA 0x80000000
77
78/* Receive Descriptor bit definitions */
79#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
80#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
81#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
82#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
83#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
84#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
85#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
86
87#define E1000_RXDEXT_STATERR_CE 0x01000000
88#define E1000_RXDEXT_STATERR_SE 0x02000000
89#define E1000_RXDEXT_STATERR_SEQ 0x04000000
90#define E1000_RXDEXT_STATERR_CXE 0x10000000
91#define E1000_RXDEXT_STATERR_TCPE 0x20000000
92#define E1000_RXDEXT_STATERR_IPE 0x40000000
93#define E1000_RXDEXT_STATERR_RXE 0x80000000
94
95/* Same mask, but for extended and packet split descriptors */
96#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
97 E1000_RXDEXT_STATERR_CE | \
98 E1000_RXDEXT_STATERR_SE | \
99 E1000_RXDEXT_STATERR_SEQ | \
100 E1000_RXDEXT_STATERR_CXE | \
101 E1000_RXDEXT_STATERR_RXE)
102
103#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
104#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
105#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
106#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
107#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
108
109
110/* Management Control */
111#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
112#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
113/* Enable Neighbor Discovery Filtering */
114#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
115#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
116/* Enable MAC address filtering */
117#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
118
119/* Receive Control */
120#define E1000_RCTL_EN 0x00000002 /* enable */
121#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
122#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
123#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
124#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
125#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
126#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
127#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
128#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
129#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
130#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
131#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
132#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
133#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
134#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
135
136/*
137 * Use byte values for the following shift parameters
138 * Usage:
139 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
140 * E1000_PSRCTL_BSIZE0_MASK) |
141 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
142 * E1000_PSRCTL_BSIZE1_MASK) |
143 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
144 * E1000_PSRCTL_BSIZE2_MASK) |
145 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
146 * E1000_PSRCTL_BSIZE3_MASK))
147 * where value0 = [128..16256], default=256
148 * value1 = [1024..64512], default=4096
149 * value2 = [0..64512], default=4096
150 * value3 = [0..64512], default=0
151 */
152
153#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
154#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
155#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
156#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
157
158#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
159#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
160#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
161#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
162
163/* SWFW_SYNC Definitions */
164#define E1000_SWFW_EEP_SM 0x1
165#define E1000_SWFW_PHY0_SM 0x2
166#define E1000_SWFW_PHY1_SM 0x4
167
168/* FACTPS Definitions */
169/* Device Control */
170#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
171#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
172#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
173#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
174#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
175#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
176#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
177#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
178#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
179#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
180#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
181/* Defined polarity of Dock/Undock indication in SDP[0] */
182/* Reset both PHY ports, through PHYRST_N pin */
183/* enable link status from external LINK_0 and LINK_1 pins */
184#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
185#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
186#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
187#define E1000_CTRL_RST 0x04000000 /* Global reset */
188#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
189#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
190#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
191#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
192/* Initiate an interrupt to manageability engine */
193#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
194
195/* Bit definitions for the Management Data IO (MDIO) and Management Data
196 * Clock (MDC) pins in the Device Control Register.
197 */
198
199#define E1000_CONNSW_ENRGSRC 0x4
200#define E1000_PCS_CFG_PCS_EN 8
201#define E1000_PCS_LCTL_FLV_LINK_UP 1
202#define E1000_PCS_LCTL_FSV_100 2
203#define E1000_PCS_LCTL_FSV_1000 4
204#define E1000_PCS_LCTL_FDV_FULL 8
205#define E1000_PCS_LCTL_FSD 0x10
206#define E1000_PCS_LCTL_FORCE_LINK 0x20
207#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
208#define E1000_PCS_LCTL_AN_ENABLE 0x10000
209#define E1000_PCS_LCTL_AN_RESTART 0x20000
210#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
211#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
212
213#define E1000_PCS_LSTS_LINK_OK 1
214#define E1000_PCS_LSTS_SPEED_100 2
215#define E1000_PCS_LSTS_SPEED_1000 4
216#define E1000_PCS_LSTS_DUPLEX_FULL 8
217#define E1000_PCS_LSTS_SYNK_OK 0x10
218
219/* Device Status */
220#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
221#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
222#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
223#define E1000_STATUS_FUNC_SHIFT 2
224#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
225#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
226#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
227#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
228/* Change in Dock/Undock state. Clear on write '0'. */
229/* Status of Master requests. */
230#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
231/* BMC external code execution disabled */
232
233/* Constants used to intrepret the masked PCI-X bus speed. */
234
235#define SPEED_10 10
236#define SPEED_100 100
237#define SPEED_1000 1000
238#define HALF_DUPLEX 1
239#define FULL_DUPLEX 2
240
241
242#define ADVERTISE_10_HALF 0x0001
243#define ADVERTISE_10_FULL 0x0002
244#define ADVERTISE_100_HALF 0x0004
245#define ADVERTISE_100_FULL 0x0008
246#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
247#define ADVERTISE_1000_FULL 0x0020
248
249/* 1000/H is not supported, nor spec-compliant. */
250#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
251 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
252 ADVERTISE_1000_FULL)
253#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
254 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
255#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
256#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
257#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
258 ADVERTISE_1000_FULL)
259#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
260
261#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
262
263/* LED Control */
264#define E1000_LEDCTL_LED0_MODE_SHIFT 0
265#define E1000_LEDCTL_LED0_BLINK 0x00000080
266
267#define E1000_LEDCTL_MODE_LED_ON 0xE
268#define E1000_LEDCTL_MODE_LED_OFF 0xF
269
270/* Transmit Descriptor bit definitions */
271#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
272#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
273#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
274#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
275#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
276#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
277#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
278/* Extended desc bits for Linksec and timesync */
279
280/* Transmit Control */
281#define E1000_TCTL_EN 0x00000002 /* enable tx */
282#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
283#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
284#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
285#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
286
287/* Transmit Arbitration Count */
288
289/* SerDes Control */
290#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
291
292/* Receive Checksum Control */
293#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
294#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
295#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
296#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
297
298/* Header split receive */
299#define E1000_RFCTL_LEF 0x00040000
300
301/* Collision related configuration parameters */
302#define E1000_COLLISION_THRESHOLD 15
303#define E1000_CT_SHIFT 4
304#define E1000_COLLISION_DISTANCE 63
305#define E1000_COLD_SHIFT 12
306
307/* Ethertype field values */
308#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
309
310#define MAX_JUMBO_FRAME_SIZE 0x3F00
311
312/* PBA constants */
313#define E1000_PBA_34K 0x0022
314#define E1000_PBA_64K 0x0040 /* 64KB */
315
316/* SW Semaphore Register */
317#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
318#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
319
320/* Interrupt Cause Read */
321#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
322#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
323#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
324#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
325#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
326#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
327#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
328/* If this bit asserted, the driver should claim the interrupt */
329#define E1000_ICR_INT_ASSERTED 0x80000000
330/* LAN connected device generates an interrupt */
331#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
332
333/* Extended Interrupt Cause Read */
334#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
335#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
336#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
337#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
338#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
339#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
340#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
341#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
342#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
343/* TCP Timer */
344
345/*
346 * This defines the bits that are set in the Interrupt Mask
347 * Set/Read Register. Each bit is documented below:
348 * o RXT0 = Receiver Timer Interrupt (ring 0)
349 * o TXDW = Transmit Descriptor Written Back
350 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
351 * o RXSEQ = Receive Sequence Error
352 * o LSC = Link Status Change
353 */
354#define IMS_ENABLE_MASK ( \
355 E1000_IMS_RXT0 | \
356 E1000_IMS_TXDW | \
357 E1000_IMS_RXDMT0 | \
358 E1000_IMS_RXSEQ | \
359 E1000_IMS_LSC | \
360 E1000_IMS_DOUTSYNC)
361
362/* Interrupt Mask Set */
363#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
364#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
365#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
366#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
367#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
368#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
369#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
370#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
371
372/* Extended Interrupt Mask Set */
373#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
374
375/* Interrupt Cause Set */
376#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
377#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
378#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
379
380/* Extended Interrupt Cause Set */
381
382/* Transmit Descriptor Control */
383/* Enable the counting of descriptors still to be processed. */
384
385/* Flow Control Constants */
386#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
387#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
388#define FLOW_CONTROL_TYPE 0x8808
389
390/* 802.1q VLAN Packet Size */
391#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
392#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
393
394/* Receive Address */
395/*
396 * Number of high/low register pairs in the RAR. The RAR (Receive Address
397 * Registers) holds the directed and multicast addresses that we monitor.
398 * Technically, we have 16 spots. However, we reserve one of these spots
399 * (RAR[15]) for our directed address used by controllers with
400 * manageability enabled, allowing us room for 15 multicast addresses.
401 */
402#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
403#define E1000_RAL_MAC_ADDR_LEN 4
404#define E1000_RAH_MAC_ADDR_LEN 2
405#define E1000_RAH_POOL_MASK 0x03FC0000
406#define E1000_RAH_POOL_1 0x00040000
407
408/* Error Codes */
409#define E1000_ERR_NVM 1
410#define E1000_ERR_PHY 2
411#define E1000_ERR_CONFIG 3
412#define E1000_ERR_PARAM 4
413#define E1000_ERR_MAC_INIT 5
414#define E1000_ERR_RESET 9
415#define E1000_ERR_MASTER_REQUESTS_PENDING 10
416#define E1000_BLK_PHY_RESET 12
417#define E1000_ERR_SWFW_SYNC 13
418#define E1000_NOT_IMPLEMENTED 14
419#define E1000_ERR_MBX 15
420
421/* Loop limit on how long we wait for auto-negotiation to complete */
422#define COPPER_LINK_UP_LIMIT 10
423#define PHY_AUTO_NEG_LIMIT 45
424#define PHY_FORCE_LIMIT 20
425/* Number of 100 microseconds we wait for PCI Express master disable */
426#define MASTER_DISABLE_TIMEOUT 800
427/* Number of milliseconds we wait for PHY configuration done after MAC reset */
428#define PHY_CFG_TIMEOUT 100
429/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
430/* Number of milliseconds for NVM auto read done after MAC reset. */
431#define AUTO_READ_DONE_TIMEOUT 10
432
433/* Flow Control */
434#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
435
436#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
437#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
438
439#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */
440#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */
441#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
442#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
443#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
444#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
445#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
446#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */
447
448#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
449#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
450#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
451#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
452#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
453#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
454
455#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
456#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
457#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
458#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
459#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
460#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
461#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
462#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
463#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
464#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
465#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
466
467#define E1000_TIMINCA_16NS_SHIFT 24
468
469/* PCI Express Control */
470#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
471#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
472#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
473#define E1000_GCR_CAP_VER2 0x00040000
474
475/* PHY Control Register */
476#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
477#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
478#define MII_CR_POWER_DOWN 0x0800 /* Power down */
479#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
480#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
481#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
482#define MII_CR_SPEED_1000 0x0040
483#define MII_CR_SPEED_100 0x2000
484#define MII_CR_SPEED_10 0x0000
485
486/* PHY Status Register */
487#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
488#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
489
490/* Autoneg Advertisement Register */
491#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
492#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
493#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
494#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
495#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
496#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
497
498/* Link Partner Ability Register (Base Page) */
499#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
500#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
501
502/* Autoneg Expansion Register */
503
504/* 1000BASE-T Control Register */
505#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
506#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
507#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
508 /* 0=Configure PHY as Slave */
509#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
510 /* 0=Automatic Master/Slave config */
511
512/* 1000BASE-T Status Register */
513#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
514#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
515
516
517/* PHY 1000 MII Register/Bit Definitions */
518/* PHY Registers defined by IEEE */
519#define PHY_CONTROL 0x00 /* Control Register */
520#define PHY_STATUS 0x01 /* Status Register */
521#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
522#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
523#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
524#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
525#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
526#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
527
528/* NVM Control */
529#define E1000_EECD_SK 0x00000001 /* NVM Clock */
530#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
531#define E1000_EECD_DI 0x00000004 /* NVM Data In */
532#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
533#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
534#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
535#define E1000_EECD_PRES 0x00000100 /* NVM Present */
536/* NVM Addressing bits based on type 0=small, 1=large */
537#define E1000_EECD_ADDR_BITS 0x00000400
538#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
539#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
540#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
541#define E1000_EECD_SIZE_EX_SHIFT 11
542
543/* Offset to data in NVM read/write registers */
544#define E1000_NVM_RW_REG_DATA 16
545#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
546#define E1000_NVM_RW_REG_START 1 /* Start operation */
547#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
548#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
549
550/* NVM Word Offsets */
551#define NVM_ID_LED_SETTINGS 0x0004
552/* For SERDES output amplitude adjustment. */
553#define NVM_INIT_CONTROL2_REG 0x000F
554#define NVM_INIT_CONTROL3_PORT_B 0x0014
555#define NVM_INIT_CONTROL3_PORT_A 0x0024
556#define NVM_ALT_MAC_ADDR_PTR 0x0037
557#define NVM_CHECKSUM_REG 0x003F
558
559#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
560#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
561#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
562#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
563
564#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
565
566/* Mask bits for fields in Word 0x0f of the NVM */
567#define NVM_WORD0F_PAUSE_MASK 0x3000
568#define NVM_WORD0F_ASM_DIR 0x2000
569
570/* Mask bits for fields in Word 0x1a of the NVM */
571
572/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
573#define NVM_SUM 0xBABA
574
575#define NVM_PBA_OFFSET_0 8
576#define NVM_PBA_OFFSET_1 9
577#define NVM_WORD_SIZE_BASE_SHIFT 6
578
579/* NVM Commands - Microwire */
580
581/* NVM Commands - SPI */
582#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
583#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
584#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
585#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
586#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
587
588/* SPI NVM Status Register */
589#define NVM_STATUS_RDY_SPI 0x01
590
591/* Word definitions for ID LED Settings */
592#define ID_LED_RESERVED_0000 0x0000
593#define ID_LED_RESERVED_FFFF 0xFFFF
594#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
595 (ID_LED_OFF1_OFF2 << 8) | \
596 (ID_LED_DEF1_DEF2 << 4) | \
597 (ID_LED_DEF1_DEF2))
598#define ID_LED_DEF1_DEF2 0x1
599#define ID_LED_DEF1_ON2 0x2
600#define ID_LED_DEF1_OFF2 0x3
601#define ID_LED_ON1_DEF2 0x4
602#define ID_LED_ON1_ON2 0x5
603#define ID_LED_ON1_OFF2 0x6
604#define ID_LED_OFF1_DEF2 0x7
605#define ID_LED_OFF1_ON2 0x8
606#define ID_LED_OFF1_OFF2 0x9
607
608#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
609#define IGP_ACTIVITY_LED_ENABLE 0x0300
610#define IGP_LED3_MODE 0x07000000
611
612/* PCI/PCI-X/PCI-EX Config space */
613#define PCIE_DEVICE_CONTROL2 0x28
614#define PCIE_DEVICE_CONTROL2_16ms 0x0005
615
616#define PHY_REVISION_MASK 0xFFFFFFF0
617#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
618#define MAX_PHY_MULTI_PAGE_REG 0xF
619
620/* Bit definitions for valid PHY IDs. */
621/*
622 * I = Integrated
623 * E = External
624 */
625#define M88E1111_I_PHY_ID 0x01410CC0
626#define IGP03E1000_E_PHY_ID 0x02A80390
627#define I82580_I_PHY_ID 0x015403A0
628#define I350_I_PHY_ID 0x015403B0
629#define M88_VENDOR 0x0141
630
631/* M88E1000 Specific Registers */
632#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
633#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
634#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
635
636#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
637#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
638
639/* M88E1000 PHY Specific Control Register */
640#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
641/* 1=CLK125 low, 0=CLK125 toggling */
642#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
643 /* Manual MDI configuration */
644#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
645/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
646#define M88E1000_PSCR_AUTO_X_1000T 0x0040
647/* Auto crossover enabled all speeds */
648#define M88E1000_PSCR_AUTO_X_MODE 0x0060
649/*
650 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
651 * 0=Normal 10BASE-T Rx Threshold
652 */
653/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
654#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
655
656/* M88E1000 PHY Specific Status Register */
657#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
658#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
659#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
660/*
661 * 0 = <50M
662 * 1 = 50-80M
663 * 2 = 80-110M
664 * 3 = 110-140M
665 * 4 = >140M
666 */
667#define M88E1000_PSSR_CABLE_LENGTH 0x0380
668#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
669#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
670
671#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
672
673/* M88E1000 Extended PHY Specific Control Register */
674/*
675 * 1 = Lost lock detect enabled.
676 * Will assert lost lock and bring
677 * link down if idle not seen
678 * within 1ms in 1000BASE-T
679 */
680/*
681 * Number of times we will attempt to autonegotiate before downshifting if we
682 * are the master
683 */
684#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
685#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
686/*
687 * Number of times we will attempt to autonegotiate before downshifting if we
688 * are the slave
689 */
690#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
691#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
692#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
693
694/* M88EC018 Rev 2 specific DownShift settings */
695#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
696#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
697
698/* MDI Control */
699#define E1000_MDIC_REG_SHIFT 16
700#define E1000_MDIC_PHY_SHIFT 21
701#define E1000_MDIC_OP_WRITE 0x04000000
702#define E1000_MDIC_OP_READ 0x08000000
703#define E1000_MDIC_READY 0x10000000
704#define E1000_MDIC_ERROR 0x40000000
705
706/* SerDes Control */
707#define E1000_GEN_CTL_READY 0x80000000
708#define E1000_GEN_CTL_ADDRESS_SHIFT 8
709#define E1000_GEN_POLL_TIMEOUT 640
710
711#define E1000_VFTA_ENTRY_SHIFT 5
712#define E1000_VFTA_ENTRY_MASK 0x7F
713#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
714
715/* DMA Coalescing register fields */
716#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based
717 on DMA coal */
718
719#endif