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1/*
2 * Low level TLB miss handlers for Book3E
3 *
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/processor.h>
14#include <asm/reg.h>
15#include <asm/page.h>
16#include <asm/mmu.h>
17#include <asm/ppc_asm.h>
18#include <asm/asm-offsets.h>
19#include <asm/cputable.h>
20#include <asm/pgtable.h>
21#include <asm/exception-64e.h>
22#include <asm/ppc-opcode.h>
23
24#ifdef CONFIG_PPC_64K_PAGES
25#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
26#else
27#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
28#endif
29#define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
30#define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
31#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
32
33
34/**********************************************************************
35 * *
36 * TLB miss handling for Book3E with TLB reservation and HES support *
37 * *
38 **********************************************************************/
39
40
41/* Data TLB miss */
42 START_EXCEPTION(data_tlb_miss)
43 TLB_MISS_PROLOG
44
45 /* Now we handle the fault proper. We only save DEAR in normal
46 * fault case since that's the only interesting values here.
47 * We could probably also optimize by not saving SRR0/1 in the
48 * linear mapping case but I'll leave that for later
49 */
50 mfspr r14,SPRN_ESR
51 mfspr r16,SPRN_DEAR /* get faulting address */
52 srdi r15,r16,60 /* get region */
53 cmpldi cr0,r15,0xc /* linear mapping ? */
54 TLB_MISS_STATS_SAVE_INFO
55 beq tlb_load_linear /* yes -> go to linear map load */
56
57 /* The page tables are mapped virtually linear. At this point, though,
58 * we don't know whether we are trying to fault in a first level
59 * virtual address or a virtual page table address. We can get that
60 * from bit 0x1 of the region ID which we have set for a page table
61 */
62 andi. r10,r15,0x1
63 bne- virt_page_table_tlb_miss
64
65 std r14,EX_TLB_ESR(r12); /* save ESR */
66 std r16,EX_TLB_DEAR(r12); /* save DEAR */
67
68 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
69 li r11,_PAGE_PRESENT
70 oris r11,r11,_PAGE_ACCESSED@h
71
72 /* We do the user/kernel test for the PID here along with the RW test
73 */
74 cmpldi cr0,r15,0 /* Check for user region */
75
76 /* We pre-test some combination of permissions to avoid double
77 * faults:
78 *
79 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
80 * ESR_ST is 0x00800000
81 * _PAGE_BAP_SW is 0x00000010
82 * So the shift is >> 19. This tests for supervisor writeability.
83 * If the page happens to be supervisor writeable and not user
84 * writeable, we will take a new fault later, but that should be
85 * a rare enough case.
86 *
87 * We also move ESR_ST in _PAGE_DIRTY position
88 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
89 *
90 * MAS1 is preset for all we need except for TID that needs to
91 * be cleared for kernel translations
92 */
93 rlwimi r11,r14,32-19,27,27
94 rlwimi r11,r14,32-16,19,19
95 beq normal_tlb_miss
96 /* XXX replace the RMW cycles with immediate loads + writes */
971: mfspr r10,SPRN_MAS1
98 cmpldi cr0,r15,8 /* Check for vmalloc region */
99 rlwinm r10,r10,0,16,1 /* Clear TID */
100 mtspr SPRN_MAS1,r10
101 beq+ normal_tlb_miss
102
103 /* We got a crappy address, just fault with whatever DEAR and ESR
104 * are here
105 */
106 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
107 TLB_MISS_EPILOG_ERROR
108 b exc_data_storage_book3e
109
110/* Instruction TLB miss */
111 START_EXCEPTION(instruction_tlb_miss)
112 TLB_MISS_PROLOG
113
114 /* If we take a recursive fault, the second level handler may need
115 * to know whether we are handling a data or instruction fault in
116 * order to get to the right store fault handler. We provide that
117 * info by writing a crazy value in ESR in our exception frame
118 */
119 li r14,-1 /* store to exception frame is done later */
120
121 /* Now we handle the fault proper. We only save DEAR in the non
122 * linear mapping case since we know the linear mapping case will
123 * not re-enter. We could indeed optimize and also not save SRR0/1
124 * in the linear mapping case but I'll leave that for later
125 *
126 * Faulting address is SRR0 which is already in r16
127 */
128 srdi r15,r16,60 /* get region */
129 cmpldi cr0,r15,0xc /* linear mapping ? */
130 TLB_MISS_STATS_SAVE_INFO
131 beq tlb_load_linear /* yes -> go to linear map load */
132
133 /* We do the user/kernel test for the PID here along with the RW test
134 */
135 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
136 oris r11,r11,_PAGE_ACCESSED@h
137
138 cmpldi cr0,r15,0 /* Check for user region */
139 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
140 beq normal_tlb_miss
141 /* XXX replace the RMW cycles with immediate loads + writes */
1421: mfspr r10,SPRN_MAS1
143 cmpldi cr0,r15,8 /* Check for vmalloc region */
144 rlwinm r10,r10,0,16,1 /* Clear TID */
145 mtspr SPRN_MAS1,r10
146 beq+ normal_tlb_miss
147
148 /* We got a crappy address, just fault */
149 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
150 TLB_MISS_EPILOG_ERROR
151 b exc_instruction_storage_book3e
152
153/*
154 * This is the guts of the first-level TLB miss handler for direct
155 * misses. We are entered with:
156 *
157 * r16 = faulting address
158 * r15 = region ID
159 * r14 = crap (free to use)
160 * r13 = PACA
161 * r12 = TLB exception frame in PACA
162 * r11 = PTE permission mask
163 * r10 = crap (free to use)
164 */
165normal_tlb_miss:
166 /* So we first construct the page table address. We do that by
167 * shifting the bottom of the address (not the region ID) by
168 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
169 * or'ing the fourth high bit.
170 *
171 * NOTE: For 64K pages, we do things slightly differently in
172 * order to handle the weird page table format used by linux
173 */
174 ori r10,r15,0x1
175#ifdef CONFIG_PPC_64K_PAGES
176 /* For the top bits, 16 bytes per PTE */
177 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
178 /* Now create the bottom bits as 0 in position 0x8000 and
179 * the rest calculated for 8 bytes per PTE
180 */
181 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
182 /* Insert the bottom bits in */
183 rlwimi r14,r15,0,16,31
184#else
185 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
186#endif
187 sldi r15,r10,60
188 clrrdi r14,r14,3
189 or r10,r15,r14
190
191BEGIN_MMU_FTR_SECTION
192 /* Set the TLB reservation and seach for existing entry. Then load
193 * the entry.
194 */
195 PPC_TLBSRX_DOT(0,r16)
196 ld r14,0(r10)
197 beq normal_tlb_miss_done
198MMU_FTR_SECTION_ELSE
199 ld r14,0(r10)
200ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
201
202finish_normal_tlb_miss:
203 /* Check if required permissions are met */
204 andc. r15,r11,r14
205 bne- normal_tlb_miss_access_fault
206
207 /* Now we build the MAS:
208 *
209 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
210 * MAS 1 : Almost fully setup
211 * - PID already updated by caller if necessary
212 * - TSIZE need change if !base page size, not
213 * yet implemented for now
214 * MAS 2 : Defaults not useful, need to be redone
215 * MAS 3+7 : Needs to be done
216 *
217 * TODO: mix up code below for better scheduling
218 */
219 clrrdi r11,r16,12 /* Clear low crap in EA */
220 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
221 mtspr SPRN_MAS2,r11
222
223 /* Check page size, if not standard, update MAS1 */
224 rldicl r11,r14,64-8,64-8
225#ifdef CONFIG_PPC_64K_PAGES
226 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
227#else
228 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
229#endif
230 beq- 1f
231 mfspr r11,SPRN_MAS1
232 rlwimi r11,r14,31,21,24
233 rlwinm r11,r11,0,21,19
234 mtspr SPRN_MAS1,r11
2351:
236 /* Move RPN in position */
237 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
238 clrldi r15,r11,12 /* Clear crap at the top */
239 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
240 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
241
242 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
243 andi. r11,r14,_PAGE_DIRTY
244 bne 1f
245 li r11,MAS3_SW|MAS3_UW
246 andc r15,r15,r11
2471:
248BEGIN_MMU_FTR_SECTION
249 srdi r16,r15,32
250 mtspr SPRN_MAS3,r15
251 mtspr SPRN_MAS7,r16
252MMU_FTR_SECTION_ELSE
253 mtspr SPRN_MAS7_MAS3,r15
254ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
255
256 tlbwe
257
258normal_tlb_miss_done:
259 /* We don't bother with restoring DEAR or ESR since we know we are
260 * level 0 and just going back to userland. They are only needed
261 * if you are going to take an access fault
262 */
263 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
264 TLB_MISS_EPILOG_SUCCESS
265 rfi
266
267normal_tlb_miss_access_fault:
268 /* We need to check if it was an instruction miss */
269 andi. r10,r11,_PAGE_EXEC
270 bne 1f
271 ld r14,EX_TLB_DEAR(r12)
272 ld r15,EX_TLB_ESR(r12)
273 mtspr SPRN_DEAR,r14
274 mtspr SPRN_ESR,r15
275 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
276 TLB_MISS_EPILOG_ERROR
277 b exc_data_storage_book3e
2781: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
279 TLB_MISS_EPILOG_ERROR
280 b exc_instruction_storage_book3e
281
282
283/*
284 * This is the guts of the second-level TLB miss handler for direct
285 * misses. We are entered with:
286 *
287 * r16 = virtual page table faulting address
288 * r15 = region (top 4 bits of address)
289 * r14 = crap (free to use)
290 * r13 = PACA
291 * r12 = TLB exception frame in PACA
292 * r11 = crap (free to use)
293 * r10 = crap (free to use)
294 *
295 * Note that this should only ever be called as a second level handler
296 * with the current scheme when using SW load.
297 * That means we can always get the original fault DEAR at
298 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
299 *
300 * It can be re-entered by the linear mapping miss handler. However, to
301 * avoid too much complication, it will restart the whole fault at level
302 * 0 so we don't care too much about clobbers
303 *
304 * XXX That code was written back when we couldn't clobber r14. We can now,
305 * so we could probably optimize things a bit
306 */
307virt_page_table_tlb_miss:
308 /* Are we hitting a kernel page table ? */
309 andi. r10,r15,0x8
310
311 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
312 * and we happen to have the swapper_pg_dir at offset 8 from the user
313 * pgdir in the PACA :-).
314 */
315 add r11,r10,r13
316
317 /* If kernel, we need to clear MAS1 TID */
318 beq 1f
319 /* XXX replace the RMW cycles with immediate loads + writes */
320 mfspr r10,SPRN_MAS1
321 rlwinm r10,r10,0,16,1 /* Clear TID */
322 mtspr SPRN_MAS1,r10
3231:
324BEGIN_MMU_FTR_SECTION
325 /* Search if we already have a TLB entry for that virtual address, and
326 * if we do, bail out.
327 */
328 PPC_TLBSRX_DOT(0,r16)
329 beq virt_page_table_tlb_miss_done
330END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
331
332 /* Now, we need to walk the page tables. First check if we are in
333 * range.
334 */
335 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
336 bne- virt_page_table_tlb_miss_fault
337
338 /* Get the PGD pointer */
339 ld r15,PACAPGD(r11)
340 cmpldi cr0,r15,0
341 beq- virt_page_table_tlb_miss_fault
342
343 /* Get to PGD entry */
344 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
345 clrrdi r10,r11,3
346 ldx r15,r10,r15
347 cmpldi cr0,r15,0
348 beq virt_page_table_tlb_miss_fault
349
350#ifndef CONFIG_PPC_64K_PAGES
351 /* Get to PUD entry */
352 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
353 clrrdi r10,r11,3
354 ldx r15,r10,r15
355 cmpldi cr0,r15,0
356 beq virt_page_table_tlb_miss_fault
357#endif /* CONFIG_PPC_64K_PAGES */
358
359 /* Get to PMD entry */
360 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
361 clrrdi r10,r11,3
362 ldx r15,r10,r15
363 cmpldi cr0,r15,0
364 beq virt_page_table_tlb_miss_fault
365
366 /* Ok, we're all right, we can now create a kernel translation for
367 * a 4K or 64K page from r16 -> r15.
368 */
369 /* Now we build the MAS:
370 *
371 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
372 * MAS 1 : Almost fully setup
373 * - PID already updated by caller if necessary
374 * - TSIZE for now is base page size always
375 * MAS 2 : Use defaults
376 * MAS 3+7 : Needs to be done
377 *
378 * So we only do MAS 2 and 3 for now...
379 */
380 clrldi r11,r15,4 /* remove region ID from RPN */
381 ori r10,r11,1 /* Or-in SR */
382
383BEGIN_MMU_FTR_SECTION
384 srdi r16,r10,32
385 mtspr SPRN_MAS3,r10
386 mtspr SPRN_MAS7,r16
387MMU_FTR_SECTION_ELSE
388 mtspr SPRN_MAS7_MAS3,r10
389ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
390
391 tlbwe
392
393BEGIN_MMU_FTR_SECTION
394virt_page_table_tlb_miss_done:
395
396 /* We have overriden MAS2:EPN but currently our primary TLB miss
397 * handler will always restore it so that should not be an issue,
398 * if we ever optimize the primary handler to not write MAS2 on
399 * some cases, we'll have to restore MAS2:EPN here based on the
400 * original fault's DEAR. If we do that we have to modify the
401 * ITLB miss handler to also store SRR0 in the exception frame
402 * as DEAR.
403 *
404 * However, one nasty thing we did is we cleared the reservation
405 * (well, potentially we did). We do a trick here thus if we
406 * are not a level 0 exception (we interrupted the TLB miss) we
407 * offset the return address by -4 in order to replay the tlbsrx
408 * instruction there
409 */
410 subf r10,r13,r12
411 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
412 bne- 1f
413 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
414 addi r10,r11,-4
415 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
4161:
417END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
418 /* Return to caller, normal case */
419 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
420 TLB_MISS_EPILOG_SUCCESS
421 rfi
422
423virt_page_table_tlb_miss_fault:
424 /* If we fault here, things are a little bit tricky. We need to call
425 * either data or instruction store fault, and we need to retreive
426 * the original fault address and ESR (for data).
427 *
428 * The thing is, we know that in normal circumstances, this is
429 * always called as a second level tlb miss for SW load or as a first
430 * level TLB miss for HW load, so we should be able to peek at the
431 * relevant informations in the first exception frame in the PACA.
432 *
433 * However, we do need to double check that, because we may just hit
434 * a stray kernel pointer or a userland attack trying to hit those
435 * areas. If that is the case, we do a data fault. (We can't get here
436 * from an instruction tlb miss anyway).
437 *
438 * Note also that when going to a fault, we must unwind the previous
439 * level as well. Since we are doing that, we don't need to clear or
440 * restore the TLB reservation neither.
441 */
442 subf r10,r13,r12
443 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
444 bne- virt_page_table_tlb_miss_whacko_fault
445
446 /* We dig the original DEAR and ESR from slot 0 */
447 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
448 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
449
450 /* We check for the "special" ESR value for instruction faults */
451 cmpdi cr0,r16,-1
452 beq 1f
453 mtspr SPRN_DEAR,r15
454 mtspr SPRN_ESR,r16
455 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
456 TLB_MISS_EPILOG_ERROR
457 b exc_data_storage_book3e
4581: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
459 TLB_MISS_EPILOG_ERROR
460 b exc_instruction_storage_book3e
461
462virt_page_table_tlb_miss_whacko_fault:
463 /* The linear fault will restart everything so ESR and DEAR will
464 * not have been clobbered, let's just fault with what we have
465 */
466 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
467 TLB_MISS_EPILOG_ERROR
468 b exc_data_storage_book3e
469
470
471/**************************************************************
472 * *
473 * TLB miss handling for Book3E with hw page table support *
474 * *
475 **************************************************************/
476
477
478/* Data TLB miss */
479 START_EXCEPTION(data_tlb_miss_htw)
480 TLB_MISS_PROLOG
481
482 /* Now we handle the fault proper. We only save DEAR in normal
483 * fault case since that's the only interesting values here.
484 * We could probably also optimize by not saving SRR0/1 in the
485 * linear mapping case but I'll leave that for later
486 */
487 mfspr r14,SPRN_ESR
488 mfspr r16,SPRN_DEAR /* get faulting address */
489 srdi r11,r16,60 /* get region */
490 cmpldi cr0,r11,0xc /* linear mapping ? */
491 TLB_MISS_STATS_SAVE_INFO
492 beq tlb_load_linear /* yes -> go to linear map load */
493
494 /* We do the user/kernel test for the PID here along with the RW test
495 */
496 cmpldi cr0,r11,0 /* Check for user region */
497 ld r15,PACAPGD(r13) /* Load user pgdir */
498 beq htw_tlb_miss
499
500 /* XXX replace the RMW cycles with immediate loads + writes */
5011: mfspr r10,SPRN_MAS1
502 cmpldi cr0,r11,8 /* Check for vmalloc region */
503 rlwinm r10,r10,0,16,1 /* Clear TID */
504 mtspr SPRN_MAS1,r10
505 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
506 beq+ htw_tlb_miss
507
508 /* We got a crappy address, just fault with whatever DEAR and ESR
509 * are here
510 */
511 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
512 TLB_MISS_EPILOG_ERROR
513 b exc_data_storage_book3e
514
515/* Instruction TLB miss */
516 START_EXCEPTION(instruction_tlb_miss_htw)
517 TLB_MISS_PROLOG
518
519 /* If we take a recursive fault, the second level handler may need
520 * to know whether we are handling a data or instruction fault in
521 * order to get to the right store fault handler. We provide that
522 * info by keeping a crazy value for ESR in r14
523 */
524 li r14,-1 /* store to exception frame is done later */
525
526 /* Now we handle the fault proper. We only save DEAR in the non
527 * linear mapping case since we know the linear mapping case will
528 * not re-enter. We could indeed optimize and also not save SRR0/1
529 * in the linear mapping case but I'll leave that for later
530 *
531 * Faulting address is SRR0 which is already in r16
532 */
533 srdi r11,r16,60 /* get region */
534 cmpldi cr0,r11,0xc /* linear mapping ? */
535 TLB_MISS_STATS_SAVE_INFO
536 beq tlb_load_linear /* yes -> go to linear map load */
537
538 /* We do the user/kernel test for the PID here along with the RW test
539 */
540 cmpldi cr0,r11,0 /* Check for user region */
541 ld r15,PACAPGD(r13) /* Load user pgdir */
542 beq htw_tlb_miss
543
544 /* XXX replace the RMW cycles with immediate loads + writes */
5451: mfspr r10,SPRN_MAS1
546 cmpldi cr0,r11,8 /* Check for vmalloc region */
547 rlwinm r10,r10,0,16,1 /* Clear TID */
548 mtspr SPRN_MAS1,r10
549 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
550 beq+ htw_tlb_miss
551
552 /* We got a crappy address, just fault */
553 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
554 TLB_MISS_EPILOG_ERROR
555 b exc_instruction_storage_book3e
556
557
558/*
559 * This is the guts of the second-level TLB miss handler for direct
560 * misses. We are entered with:
561 *
562 * r16 = virtual page table faulting address
563 * r15 = PGD pointer
564 * r14 = ESR
565 * r13 = PACA
566 * r12 = TLB exception frame in PACA
567 * r11 = crap (free to use)
568 * r10 = crap (free to use)
569 *
570 * It can be re-entered by the linear mapping miss handler. However, to
571 * avoid too much complication, it will save/restore things for us
572 */
573htw_tlb_miss:
574 /* Search if we already have a TLB entry for that virtual address, and
575 * if we do, bail out.
576 *
577 * MAS1:IND should be already set based on MAS4
578 */
579 PPC_TLBSRX_DOT(0,r16)
580 beq htw_tlb_miss_done
581
582 /* Now, we need to walk the page tables. First check if we are in
583 * range.
584 */
585 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
586 bne- htw_tlb_miss_fault
587
588 /* Get the PGD pointer */
589 cmpldi cr0,r15,0
590 beq- htw_tlb_miss_fault
591
592 /* Get to PGD entry */
593 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
594 clrrdi r10,r11,3
595 ldx r15,r10,r15
596 cmpldi cr0,r15,0
597 beq htw_tlb_miss_fault
598
599#ifndef CONFIG_PPC_64K_PAGES
600 /* Get to PUD entry */
601 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
602 clrrdi r10,r11,3
603 ldx r15,r10,r15
604 cmpldi cr0,r15,0
605 beq htw_tlb_miss_fault
606#endif /* CONFIG_PPC_64K_PAGES */
607
608 /* Get to PMD entry */
609 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
610 clrrdi r10,r11,3
611 ldx r15,r10,r15
612 cmpldi cr0,r15,0
613 beq htw_tlb_miss_fault
614
615 /* Ok, we're all right, we can now create an indirect entry for
616 * a 1M or 256M page.
617 *
618 * The last trick is now that because we use "half" pages for
619 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
620 * for an added LSB bit to the RPN. For 64K pages, there is no
621 * problem as we already use 32K arrays (half PTE pages), but for
622 * 4K page we need to extract a bit from the virtual address and
623 * insert it into the "PA52" bit of the RPN.
624 */
625#ifndef CONFIG_PPC_64K_PAGES
626 rlwimi r15,r16,32-9,20,20
627#endif
628 /* Now we build the MAS:
629 *
630 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
631 * MAS 1 : Almost fully setup
632 * - PID already updated by caller if necessary
633 * - TSIZE for now is base ind page size always
634 * MAS 2 : Use defaults
635 * MAS 3+7 : Needs to be done
636 */
637#ifdef CONFIG_PPC_64K_PAGES
638 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
639#else
640 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
641#endif
642
643BEGIN_MMU_FTR_SECTION
644 srdi r16,r10,32
645 mtspr SPRN_MAS3,r10
646 mtspr SPRN_MAS7,r16
647MMU_FTR_SECTION_ELSE
648 mtspr SPRN_MAS7_MAS3,r10
649ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
650
651 tlbwe
652
653htw_tlb_miss_done:
654 /* We don't bother with restoring DEAR or ESR since we know we are
655 * level 0 and just going back to userland. They are only needed
656 * if you are going to take an access fault
657 */
658 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
659 TLB_MISS_EPILOG_SUCCESS
660 rfi
661
662htw_tlb_miss_fault:
663 /* We need to check if it was an instruction miss. We know this
664 * though because r14 would contain -1
665 */
666 cmpdi cr0,r14,-1
667 beq 1f
668 mtspr SPRN_DEAR,r16
669 mtspr SPRN_ESR,r14
670 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
671 TLB_MISS_EPILOG_ERROR
672 b exc_data_storage_book3e
6731: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
674 TLB_MISS_EPILOG_ERROR
675 b exc_instruction_storage_book3e
676
677/*
678 * This is the guts of "any" level TLB miss handler for kernel linear
679 * mapping misses. We are entered with:
680 *
681 *
682 * r16 = faulting address
683 * r15 = crap (free to use)
684 * r14 = ESR (data) or -1 (instruction)
685 * r13 = PACA
686 * r12 = TLB exception frame in PACA
687 * r11 = crap (free to use)
688 * r10 = crap (free to use)
689 *
690 * In addition we know that we will not re-enter, so in theory, we could
691 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
692 *
693 * We also need to be careful about MAS registers here & TLB reservation,
694 * as we know we'll have clobbered them if we interrupt the main TLB miss
695 * handlers in which case we probably want to do a full restart at level
696 * 0 rather than saving / restoring the MAS.
697 *
698 * Note: If we care about performance of that core, we can easily shuffle
699 * a few things around
700 */
701tlb_load_linear:
702 /* For now, we assume the linear mapping is contiguous and stops at
703 * linear_map_top. We also assume the size is a multiple of 1G, thus
704 * we only use 1G pages for now. That might have to be changed in a
705 * final implementation, especially when dealing with hypervisors
706 */
707 ld r11,PACATOC(r13)
708 ld r11,linear_map_top@got(r11)
709 ld r10,0(r11)
710 cmpld cr0,r10,r16
711 bge tlb_load_linear_fault
712
713 /* MAS1 need whole new setup. */
714 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
715 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
716 mtspr SPRN_MAS1,r15
717
718 /* Already somebody there ? */
719 PPC_TLBSRX_DOT(0,r16)
720 beq tlb_load_linear_done
721
722 /* Now we build the remaining MAS. MAS0 and 2 should be fine
723 * with their defaults, which leaves us with MAS 3 and 7. The
724 * mapping is linear, so we just take the address, clear the
725 * region bits, and or in the permission bits which are currently
726 * hard wired
727 */
728 clrrdi r10,r16,30 /* 1G page index */
729 clrldi r10,r10,4 /* clear region bits */
730 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
731
732BEGIN_MMU_FTR_SECTION
733 srdi r16,r10,32
734 mtspr SPRN_MAS3,r10
735 mtspr SPRN_MAS7,r16
736MMU_FTR_SECTION_ELSE
737 mtspr SPRN_MAS7_MAS3,r10
738ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
739
740 tlbwe
741
742tlb_load_linear_done:
743 /* We use the "error" epilog for success as we do want to
744 * restore to the initial faulting context, whatever it was.
745 * We do that because we can't resume a fault within a TLB
746 * miss handler, due to MAS and TLB reservation being clobbered.
747 */
748 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
749 TLB_MISS_EPILOG_ERROR
750 rfi
751
752tlb_load_linear_fault:
753 /* We keep the DEAR and ESR around, this shouldn't have happened */
754 cmpdi cr0,r14,-1
755 beq 1f
756 TLB_MISS_EPILOG_ERROR_SPECIAL
757 b exc_data_storage_book3e
7581: TLB_MISS_EPILOG_ERROR_SPECIAL
759 b exc_instruction_storage_book3e
760
761
762#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
763.tlb_stat_inc:
7641: ldarx r8,0,r9
765 addi r8,r8,1
766 stdcx. r8,0,r9
767 bne- 1b
768 blr
769#endif