tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
17/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
23#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24#define BCM_VLAN 1
25#endif
26
27#define BNX2X_MULTI_QUEUE
28
29#define BNX2X_NEW_NAPI
30
31
32
33#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
34#define BCM_CNIC 1
35#include "cnic_if.h"
36#endif
37
38
39#ifdef BCM_CNIC
40#define BNX2X_MIN_MSIX_VEC_CNT 3
41#define BNX2X_MSIX_VEC_FP_START 2
42#else
43#define BNX2X_MIN_MSIX_VEC_CNT 2
44#define BNX2X_MSIX_VEC_FP_START 1
45#endif
46
47#include <linux/mdio.h>
48#include "bnx2x_reg.h"
49#include "bnx2x_fw_defs.h"
50#include "bnx2x_hsi.h"
51#include "bnx2x_link.h"
52
53/* error/debug prints */
54
55#define DRV_MODULE_NAME "bnx2x"
56
57/* for messages that are currently off */
58#define BNX2X_MSG_OFF 0
59#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
60#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
61#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
62#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
63#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
64#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
65
66#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
67
68/* regular debug print */
69#define DP(__mask, __fmt, __args...) \
70do { \
71 if (bp->msg_enable & (__mask)) \
72 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
73 __func__, __LINE__, \
74 bp->dev ? (bp->dev->name) : "?", \
75 ##__args); \
76} while (0)
77
78/* errors debug print */
79#define BNX2X_DBG_ERR(__fmt, __args...) \
80do { \
81 if (netif_msg_probe(bp)) \
82 pr_err("[%s:%d(%s)]" __fmt, \
83 __func__, __LINE__, \
84 bp->dev ? (bp->dev->name) : "?", \
85 ##__args); \
86} while (0)
87
88/* for errors (never masked) */
89#define BNX2X_ERR(__fmt, __args...) \
90do { \
91 pr_err("[%s:%d(%s)]" __fmt, \
92 __func__, __LINE__, \
93 bp->dev ? (bp->dev->name) : "?", \
94 ##__args); \
95 } while (0)
96
97#define BNX2X_ERROR(__fmt, __args...) do { \
98 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
99 } while (0)
100
101
102/* before we have a dev->name use dev_info() */
103#define BNX2X_DEV_INFO(__fmt, __args...) \
104do { \
105 if (netif_msg_probe(bp)) \
106 dev_info(&bp->pdev->dev, __fmt, ##__args); \
107} while (0)
108
109
110#ifdef BNX2X_STOP_ON_ERROR
111#define bnx2x_panic() do { \
112 bp->panic = 1; \
113 BNX2X_ERR("driver assert\n"); \
114 bnx2x_int_disable(bp); \
115 bnx2x_panic_dump(bp); \
116 } while (0)
117#else
118#define bnx2x_panic() do { \
119 bp->panic = 1; \
120 BNX2X_ERR("driver assert\n"); \
121 bnx2x_panic_dump(bp); \
122 } while (0)
123#endif
124
125
126#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
127#define U64_HI(x) (u32)(((u64)(x)) >> 32)
128#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
129
130
131#define REG_ADDR(bp, offset) (bp->regview + offset)
132
133#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
134#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
135
136#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
137#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
138#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
139
140#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
141#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
142
143#define REG_RD_DMAE(bp, offset, valp, len32) \
144 do { \
145 bnx2x_read_dmae(bp, offset, len32);\
146 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
147 } while (0)
148
149#define REG_WR_DMAE(bp, offset, valp, len32) \
150 do { \
151 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
152 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
153 offset, len32); \
154 } while (0)
155
156#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
157 do { \
158 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
159 bnx2x_write_big_buf_wb(bp, addr, len32); \
160 } while (0)
161
162#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
163 offsetof(struct shmem_region, field))
164#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
165#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
166
167#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
168 offsetof(struct shmem2_region, field))
169#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
170#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
171
172#define MF_CFG_RD(bp, field) SHMEM_RD(bp, mf_cfg.field)
173#define MF_CFG_WR(bp, field, val) SHMEM_WR(bp, mf_cfg.field, val)
174
175#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
176#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
177
178#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
179 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
180
181
182/* fast path */
183
184struct sw_rx_bd {
185 struct sk_buff *skb;
186 DEFINE_DMA_UNMAP_ADDR(mapping);
187};
188
189struct sw_tx_bd {
190 struct sk_buff *skb;
191 u16 first_bd;
192 u8 flags;
193/* Set on the first BD descriptor when there is a split BD */
194#define BNX2X_TSO_SPLIT_BD (1<<0)
195};
196
197struct sw_rx_page {
198 struct page *page;
199 DEFINE_DMA_UNMAP_ADDR(mapping);
200};
201
202union db_prod {
203 struct doorbell_set_prod data;
204 u32 raw;
205};
206
207
208/* MC hsi */
209#define BCM_PAGE_SHIFT 12
210#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
211#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
212#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
213
214#define PAGES_PER_SGE_SHIFT 0
215#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
216#define SGE_PAGE_SIZE PAGE_SIZE
217#define SGE_PAGE_SHIFT PAGE_SHIFT
218#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
219
220/* SGE ring related macros */
221#define NUM_RX_SGE_PAGES 2
222#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
223#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
224/* RX_SGE_CNT is promised to be a power of 2 */
225#define RX_SGE_MASK (RX_SGE_CNT - 1)
226#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
227#define MAX_RX_SGE (NUM_RX_SGE - 1)
228#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
229 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
230#define RX_SGE(x) ((x) & MAX_RX_SGE)
231
232/* SGE producer mask related macros */
233/* Number of bits in one sge_mask array element */
234#define RX_SGE_MASK_ELEM_SZ 64
235#define RX_SGE_MASK_ELEM_SHIFT 6
236#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
237
238/* Creates a bitmask of all ones in less significant bits.
239 idx - index of the most significant bit in the created mask */
240#define RX_SGE_ONES_MASK(idx) \
241 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
242#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
243
244/* Number of u64 elements in SGE mask array */
245#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
246 RX_SGE_MASK_ELEM_SZ)
247#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
248#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
249
250
251struct bnx2x_eth_q_stats {
252 u32 total_bytes_received_hi;
253 u32 total_bytes_received_lo;
254 u32 total_bytes_transmitted_hi;
255 u32 total_bytes_transmitted_lo;
256 u32 total_unicast_packets_received_hi;
257 u32 total_unicast_packets_received_lo;
258 u32 total_multicast_packets_received_hi;
259 u32 total_multicast_packets_received_lo;
260 u32 total_broadcast_packets_received_hi;
261 u32 total_broadcast_packets_received_lo;
262 u32 total_unicast_packets_transmitted_hi;
263 u32 total_unicast_packets_transmitted_lo;
264 u32 total_multicast_packets_transmitted_hi;
265 u32 total_multicast_packets_transmitted_lo;
266 u32 total_broadcast_packets_transmitted_hi;
267 u32 total_broadcast_packets_transmitted_lo;
268 u32 valid_bytes_received_hi;
269 u32 valid_bytes_received_lo;
270
271 u32 error_bytes_received_hi;
272 u32 error_bytes_received_lo;
273 u32 etherstatsoverrsizepkts_hi;
274 u32 etherstatsoverrsizepkts_lo;
275 u32 no_buff_discard_hi;
276 u32 no_buff_discard_lo;
277
278 u32 driver_xoff;
279 u32 rx_err_discard_pkt;
280 u32 rx_skb_alloc_failed;
281 u32 hw_csum_err;
282};
283
284#define BNX2X_NUM_Q_STATS 13
285#define Q_STATS_OFFSET32(stat_name) \
286 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
287
288struct bnx2x_fastpath {
289
290 struct napi_struct napi;
291 struct host_status_block *status_blk;
292 dma_addr_t status_blk_mapping;
293
294 struct sw_tx_bd *tx_buf_ring;
295
296 union eth_tx_bd_types *tx_desc_ring;
297 dma_addr_t tx_desc_mapping;
298
299 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
300 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
301
302 struct eth_rx_bd *rx_desc_ring;
303 dma_addr_t rx_desc_mapping;
304
305 union eth_rx_cqe *rx_comp_ring;
306 dma_addr_t rx_comp_mapping;
307
308 /* SGE ring */
309 struct eth_rx_sge *rx_sge_ring;
310 dma_addr_t rx_sge_mapping;
311
312 u64 sge_mask[RX_SGE_MASK_LEN];
313
314 int state;
315#define BNX2X_FP_STATE_CLOSED 0
316#define BNX2X_FP_STATE_IRQ 0x80000
317#define BNX2X_FP_STATE_OPENING 0x90000
318#define BNX2X_FP_STATE_OPEN 0xa0000
319#define BNX2X_FP_STATE_HALTING 0xb0000
320#define BNX2X_FP_STATE_HALTED 0xc0000
321
322 u8 index; /* number in fp array */
323 u8 cl_id; /* eth client id */
324 u8 sb_id; /* status block number in HW */
325
326 union db_prod tx_db;
327
328 u16 tx_pkt_prod;
329 u16 tx_pkt_cons;
330 u16 tx_bd_prod;
331 u16 tx_bd_cons;
332 __le16 *tx_cons_sb;
333
334 __le16 fp_c_idx;
335 __le16 fp_u_idx;
336
337 u16 rx_bd_prod;
338 u16 rx_bd_cons;
339 u16 rx_comp_prod;
340 u16 rx_comp_cons;
341 u16 rx_sge_prod;
342 /* The last maximal completed SGE */
343 u16 last_max_sge;
344 __le16 *rx_cons_sb;
345 __le16 *rx_bd_cons_sb;
346
347
348 unsigned long tx_pkt,
349 rx_pkt,
350 rx_calls;
351
352 /* TPA related */
353 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
354 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
355#define BNX2X_TPA_START 1
356#define BNX2X_TPA_STOP 2
357 u8 disable_tpa;
358#ifdef BNX2X_STOP_ON_ERROR
359 u64 tpa_queue_used;
360#endif
361
362 struct tstorm_per_client_stats old_tclient;
363 struct ustorm_per_client_stats old_uclient;
364 struct xstorm_per_client_stats old_xclient;
365 struct bnx2x_eth_q_stats eth_q_stats;
366
367 /* The size is calculated using the following:
368 sizeof name field from netdev structure +
369 4 ('-Xx-' string) +
370 4 (for the digits and to make it DWORD aligned) */
371#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
372 char name[FP_NAME_SIZE];
373 struct bnx2x *bp; /* parent */
374};
375
376#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
377
378
379/* MC hsi */
380#define MAX_FETCH_BD 13 /* HW max BDs per packet */
381#define RX_COPY_THRESH 92
382
383#define NUM_TX_RINGS 16
384#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
385#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
386#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
387#define MAX_TX_BD (NUM_TX_BD - 1)
388#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
389#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
390 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
391#define TX_BD(x) ((x) & MAX_TX_BD)
392#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
393
394/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
395#define NUM_RX_RINGS 8
396#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
397#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
398#define RX_DESC_MASK (RX_DESC_CNT - 1)
399#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
400#define MAX_RX_BD (NUM_RX_BD - 1)
401#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
402#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
403 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
404#define RX_BD(x) ((x) & MAX_RX_BD)
405
406/* As long as CQE is 4 times bigger than BD entry we have to allocate
407 4 times more pages for CQ ring in order to keep it balanced with
408 BD ring */
409#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
410#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
411#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
412#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
413#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
414#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
415#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
416 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
417#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
418
419
420/* This is needed for determining of last_max */
421#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
422
423#define __SGE_MASK_SET_BIT(el, bit) \
424 do { \
425 el = ((el) | ((u64)0x1 << (bit))); \
426 } while (0)
427
428#define __SGE_MASK_CLEAR_BIT(el, bit) \
429 do { \
430 el = ((el) & (~((u64)0x1 << (bit)))); \
431 } while (0)
432
433#define SGE_MASK_SET_BIT(fp, idx) \
434 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
435 ((idx) & RX_SGE_MASK_ELEM_MASK))
436
437#define SGE_MASK_CLEAR_BIT(fp, idx) \
438 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
439 ((idx) & RX_SGE_MASK_ELEM_MASK))
440
441
442/* used on a CID received from the HW */
443#define SW_CID(x) (le32_to_cpu(x) & \
444 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
445#define CQE_CMD(x) (le32_to_cpu(x) >> \
446 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
447
448#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
449 le32_to_cpu((bd)->addr_lo))
450#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
451
452
453#define DPM_TRIGER_TYPE 0x40
454#define DOORBELL(bp, cid, val) \
455 do { \
456 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
457 DPM_TRIGER_TYPE); \
458 } while (0)
459
460
461/* TX CSUM helpers */
462#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
463 skb->csum_offset)
464#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
465 skb->csum_offset))
466
467#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
468
469#define XMIT_PLAIN 0
470#define XMIT_CSUM_V4 0x1
471#define XMIT_CSUM_V6 0x2
472#define XMIT_CSUM_TCP 0x4
473#define XMIT_GSO_V4 0x8
474#define XMIT_GSO_V6 0x10
475
476#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
477#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
478
479
480/* stuff added to make the code fit 80Col */
481
482#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
483
484#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
485#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
486#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
487 (TPA_TYPE_START | TPA_TYPE_END))
488
489#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
490
491#define BNX2X_IP_CSUM_ERR(cqe) \
492 (!((cqe)->fast_path_cqe.status_flags & \
493 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
494 ((cqe)->fast_path_cqe.type_error_flags & \
495 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
496
497#define BNX2X_L4_CSUM_ERR(cqe) \
498 (!((cqe)->fast_path_cqe.status_flags & \
499 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
500 ((cqe)->fast_path_cqe.type_error_flags & \
501 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
502
503#define BNX2X_RX_CSUM_OK(cqe) \
504 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
505
506#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
507 (((le16_to_cpu(flags) & \
508 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
509 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
510 == PRS_FLAG_OVERETH_IPV4)
511#define BNX2X_RX_SUM_FIX(cqe) \
512 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
513
514
515#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
516#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
517
518#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
519#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
520#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
521
522#define BNX2X_RX_SB_INDEX \
523 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
524
525#define BNX2X_RX_SB_BD_INDEX \
526 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
527
528#define BNX2X_RX_SB_INDEX_NUM \
529 (((U_SB_ETH_RX_CQ_INDEX << \
530 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
531 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
532 ((U_SB_ETH_RX_BD_INDEX << \
533 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
534 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
535
536#define BNX2X_TX_SB_INDEX \
537 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
538
539
540/* end of fast path */
541
542/* common */
543
544struct bnx2x_common {
545
546 u32 chip_id;
547/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
548#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
549
550#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
551#define CHIP_NUM_57710 0x164e
552#define CHIP_NUM_57711 0x164f
553#define CHIP_NUM_57711E 0x1650
554#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
555#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
556#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
557#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
558 CHIP_IS_57711E(bp))
559#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
560
561#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
562#define CHIP_REV_Ax 0x00000000
563/* assume maximum 5 revisions */
564#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
565/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
566#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
567 !(CHIP_REV(bp) & 0x00001000))
568/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
569#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
570 (CHIP_REV(bp) & 0x00001000))
571
572#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
573 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
574
575#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
576#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
577
578 int flash_size;
579#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
580#define NVRAM_TIMEOUT_COUNT 30000
581#define NVRAM_PAGE_SIZE 256
582
583 u32 shmem_base;
584 u32 shmem2_base;
585
586 u32 hw_config;
587
588 u32 bc_ver;
589};
590
591
592/* end of common */
593
594/* port */
595
596struct nig_stats {
597 u32 brb_discard;
598 u32 brb_packet;
599 u32 brb_truncate;
600 u32 flow_ctrl_discard;
601 u32 flow_ctrl_octets;
602 u32 flow_ctrl_packet;
603 u32 mng_discard;
604 u32 mng_octet_inp;
605 u32 mng_octet_out;
606 u32 mng_packet_inp;
607 u32 mng_packet_out;
608 u32 pbf_octets;
609 u32 pbf_packet;
610 u32 safc_inp;
611 u32 egress_mac_pkt0_lo;
612 u32 egress_mac_pkt0_hi;
613 u32 egress_mac_pkt1_lo;
614 u32 egress_mac_pkt1_hi;
615};
616
617struct bnx2x_port {
618 u32 pmf;
619
620 u32 link_config;
621
622 u32 supported;
623/* link settings - missing defines */
624#define SUPPORTED_2500baseX_Full (1 << 15)
625
626 u32 advertising;
627/* link settings - missing defines */
628#define ADVERTISED_2500baseX_Full (1 << 15)
629
630 u32 phy_addr;
631
632 /* used to synchronize phy accesses */
633 struct mutex phy_mutex;
634 int need_hw_lock;
635
636 u32 port_stx;
637
638 struct nig_stats old_nig_stats;
639};
640
641/* end of port */
642
643
644enum bnx2x_stats_event {
645 STATS_EVENT_PMF = 0,
646 STATS_EVENT_LINK_UP,
647 STATS_EVENT_UPDATE,
648 STATS_EVENT_STOP,
649 STATS_EVENT_MAX
650};
651
652enum bnx2x_stats_state {
653 STATS_STATE_DISABLED = 0,
654 STATS_STATE_ENABLED,
655 STATS_STATE_MAX
656};
657
658struct bnx2x_eth_stats {
659 u32 total_bytes_received_hi;
660 u32 total_bytes_received_lo;
661 u32 total_bytes_transmitted_hi;
662 u32 total_bytes_transmitted_lo;
663 u32 total_unicast_packets_received_hi;
664 u32 total_unicast_packets_received_lo;
665 u32 total_multicast_packets_received_hi;
666 u32 total_multicast_packets_received_lo;
667 u32 total_broadcast_packets_received_hi;
668 u32 total_broadcast_packets_received_lo;
669 u32 total_unicast_packets_transmitted_hi;
670 u32 total_unicast_packets_transmitted_lo;
671 u32 total_multicast_packets_transmitted_hi;
672 u32 total_multicast_packets_transmitted_lo;
673 u32 total_broadcast_packets_transmitted_hi;
674 u32 total_broadcast_packets_transmitted_lo;
675 u32 valid_bytes_received_hi;
676 u32 valid_bytes_received_lo;
677
678 u32 error_bytes_received_hi;
679 u32 error_bytes_received_lo;
680 u32 etherstatsoverrsizepkts_hi;
681 u32 etherstatsoverrsizepkts_lo;
682 u32 no_buff_discard_hi;
683 u32 no_buff_discard_lo;
684
685 u32 rx_stat_ifhcinbadoctets_hi;
686 u32 rx_stat_ifhcinbadoctets_lo;
687 u32 tx_stat_ifhcoutbadoctets_hi;
688 u32 tx_stat_ifhcoutbadoctets_lo;
689 u32 rx_stat_dot3statsfcserrors_hi;
690 u32 rx_stat_dot3statsfcserrors_lo;
691 u32 rx_stat_dot3statsalignmenterrors_hi;
692 u32 rx_stat_dot3statsalignmenterrors_lo;
693 u32 rx_stat_dot3statscarriersenseerrors_hi;
694 u32 rx_stat_dot3statscarriersenseerrors_lo;
695 u32 rx_stat_falsecarriererrors_hi;
696 u32 rx_stat_falsecarriererrors_lo;
697 u32 rx_stat_etherstatsundersizepkts_hi;
698 u32 rx_stat_etherstatsundersizepkts_lo;
699 u32 rx_stat_dot3statsframestoolong_hi;
700 u32 rx_stat_dot3statsframestoolong_lo;
701 u32 rx_stat_etherstatsfragments_hi;
702 u32 rx_stat_etherstatsfragments_lo;
703 u32 rx_stat_etherstatsjabbers_hi;
704 u32 rx_stat_etherstatsjabbers_lo;
705 u32 rx_stat_maccontrolframesreceived_hi;
706 u32 rx_stat_maccontrolframesreceived_lo;
707 u32 rx_stat_bmac_xpf_hi;
708 u32 rx_stat_bmac_xpf_lo;
709 u32 rx_stat_bmac_xcf_hi;
710 u32 rx_stat_bmac_xcf_lo;
711 u32 rx_stat_xoffstateentered_hi;
712 u32 rx_stat_xoffstateentered_lo;
713 u32 rx_stat_xonpauseframesreceived_hi;
714 u32 rx_stat_xonpauseframesreceived_lo;
715 u32 rx_stat_xoffpauseframesreceived_hi;
716 u32 rx_stat_xoffpauseframesreceived_lo;
717 u32 tx_stat_outxonsent_hi;
718 u32 tx_stat_outxonsent_lo;
719 u32 tx_stat_outxoffsent_hi;
720 u32 tx_stat_outxoffsent_lo;
721 u32 tx_stat_flowcontroldone_hi;
722 u32 tx_stat_flowcontroldone_lo;
723 u32 tx_stat_etherstatscollisions_hi;
724 u32 tx_stat_etherstatscollisions_lo;
725 u32 tx_stat_dot3statssinglecollisionframes_hi;
726 u32 tx_stat_dot3statssinglecollisionframes_lo;
727 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
728 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
729 u32 tx_stat_dot3statsdeferredtransmissions_hi;
730 u32 tx_stat_dot3statsdeferredtransmissions_lo;
731 u32 tx_stat_dot3statsexcessivecollisions_hi;
732 u32 tx_stat_dot3statsexcessivecollisions_lo;
733 u32 tx_stat_dot3statslatecollisions_hi;
734 u32 tx_stat_dot3statslatecollisions_lo;
735 u32 tx_stat_etherstatspkts64octets_hi;
736 u32 tx_stat_etherstatspkts64octets_lo;
737 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
738 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
739 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
740 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
741 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
742 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
743 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
744 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
745 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
746 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
747 u32 tx_stat_etherstatspktsover1522octets_hi;
748 u32 tx_stat_etherstatspktsover1522octets_lo;
749 u32 tx_stat_bmac_2047_hi;
750 u32 tx_stat_bmac_2047_lo;
751 u32 tx_stat_bmac_4095_hi;
752 u32 tx_stat_bmac_4095_lo;
753 u32 tx_stat_bmac_9216_hi;
754 u32 tx_stat_bmac_9216_lo;
755 u32 tx_stat_bmac_16383_hi;
756 u32 tx_stat_bmac_16383_lo;
757 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
758 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
759 u32 tx_stat_bmac_ufl_hi;
760 u32 tx_stat_bmac_ufl_lo;
761
762 u32 pause_frames_received_hi;
763 u32 pause_frames_received_lo;
764 u32 pause_frames_sent_hi;
765 u32 pause_frames_sent_lo;
766
767 u32 etherstatspkts1024octetsto1522octets_hi;
768 u32 etherstatspkts1024octetsto1522octets_lo;
769 u32 etherstatspktsover1522octets_hi;
770 u32 etherstatspktsover1522octets_lo;
771
772 u32 brb_drop_hi;
773 u32 brb_drop_lo;
774 u32 brb_truncate_hi;
775 u32 brb_truncate_lo;
776
777 u32 mac_filter_discard;
778 u32 xxoverflow_discard;
779 u32 brb_truncate_discard;
780 u32 mac_discard;
781
782 u32 driver_xoff;
783 u32 rx_err_discard_pkt;
784 u32 rx_skb_alloc_failed;
785 u32 hw_csum_err;
786
787 u32 nig_timer_max;
788};
789
790#define BNX2X_NUM_STATS 43
791#define STATS_OFFSET32(stat_name) \
792 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
793
794
795#ifdef BCM_CNIC
796#define MAX_CONTEXT 15
797#else
798#define MAX_CONTEXT 16
799#endif
800
801union cdu_context {
802 struct eth_context eth;
803 char pad[1024];
804};
805
806#define MAX_DMAE_C 8
807
808/* DMA memory not used in fastpath */
809struct bnx2x_slowpath {
810 union cdu_context context[MAX_CONTEXT];
811 struct eth_stats_query fw_stats;
812 struct mac_configuration_cmd mac_config;
813 struct mac_configuration_cmd mcast_config;
814
815 /* used by dmae command executer */
816 struct dmae_command dmae[MAX_DMAE_C];
817
818 u32 stats_comp;
819 union mac_stats mac_stats;
820 struct nig_stats nig_stats;
821 struct host_port_stats port_stats;
822 struct host_func_stats func_stats;
823 struct host_func_stats func_stats_base;
824
825 u32 wb_comp;
826 u32 wb_data[4];
827};
828
829#define bnx2x_sp(bp, var) (&bp->slowpath->var)
830#define bnx2x_sp_mapping(bp, var) \
831 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
832
833
834/* attn group wiring */
835#define MAX_DYNAMIC_ATTN_GRPS 8
836
837struct attn_route {
838 u32 sig[4];
839};
840
841typedef enum {
842 BNX2X_RECOVERY_DONE,
843 BNX2X_RECOVERY_INIT,
844 BNX2X_RECOVERY_WAIT,
845} bnx2x_recovery_state_t;
846
847struct bnx2x {
848 /* Fields used in the tx and intr/napi performance paths
849 * are grouped together in the beginning of the structure
850 */
851 struct bnx2x_fastpath fp[MAX_CONTEXT];
852 void __iomem *regview;
853 void __iomem *doorbells;
854#ifdef BCM_CNIC
855#define BNX2X_DB_SIZE (18*BCM_PAGE_SIZE)
856#else
857#define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
858#endif
859
860 struct net_device *dev;
861 struct pci_dev *pdev;
862
863 atomic_t intr_sem;
864
865 bnx2x_recovery_state_t recovery_state;
866 int is_leader;
867#ifdef BCM_CNIC
868 struct msix_entry msix_table[MAX_CONTEXT+2];
869#else
870 struct msix_entry msix_table[MAX_CONTEXT+1];
871#endif
872#define INT_MODE_INTx 1
873#define INT_MODE_MSI 2
874
875 int tx_ring_size;
876
877#ifdef BCM_VLAN
878 struct vlan_group *vlgrp;
879#endif
880
881 u32 rx_csum;
882 u32 rx_buf_size;
883#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
884#define ETH_MIN_PACKET_SIZE 60
885#define ETH_MAX_PACKET_SIZE 1500
886#define ETH_MAX_JUMBO_PACKET_SIZE 9600
887
888 /* Max supported alignment is 256 (8 shift) */
889#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
890 L1_CACHE_SHIFT : 8)
891#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
892
893 struct host_def_status_block *def_status_blk;
894#define DEF_SB_ID 16
895 __le16 def_c_idx;
896 __le16 def_u_idx;
897 __le16 def_x_idx;
898 __le16 def_t_idx;
899 __le16 def_att_idx;
900 u32 attn_state;
901 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
902
903 /* slow path ring */
904 struct eth_spe *spq;
905 dma_addr_t spq_mapping;
906 u16 spq_prod_idx;
907 struct eth_spe *spq_prod_bd;
908 struct eth_spe *spq_last_bd;
909 __le16 *dsb_sp_prod;
910 u16 spq_left; /* serialize spq */
911 /* used to synchronize spq accesses */
912 spinlock_t spq_lock;
913
914 /* Flags for marking that there is a STAT_QUERY or
915 SET_MAC ramrod pending */
916 int stats_pending;
917 int set_mac_pending;
918
919 /* End of fields used in the performance code paths */
920
921 int panic;
922 int msg_enable;
923
924 u32 flags;
925#define PCIX_FLAG 1
926#define PCI_32BIT_FLAG 2
927#define ONE_PORT_FLAG 4
928#define NO_WOL_FLAG 8
929#define USING_DAC_FLAG 0x10
930#define USING_MSIX_FLAG 0x20
931#define USING_MSI_FLAG 0x40
932#define TPA_ENABLE_FLAG 0x80
933#define NO_MCP_FLAG 0x100
934#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
935#define HW_VLAN_TX_FLAG 0x400
936#define HW_VLAN_RX_FLAG 0x800
937#define MF_FUNC_DIS 0x1000
938
939 int func;
940#define BP_PORT(bp) (bp->func % PORT_MAX)
941#define BP_FUNC(bp) (bp->func)
942#define BP_E1HVN(bp) (bp->func >> 1)
943#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
944
945#ifdef BCM_CNIC
946#define BCM_CNIC_CID_START 16
947#define BCM_ISCSI_ETH_CL_ID 17
948#endif
949
950 int pm_cap;
951 int pcie_cap;
952 int mrrs;
953
954 struct delayed_work sp_task;
955 struct delayed_work reset_task;
956 struct timer_list timer;
957 int current_interval;
958
959 u16 fw_seq;
960 u16 fw_drv_pulse_wr_seq;
961 u32 func_stx;
962
963 struct link_params link_params;
964 struct link_vars link_vars;
965 struct mdio_if_info mdio;
966
967 struct bnx2x_common common;
968 struct bnx2x_port port;
969
970 struct cmng_struct_per_port cmng;
971 u32 vn_weight_sum;
972
973 u32 mf_config;
974 u16 e1hov;
975 u8 e1hmf;
976#define IS_E1HMF(bp) (bp->e1hmf != 0)
977
978 u8 wol;
979
980 int rx_ring_size;
981
982 u16 tx_quick_cons_trip_int;
983 u16 tx_quick_cons_trip;
984 u16 tx_ticks_int;
985 u16 tx_ticks;
986
987 u16 rx_quick_cons_trip_int;
988 u16 rx_quick_cons_trip;
989 u16 rx_ticks_int;
990 u16 rx_ticks;
991/* Maximal coalescing timeout in us */
992#define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
993
994 u32 lin_cnt;
995
996 int state;
997#define BNX2X_STATE_CLOSED 0
998#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
999#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1000#define BNX2X_STATE_OPEN 0x3000
1001#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1002#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1003#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
1004#define BNX2X_STATE_DIAG 0xe000
1005#define BNX2X_STATE_ERROR 0xf000
1006
1007 int multi_mode;
1008 int num_queues;
1009
1010 u32 rx_mode;
1011#define BNX2X_RX_MODE_NONE 0
1012#define BNX2X_RX_MODE_NORMAL 1
1013#define BNX2X_RX_MODE_ALLMULTI 2
1014#define BNX2X_RX_MODE_PROMISC 3
1015#define BNX2X_MAX_MULTICAST 64
1016#define BNX2X_MAX_EMUL_MULTI 16
1017
1018 u32 rx_mode_cl_mask;
1019
1020 dma_addr_t def_status_blk_mapping;
1021
1022 struct bnx2x_slowpath *slowpath;
1023 dma_addr_t slowpath_mapping;
1024
1025 int dropless_fc;
1026
1027#ifdef BCM_CNIC
1028 u32 cnic_flags;
1029#define BNX2X_CNIC_FLAG_MAC_SET 1
1030
1031 void *t1;
1032 dma_addr_t t1_mapping;
1033 void *t2;
1034 dma_addr_t t2_mapping;
1035 void *timers;
1036 dma_addr_t timers_mapping;
1037 void *qm;
1038 dma_addr_t qm_mapping;
1039 struct cnic_ops *cnic_ops;
1040 void *cnic_data;
1041 u32 cnic_tag;
1042 struct cnic_eth_dev cnic_eth_dev;
1043 struct host_status_block *cnic_sb;
1044 dma_addr_t cnic_sb_mapping;
1045#define CNIC_SB_ID(bp) BP_L_ID(bp)
1046 struct eth_spe *cnic_kwq;
1047 struct eth_spe *cnic_kwq_prod;
1048 struct eth_spe *cnic_kwq_cons;
1049 struct eth_spe *cnic_kwq_last;
1050 u16 cnic_kwq_pending;
1051 u16 cnic_spq_pending;
1052 struct mutex cnic_mutex;
1053 u8 iscsi_mac[6];
1054#endif
1055
1056 int dmae_ready;
1057 /* used to synchronize dmae accesses */
1058 struct mutex dmae_mutex;
1059
1060 /* used to protect the FW mail box */
1061 struct mutex fw_mb_mutex;
1062
1063 /* used to synchronize stats collecting */
1064 int stats_state;
1065 /* used by dmae command loader */
1066 struct dmae_command stats_dmae;
1067 int executer_idx;
1068
1069 u16 stats_counter;
1070 struct bnx2x_eth_stats eth_stats;
1071
1072 struct z_stream_s *strm;
1073 void *gunzip_buf;
1074 dma_addr_t gunzip_mapping;
1075 int gunzip_outlen;
1076#define FW_BUF_SIZE 0x8000
1077#define GUNZIP_BUF(bp) (bp->gunzip_buf)
1078#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1079#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1080
1081 struct raw_op *init_ops;
1082 /* Init blocks offsets inside init_ops */
1083 u16 *init_ops_offsets;
1084 /* Data blob - has 32 bit granularity */
1085 u32 *init_data;
1086 /* Zipped PRAM blobs - raw data */
1087 const u8 *tsem_int_table_data;
1088 const u8 *tsem_pram_data;
1089 const u8 *usem_int_table_data;
1090 const u8 *usem_pram_data;
1091 const u8 *xsem_int_table_data;
1092 const u8 *xsem_pram_data;
1093 const u8 *csem_int_table_data;
1094 const u8 *csem_pram_data;
1095#define INIT_OPS(bp) (bp->init_ops)
1096#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1097#define INIT_DATA(bp) (bp->init_data)
1098#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1099#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1100#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1101#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1102#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1103#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1104#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1105#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1106
1107 char fw_ver[32];
1108 const struct firmware *firmware;
1109};
1110
1111
1112#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \
1113 : MAX_CONTEXT)
1114#define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1115#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1116
1117#define for_each_queue(bp, var) \
1118 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1119#define for_each_nondefault_queue(bp, var) \
1120 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1121
1122
1123void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1124void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1125 u32 len32);
1126int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1127int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1128int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1129u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1130void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1131void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1132 u32 addr, u32 len);
1133
1134static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1135 int wait)
1136{
1137 u32 val;
1138
1139 do {
1140 val = REG_RD(bp, reg);
1141 if (val == expected)
1142 break;
1143 ms -= wait;
1144 msleep(wait);
1145
1146 } while (ms > 0);
1147
1148 return val;
1149}
1150
1151
1152/* load/unload mode */
1153#define LOAD_NORMAL 0
1154#define LOAD_OPEN 1
1155#define LOAD_DIAG 2
1156#define UNLOAD_NORMAL 0
1157#define UNLOAD_CLOSE 1
1158#define UNLOAD_RECOVERY 2
1159
1160
1161/* DMAE command defines */
1162#define DMAE_CMD_SRC_PCI 0
1163#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1164
1165#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1166#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1167
1168#define DMAE_CMD_C_DST_PCI 0
1169#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1170
1171#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1172
1173#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1174#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1175#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1176#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1177
1178#define DMAE_CMD_PORT_0 0
1179#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1180
1181#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1182#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1183#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1184
1185#define DMAE_LEN32_RD_MAX 0x80
1186#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1187
1188#define DMAE_COMP_VAL 0xe0d0d0ae
1189
1190#define MAX_DMAE_C_PER_PORT 8
1191#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1192 BP_E1HVN(bp))
1193#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1194 E1HVN_MAX)
1195
1196
1197/* PCIE link and speed */
1198#define PCICFG_LINK_WIDTH 0x1f00000
1199#define PCICFG_LINK_WIDTH_SHIFT 20
1200#define PCICFG_LINK_SPEED 0xf0000
1201#define PCICFG_LINK_SPEED_SHIFT 16
1202
1203
1204#define BNX2X_NUM_TESTS 7
1205
1206#define BNX2X_PHY_LOOPBACK 0
1207#define BNX2X_MAC_LOOPBACK 1
1208#define BNX2X_PHY_LOOPBACK_FAILED 1
1209#define BNX2X_MAC_LOOPBACK_FAILED 2
1210#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1211 BNX2X_PHY_LOOPBACK_FAILED)
1212
1213
1214#define STROM_ASSERT_ARRAY_SIZE 50
1215
1216
1217/* must be used on a CID before placing it on a HW ring */
1218#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1219 (BP_E1HVN(bp) << 17) | (x))
1220
1221#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1222#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1223
1224
1225#define BNX2X_BTR 1
1226#define MAX_SPQ_PENDING 8
1227
1228
1229/* CMNG constants
1230 derived from lab experiments, and not from system spec calculations !!! */
1231#define DEF_MIN_RATE 100
1232/* resolution of the rate shaping timer - 100 usec */
1233#define RS_PERIODIC_TIMEOUT_USEC 100
1234/* resolution of fairness algorithm in usecs -
1235 coefficient for calculating the actual t fair */
1236#define T_FAIR_COEF 10000000
1237/* number of bytes in single QM arbitration cycle -
1238 coefficient for calculating the fairness timer */
1239#define QM_ARB_BYTES 40000
1240#define FAIR_MEM 2
1241
1242
1243#define ATTN_NIG_FOR_FUNC (1L << 8)
1244#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1245#define GPIO_2_FUNC (1L << 10)
1246#define GPIO_3_FUNC (1L << 11)
1247#define GPIO_4_FUNC (1L << 12)
1248#define ATTN_GENERAL_ATTN_1 (1L << 13)
1249#define ATTN_GENERAL_ATTN_2 (1L << 14)
1250#define ATTN_GENERAL_ATTN_3 (1L << 15)
1251#define ATTN_GENERAL_ATTN_4 (1L << 13)
1252#define ATTN_GENERAL_ATTN_5 (1L << 14)
1253#define ATTN_GENERAL_ATTN_6 (1L << 15)
1254
1255#define ATTN_HARD_WIRED_MASK 0xff00
1256#define ATTENTION_ID 4
1257
1258
1259/* stuff added to make the code fit 80Col */
1260
1261#define BNX2X_PMF_LINK_ASSERT \
1262 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1263
1264#define BNX2X_MC_ASSERT_BITS \
1265 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1266 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1267 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1268 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1269
1270#define BNX2X_MCP_ASSERT \
1271 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1272
1273#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1274#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1275 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1276 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1277 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1278 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1279 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1280
1281#define HW_INTERRUT_ASSERT_SET_0 \
1282 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1283 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1284 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1285 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1286#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1287 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1288 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1289 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1290 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1291#define HW_INTERRUT_ASSERT_SET_1 \
1292 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1293 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1294 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1295 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1296 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1297 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1298 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1299 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1300 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1301 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1302 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1303#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1304 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1305 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1306 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1307 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1308 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1309 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1310 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1311 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1312 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1313 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1314#define HW_INTERRUT_ASSERT_SET_2 \
1315 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1316 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1317 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1318 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1319 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1320#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1321 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1322 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1323 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1324 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1325 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1326 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1327
1328#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1329 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1330 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1331 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1332
1333#define RSS_FLAGS(bp) \
1334 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1335 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1336 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1337 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1338 (bp->multi_mode << \
1339 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1340#define MULTI_MASK 0x7f
1341
1342
1343#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1344#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1345#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1346#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1347
1348#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1349
1350#define BNX2X_SP_DSB_INDEX \
1351(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1352
1353
1354#define CAM_IS_INVALID(x) \
1355(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1356
1357#define CAM_INVALIDATE(x) \
1358 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1359
1360
1361/* Number of u32 elements in MC hash array */
1362#define MC_HASH_SIZE 8
1363#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1364 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1365
1366
1367#ifndef PXP2_REG_PXP2_INT_STS
1368#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1369#endif
1370
1371#define BNX2X_VPD_LEN 128
1372#define VENDOR_ID_LEN 4
1373
1374/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1375
1376#endif /* bnx2x.h */