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kernel / sound / oss / swarm_cs4297a.c
at v2.6.34 2739 lines 89 kB view raw
1/******************************************************************************* 2* 3* "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver. 4* 5* Copyright (C) 2001 Broadcom Corporation. 6* Copyright (C) 2000,2001 Cirrus Logic Corp. 7* -- adapted from drivers by Thomas Sailer, 8* -- but don't bug him; Problems should go to: 9* -- tom woller (twoller@crystal.cirrus.com) or 10* (audio@crystal.cirrus.com). 11* -- adapted from cs4281 PCI driver for cs4297a on 12* BCM1250 Synchronous Serial interface 13* (Kip Walker, Broadcom Corp.) 14* Copyright (C) 2004 Maciej W. Rozycki 15* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 16* 17* This program is free software; you can redistribute it and/or modify 18* it under the terms of the GNU General Public License as published by 19* the Free Software Foundation; either version 2 of the License, or 20* (at your option) any later version. 21* 22* This program is distributed in the hope that it will be useful, 23* but WITHOUT ANY WARRANTY; without even the implied warranty of 24* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25* GNU General Public License for more details. 26* 27* You should have received a copy of the GNU General Public License 28* along with this program; if not, write to the Free Software 29* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 30* 31* Module command line parameters: 32* none 33* 34* Supported devices: 35* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible 36* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible 37* /dev/midi simple MIDI UART interface, no ioctl 38* 39* Modification History 40* 08/20/00 trw - silence and no stopping DAC until release 41* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop. 42* 09/18/00 trw - added 16bit only record with conversion 43* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous 44* capture/playback rates) 45* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin 46* libOSSm.so) 47* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal) 48* 11/03/00 trw - fixed interrupt loss/stutter, added debug. 49* 11/10/00 bkz - added __devinit to cs4297a_hw_init() 50* 11/10/00 trw - fixed SMP and capture spinlock hang. 51* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm. 52* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix. 53* 12/08/00 trw - added PM support. 54* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8 55* (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident. 56* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup. 57* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use 58* defaultorder-100 as power of 2 for the buffer size. example: 59* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size. 60* 61*******************************************************************************/ 62 63#include <linux/list.h> 64#include <linux/module.h> 65#include <linux/string.h> 66#include <linux/ioport.h> 67#include <linux/sched.h> 68#include <linux/delay.h> 69#include <linux/sound.h> 70#include <linux/slab.h> 71#include <linux/soundcard.h> 72#include <linux/ac97_codec.h> 73#include <linux/pci.h> 74#include <linux/bitops.h> 75#include <linux/interrupt.h> 76#include <linux/init.h> 77#include <linux/poll.h> 78#include <linux/mutex.h> 79#include <linux/kernel.h> 80 81#include <asm/byteorder.h> 82#include <asm/dma.h> 83#include <asm/io.h> 84#include <asm/uaccess.h> 85 86#include <asm/sibyte/sb1250_regs.h> 87#include <asm/sibyte/sb1250_int.h> 88#include <asm/sibyte/sb1250_dma.h> 89#include <asm/sibyte/sb1250_scd.h> 90#include <asm/sibyte/sb1250_syncser.h> 91#include <asm/sibyte/sb1250_mac.h> 92#include <asm/sibyte/sb1250.h> 93 94struct cs4297a_state; 95 96static void stop_dac(struct cs4297a_state *s); 97static void stop_adc(struct cs4297a_state *s); 98static void start_dac(struct cs4297a_state *s); 99static void start_adc(struct cs4297a_state *s); 100#undef OSS_DOCUMENTED_MIXER_SEMANTICS 101 102// --------------------------------------------------------------------- 103 104#define CS4297a_MAGIC 0xf00beef1 105 106// buffer order determines the size of the dma buffer for the driver. 107// under Linux, a smaller buffer allows more responsiveness from many of the 108// applications (e.g. games). A larger buffer allows some of the apps (esound) 109// to not underrun the dma buffer as easily. As default, use 32k (order=3) 110// rather than 64k as some of the games work more responsively. 111// log base 2( buff sz = 32k). 112 113// 114// Turn on/off debugging compilation by commenting out "#define CSDEBUG" 115// 116#define CSDEBUG 0 117#if CSDEBUG 118#define CSDEBUG_INTERFACE 1 119#else 120#undef CSDEBUG_INTERFACE 121#endif 122// 123// cs_debugmask areas 124// 125#define CS_INIT 0x00000001 // initialization and probe functions 126#define CS_ERROR 0x00000002 // tmp debugging bit placeholder 127#define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other) 128#define CS_FUNCTION 0x00000008 // enter/leave functions 129#define CS_WAVE_WRITE 0x00000010 // write information for wave 130#define CS_WAVE_READ 0x00000020 // read information for wave 131#define CS_AC97 0x00000040 // AC97 register access 132#define CS_DESCR 0x00000080 // descriptor management 133#define CS_OPEN 0x00000400 // all open functions in the driver 134#define CS_RELEASE 0x00000800 // all release functions in the driver 135#define CS_PARMS 0x00001000 // functional and operational parameters 136#define CS_IOCTL 0x00002000 // ioctl (non-mixer) 137#define CS_TMP 0x10000000 // tmp debug mask bit 138 139// 140// CSDEBUG is usual mode is set to 1, then use the 141// cs_debuglevel and cs_debugmask to turn on or off debugging. 142// Debug level of 1 has been defined to be kernel errors and info 143// that should be printed on any released driver. 144// 145#if CSDEBUG 146#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;} 147#else 148#define CS_DBGOUT(mask,level,x) 149#endif 150 151#if CSDEBUG 152static unsigned long cs_debuglevel = 4; // levels range from 1-9 153static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/; 154module_param(cs_debuglevel, int, 0); 155module_param(cs_debugmask, int, 0); 156#endif 157#define CS_TRUE 1 158#define CS_FALSE 0 159 160#define CS_TYPE_ADC 0 161#define CS_TYPE_DAC 1 162 163#define SER_BASE (A_SER_BASE_1 + KSEG1) 164#define SS_CSR(t) (SER_BASE+t) 165#define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8)) 166#define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8)) 167 168#define FRAME_BYTES 32 169#define FRAME_SAMPLE_BYTES 4 170 171/* Should this be variable? */ 172#define SAMPLE_BUF_SIZE (16*1024) 173#define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES) 174/* The driver can explode/shrink the frames to/from a smaller sample 175 buffer */ 176#define DMA_BLOAT_FACTOR 1 177#define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR) 178#define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES) 179 180/* Use the maxmium count (255 == 5.1 ms between interrupts) */ 181#define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1) 182 183/* Figure this out: how many TX DMAs ahead to schedule a reg access */ 184#define REG_LATENCY 150 185 186#define FRAME_TX_US 20 187 188#define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz) 189 190static const char invalid_magic[] = 191 KERN_CRIT "cs4297a: invalid magic value\n"; 192 193#define VALIDATE_STATE(s) \ 194({ \ 195 if (!(s) || (s)->magic != CS4297a_MAGIC) { \ 196 printk(invalid_magic); \ 197 return -ENXIO; \ 198 } \ 199}) 200 201struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs }; 202 203typedef struct serdma_descr_s { 204 u64 descr_a; 205 u64 descr_b; 206} serdma_descr_t; 207 208typedef unsigned long paddr_t; 209 210typedef struct serdma_s { 211 unsigned ringsz; 212 serdma_descr_t *descrtab; 213 serdma_descr_t *descrtab_end; 214 paddr_t descrtab_phys; 215 216 serdma_descr_t *descr_add; 217 serdma_descr_t *descr_rem; 218 219 u64 *dma_buf; // buffer for DMA contents (frames) 220 paddr_t dma_buf_phys; 221 u16 *sample_buf; // tmp buffer for sample conversions 222 u16 *sb_swptr; 223 u16 *sb_hwptr; 224 u16 *sb_end; 225 226 dma_addr_t dmaaddr; 227// unsigned buforder; // Log base 2 of 'dma_buf' size in bytes.. 228 unsigned numfrag; // # of 'fragments' in the buffer. 229 unsigned fragshift; // Log base 2 of fragment size. 230 unsigned hwptr, swptr; 231 unsigned total_bytes; // # bytes process since open. 232 unsigned blocks; // last returned blocks value GETOPTR 233 unsigned wakeup; // interrupt occurred on block 234 int count; 235 unsigned underrun; // underrun flag 236 unsigned error; // over/underrun 237 wait_queue_head_t wait; 238 wait_queue_head_t reg_wait; 239 // redundant, but makes calculations easier 240 unsigned fragsize; // 2**fragshift.. 241 unsigned sbufsz; // 2**buforder. 242 unsigned fragsamples; 243 // OSS stuff 244 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()? 245 unsigned ready:1; // prog_dmabuf_dac()/adc() successful? 246 unsigned endcleared:1; 247 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX) 248 unsigned ossfragshift; 249 int ossmaxfrags; 250 unsigned subdivision; 251} serdma_t; 252 253struct cs4297a_state { 254 // magic 255 unsigned int magic; 256 257 struct list_head list; 258 259 // soundcore stuff 260 int dev_audio; 261 int dev_mixer; 262 263 // hardware resources 264 unsigned int irq; 265 266 struct { 267 unsigned int rx_ovrrn; /* FIFO */ 268 unsigned int rx_overflow; /* staging buffer */ 269 unsigned int tx_underrun; 270 unsigned int rx_bad; 271 unsigned int rx_good; 272 } stats; 273 274 // mixer registers 275 struct { 276 unsigned short vol[10]; 277 unsigned int recsrc; 278 unsigned int modcnt; 279 unsigned short micpreamp; 280 } mix; 281 282 // wave stuff 283 struct properties { 284 unsigned fmt; 285 unsigned fmt_original; // original requested format 286 unsigned channels; 287 unsigned rate; 288 } prop_dac, prop_adc; 289 unsigned conversion:1; // conversion from 16 to 8 bit in progress 290 unsigned ena; 291 spinlock_t lock; 292 struct mutex open_mutex; 293 struct mutex open_sem_adc; 294 struct mutex open_sem_dac; 295 fmode_t open_mode; 296 wait_queue_head_t open_wait; 297 wait_queue_head_t open_wait_adc; 298 wait_queue_head_t open_wait_dac; 299 300 dma_addr_t dmaaddr_sample_buf; 301 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes.. 302 303 serdma_t dma_dac, dma_adc; 304 305 volatile u16 read_value; 306 volatile u16 read_reg; 307 volatile u64 reg_request; 308}; 309 310#if 1 311#define prog_codec(a,b) 312#define dealloc_dmabuf(a,b); 313#endif 314 315static int prog_dmabuf_adc(struct cs4297a_state *s) 316{ 317 s->dma_adc.ready = 1; 318 return 0; 319} 320 321 322static int prog_dmabuf_dac(struct cs4297a_state *s) 323{ 324 s->dma_dac.ready = 1; 325 return 0; 326} 327 328static void clear_advance(void *buf, unsigned bsize, unsigned bptr, 329 unsigned len, unsigned char c) 330{ 331 if (bptr + len > bsize) { 332 unsigned x = bsize - bptr; 333 memset(((char *) buf) + bptr, c, x); 334 bptr = 0; 335 len -= x; 336 } 337 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO 338 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n", 339 (unsigned)c, (unsigned)((char *) buf) + bptr, len)); 340 memset(((char *) buf) + bptr, c, len); 341} 342 343#if CSDEBUG 344 345// DEBUG ROUTINES 346 347#define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int) 348#define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int) 349#define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int) 350#define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int) 351 352static void cs_printioctl(unsigned int x) 353{ 354 unsigned int i; 355 unsigned char vidx; 356 // Index of mixtable1[] member is Device ID 357 // and must be <= SOUND_MIXER_NRDEVICES. 358 // Value of array member is index into s->mix.vol[] 359 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { 360 [SOUND_MIXER_PCM] = 1, // voice 361 [SOUND_MIXER_LINE1] = 2, // AUX 362 [SOUND_MIXER_CD] = 3, // CD 363 [SOUND_MIXER_LINE] = 4, // Line 364 [SOUND_MIXER_SYNTH] = 5, // FM 365 [SOUND_MIXER_MIC] = 6, // Mic 366 [SOUND_MIXER_SPEAKER] = 7, // Speaker 367 [SOUND_MIXER_RECLEV] = 8, // Recording level 368 [SOUND_MIXER_VOLUME] = 9 // Master Volume 369 }; 370 371 switch (x) { 372 case SOUND_MIXER_CS_GETDBGMASK: 373 CS_DBGOUT(CS_IOCTL, 4, 374 printk("SOUND_MIXER_CS_GETDBGMASK:\n")); 375 break; 376 case SOUND_MIXER_CS_GETDBGLEVEL: 377 CS_DBGOUT(CS_IOCTL, 4, 378 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n")); 379 break; 380 case SOUND_MIXER_CS_SETDBGMASK: 381 CS_DBGOUT(CS_IOCTL, 4, 382 printk("SOUND_MIXER_CS_SETDBGMASK:\n")); 383 break; 384 case SOUND_MIXER_CS_SETDBGLEVEL: 385 CS_DBGOUT(CS_IOCTL, 4, 386 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n")); 387 break; 388 case OSS_GETVERSION: 389 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n")); 390 break; 391 case SNDCTL_DSP_SYNC: 392 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n")); 393 break; 394 case SNDCTL_DSP_SETDUPLEX: 395 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n")); 396 break; 397 case SNDCTL_DSP_GETCAPS: 398 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n")); 399 break; 400 case SNDCTL_DSP_RESET: 401 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n")); 402 break; 403 case SNDCTL_DSP_SPEED: 404 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n")); 405 break; 406 case SNDCTL_DSP_STEREO: 407 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n")); 408 break; 409 case SNDCTL_DSP_CHANNELS: 410 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n")); 411 break; 412 case SNDCTL_DSP_GETFMTS: 413 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n")); 414 break; 415 case SNDCTL_DSP_SETFMT: 416 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n")); 417 break; 418 case SNDCTL_DSP_POST: 419 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n")); 420 break; 421 case SNDCTL_DSP_GETTRIGGER: 422 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n")); 423 break; 424 case SNDCTL_DSP_SETTRIGGER: 425 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n")); 426 break; 427 case SNDCTL_DSP_GETOSPACE: 428 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n")); 429 break; 430 case SNDCTL_DSP_GETISPACE: 431 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n")); 432 break; 433 case SNDCTL_DSP_NONBLOCK: 434 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n")); 435 break; 436 case SNDCTL_DSP_GETODELAY: 437 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n")); 438 break; 439 case SNDCTL_DSP_GETIPTR: 440 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n")); 441 break; 442 case SNDCTL_DSP_GETOPTR: 443 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n")); 444 break; 445 case SNDCTL_DSP_GETBLKSIZE: 446 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n")); 447 break; 448 case SNDCTL_DSP_SETFRAGMENT: 449 CS_DBGOUT(CS_IOCTL, 4, 450 printk("SNDCTL_DSP_SETFRAGMENT:\n")); 451 break; 452 case SNDCTL_DSP_SUBDIVIDE: 453 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n")); 454 break; 455 case SOUND_PCM_READ_RATE: 456 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n")); 457 break; 458 case SOUND_PCM_READ_CHANNELS: 459 CS_DBGOUT(CS_IOCTL, 4, 460 printk("SOUND_PCM_READ_CHANNELS:\n")); 461 break; 462 case SOUND_PCM_READ_BITS: 463 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n")); 464 break; 465 case SOUND_PCM_WRITE_FILTER: 466 CS_DBGOUT(CS_IOCTL, 4, 467 printk("SOUND_PCM_WRITE_FILTER:\n")); 468 break; 469 case SNDCTL_DSP_SETSYNCRO: 470 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n")); 471 break; 472 case SOUND_PCM_READ_FILTER: 473 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n")); 474 break; 475 case SOUND_MIXER_PRIVATE1: 476 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n")); 477 break; 478 case SOUND_MIXER_PRIVATE2: 479 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n")); 480 break; 481 case SOUND_MIXER_PRIVATE3: 482 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n")); 483 break; 484 case SOUND_MIXER_PRIVATE4: 485 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n")); 486 break; 487 case SOUND_MIXER_PRIVATE5: 488 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n")); 489 break; 490 case SOUND_MIXER_INFO: 491 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n")); 492 break; 493 case SOUND_OLD_MIXER_INFO: 494 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n")); 495 break; 496 497 default: 498 switch (_IOC_NR(x)) { 499 case SOUND_MIXER_VOLUME: 500 CS_DBGOUT(CS_IOCTL, 4, 501 printk("SOUND_MIXER_VOLUME:\n")); 502 break; 503 case SOUND_MIXER_SPEAKER: 504 CS_DBGOUT(CS_IOCTL, 4, 505 printk("SOUND_MIXER_SPEAKER:\n")); 506 break; 507 case SOUND_MIXER_RECLEV: 508 CS_DBGOUT(CS_IOCTL, 4, 509 printk("SOUND_MIXER_RECLEV:\n")); 510 break; 511 case SOUND_MIXER_MIC: 512 CS_DBGOUT(CS_IOCTL, 4, 513 printk("SOUND_MIXER_MIC:\n")); 514 break; 515 case SOUND_MIXER_SYNTH: 516 CS_DBGOUT(CS_IOCTL, 4, 517 printk("SOUND_MIXER_SYNTH:\n")); 518 break; 519 case SOUND_MIXER_RECSRC: 520 CS_DBGOUT(CS_IOCTL, 4, 521 printk("SOUND_MIXER_RECSRC:\n")); 522 break; 523 case SOUND_MIXER_DEVMASK: 524 CS_DBGOUT(CS_IOCTL, 4, 525 printk("SOUND_MIXER_DEVMASK:\n")); 526 break; 527 case SOUND_MIXER_RECMASK: 528 CS_DBGOUT(CS_IOCTL, 4, 529 printk("SOUND_MIXER_RECMASK:\n")); 530 break; 531 case SOUND_MIXER_STEREODEVS: 532 CS_DBGOUT(CS_IOCTL, 4, 533 printk("SOUND_MIXER_STEREODEVS:\n")); 534 break; 535 case SOUND_MIXER_CAPS: 536 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n")); 537 break; 538 default: 539 i = _IOC_NR(x); 540 if (i >= SOUND_MIXER_NRDEVICES 541 || !(vidx = mixtable1[i])) { 542 CS_DBGOUT(CS_IOCTL, 4, printk 543 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n", 544 x, i)); 545 } else { 546 CS_DBGOUT(CS_IOCTL, 4, printk 547 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n", 548 x, i)); 549 } 550 break; 551 } 552 } 553} 554#endif 555 556 557static int ser_init(struct cs4297a_state *s) 558{ 559 int i; 560 561 CS_DBGOUT(CS_INIT, 2, 562 printk(KERN_INFO "cs4297a: Setting up serial parameters\n")); 563 564 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD)); 565 566 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE)); 567 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ)); 568 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ)); 569 570 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH)); 571 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH)); 572 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH)); 573 574 /* This looks good from experimentation */ 575 __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT | 576 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE), 577 SS_CSR(R_SER_LINE_MODE)); 578 579 /* This looks good from experimentation */ 580 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, 581 SS_TXTBL(0)); 582 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 583 SS_TXTBL(1)); 584 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 585 SS_TXTBL(2)); 586 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | 587 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3)); 588 589 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, 590 SS_RXTBL(0)); 591 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 592 SS_RXTBL(1)); 593 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 594 SS_RXTBL(2)); 595 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE | 596 M_SYNCSER_SEQ_LAST, SS_RXTBL(3)); 597 598 for (i=4; i<16; i++) { 599 /* Just in case... */ 600 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i)); 601 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i)); 602 } 603 604 return 0; 605} 606 607static int init_serdma(serdma_t *dma) 608{ 609 CS_DBGOUT(CS_INIT, 2, 610 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n", 611 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE)); 612 613 /* Descriptors */ 614 dma->ringsz = DMA_DESCR; 615 dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL); 616 if (!dma->descrtab) { 617 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n"); 618 return -1; 619 } 620 dma->descrtab_end = dma->descrtab + dma->ringsz; 621 /* XXX bloddy mess, use proper DMA API here ... */ 622 dma->descrtab_phys = CPHYSADDR((long)dma->descrtab); 623 dma->descr_add = dma->descr_rem = dma->descrtab; 624 625 /* Frame buffer area */ 626 dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL); 627 if (!dma->dma_buf) { 628 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n"); 629 kfree(dma->descrtab); 630 return -1; 631 } 632 dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf); 633 634 /* Samples buffer area */ 635 dma->sbufsz = SAMPLE_BUF_SIZE; 636 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL); 637 if (!dma->sample_buf) { 638 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n"); 639 kfree(dma->descrtab); 640 kfree(dma->dma_buf); 641 return -1; 642 } 643 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf; 644 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz); 645 dma->fragsize = dma->sbufsz >> 1; 646 647 CS_DBGOUT(CS_INIT, 4, 648 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n", 649 (int)dma->descrtab, (int)dma->dma_buf, 650 (int)dma->sample_buf)); 651 652 return 0; 653} 654 655static int dma_init(struct cs4297a_state *s) 656{ 657 int i; 658 659 CS_DBGOUT(CS_INIT, 2, 660 printk(KERN_INFO "cs4297a: Setting up DMA\n")); 661 662 if (init_serdma(&s->dma_adc) || 663 init_serdma(&s->dma_dac)) 664 return -1; 665 666 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))|| 667 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) { 668 panic("DMA state corrupted?!"); 669 } 670 671 /* Initialize now - the descr/buffer pairings will never 672 change... */ 673 for (i=0; i<DMA_DESCR; i++) { 674 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) | 675 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES); 676 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES); 677 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) | 678 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES); 679 s->dma_adc.descrtab[i].descr_b = 0; 680 } 681 682 __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) | 683 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN), 684 SS_CSR(R_SER_DMA_CONFIG0_RX)); 685 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX)); 686 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX)); 687 688 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX)); 689 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX)); 690 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX)); 691 692 /* Prep the receive DMA descriptor ring */ 693 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 694 695 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE)); 696 697 __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT), 698 SS_CSR(R_SER_INT_MASK)); 699 700 /* Enable the rx/tx; let the codec warm up to the sync and 701 start sending good frames before the receive FIFO is 702 enabled */ 703 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); 704 udelay(1000); 705 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); 706 707 /* XXXKW is this magic? (the "1" part) */ 708 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1) 709 ; 710 711 CS_DBGOUT(CS_INIT, 4, 712 printk(KERN_INFO "cs4297a: status: %08x\n", 713 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff))); 714 715 return 0; 716} 717 718static int serdma_reg_access(struct cs4297a_state *s, u64 data) 719{ 720 serdma_t *d = &s->dma_dac; 721 u64 *data_p; 722 unsigned swptr; 723 unsigned long flags; 724 serdma_descr_t *descr; 725 726 if (s->reg_request) { 727 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n"); 728 return -1; 729 } 730 731 if (s->ena & FMODE_WRITE) { 732 /* Since a writer has the DSP open, we have to mux the 733 request in */ 734 s->reg_request = data; 735 interruptible_sleep_on(&s->dma_dac.reg_wait); 736 /* XXXKW how can I deal with the starvation case where 737 the opener isn't writing? */ 738 } else { 739 /* Be safe when changing ring pointers */ 740 spin_lock_irqsave(&s->lock, flags); 741 if (d->hwptr != d->swptr) { 742 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n", 743 d->hwptr, d->swptr); 744 spin_unlock_irqrestore(&s->lock, flags); 745 return -1; 746 } 747 swptr = d->swptr; 748 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz; 749 spin_unlock_irqrestore(&s->lock, flags); 750 751 descr = &d->descrtab[swptr]; 752 data_p = &d->dma_buf[swptr * 4]; 753 *data_p = cpu_to_be64(data); 754 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); 755 CS_DBGOUT(CS_DESCR, 4, 756 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n", 757 data_p, swptr, d->hwptr)); 758 } 759 760 CS_DBGOUT(CS_FUNCTION, 6, 761 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n")); 762 763 return 0; 764} 765 766//**************************************************************************** 767// "cs4297a_read_ac97" -- Reads an AC97 register 768//**************************************************************************** 769static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset, 770 u32 * value) 771{ 772 CS_DBGOUT(CS_AC97, 1, 773 printk(KERN_INFO "cs4297a: read reg %2x\n", offset)); 774 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40))) 775 return -1; 776 777 interruptible_sleep_on(&s->dma_adc.reg_wait); 778 *value = s->read_value; 779 CS_DBGOUT(CS_AC97, 2, 780 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value)); 781 782 return 0; 783} 784 785 786//**************************************************************************** 787// "cs4297a_write_ac97()"-- writes an AC97 register 788//**************************************************************************** 789static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset, 790 u32 value) 791{ 792 CS_DBGOUT(CS_AC97, 1, 793 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value)); 794 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12))); 795} 796 797static void stop_dac(struct cs4297a_state *s) 798{ 799 unsigned long flags; 800 801 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n")); 802 spin_lock_irqsave(&s->lock, flags); 803 s->ena &= ~FMODE_WRITE; 804#if 0 805 /* XXXKW what do I really want here? My theory for now is 806 that I just flip the "ena" bit, and the interrupt handler 807 will stop processing the xmit channel */ 808 __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0, 809 SS_CSR(R_SER_DMA_ENABLE)); 810#endif 811 812 spin_unlock_irqrestore(&s->lock, flags); 813} 814 815 816static void start_dac(struct cs4297a_state *s) 817{ 818 unsigned long flags; 819 820 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n")); 821 spin_lock_irqsave(&s->lock, flags); 822 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || 823 (s->dma_dac.count > 0 824 && s->dma_dac.ready))) { 825 s->ena |= FMODE_WRITE; 826 /* XXXKW what do I really want here? My theory for 827 now is that I just flip the "ena" bit, and the 828 interrupt handler will start processing the xmit 829 channel */ 830 831 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO 832 "cs4297a: start_dac(): start dma\n")); 833 834 } 835 spin_unlock_irqrestore(&s->lock, flags); 836 CS_DBGOUT(CS_FUNCTION, 3, 837 printk(KERN_INFO "cs4297a: start_dac()-\n")); 838} 839 840 841static void stop_adc(struct cs4297a_state *s) 842{ 843 unsigned long flags; 844 845 CS_DBGOUT(CS_FUNCTION, 3, 846 printk(KERN_INFO "cs4297a: stop_adc()+\n")); 847 848 spin_lock_irqsave(&s->lock, flags); 849 s->ena &= ~FMODE_READ; 850 851 if (s->conversion == 1) { 852 s->conversion = 0; 853 s->prop_adc.fmt = s->prop_adc.fmt_original; 854 } 855 /* Nothing to do really, I need to keep the DMA going 856 XXXKW when do I get here, and is there more I should do? */ 857 spin_unlock_irqrestore(&s->lock, flags); 858 CS_DBGOUT(CS_FUNCTION, 3, 859 printk(KERN_INFO "cs4297a: stop_adc()-\n")); 860} 861 862 863static void start_adc(struct cs4297a_state *s) 864{ 865 unsigned long flags; 866 867 CS_DBGOUT(CS_FUNCTION, 2, 868 printk(KERN_INFO "cs4297a: start_adc()+\n")); 869 870 if (!(s->ena & FMODE_READ) && 871 (s->dma_adc.mapped || s->dma_adc.count <= 872 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize)) 873 && s->dma_adc.ready) { 874 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) { 875 // 876 // now only use 16 bit capture, due to truncation issue 877 // in the chip, noticable distortion occurs. 878 // allocate buffer and then convert from 16 bit to 879 // 8 bit for the user buffer. 880 // 881 s->prop_adc.fmt_original = s->prop_adc.fmt; 882 if (s->prop_adc.fmt & AFMT_S8) { 883 s->prop_adc.fmt &= ~AFMT_S8; 884 s->prop_adc.fmt |= AFMT_S16_LE; 885 } 886 if (s->prop_adc.fmt & AFMT_U8) { 887 s->prop_adc.fmt &= ~AFMT_U8; 888 s->prop_adc.fmt |= AFMT_U16_LE; 889 } 890 // 891 // prog_dmabuf_adc performs a stop_adc() but that is 892 // ok since we really haven't started the DMA yet. 893 // 894 prog_codec(s, CS_TYPE_ADC); 895 896 prog_dmabuf_adc(s); 897 s->conversion = 1; 898 } 899 spin_lock_irqsave(&s->lock, flags); 900 s->ena |= FMODE_READ; 901 /* Nothing to do really, I am probably already 902 DMAing... XXXKW when do I get here, and is there 903 more I should do? */ 904 spin_unlock_irqrestore(&s->lock, flags); 905 906 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO 907 "cs4297a: start_adc(): start adc\n")); 908 } 909 CS_DBGOUT(CS_FUNCTION, 2, 910 printk(KERN_INFO "cs4297a: start_adc()-\n")); 911 912} 913 914 915// call with spinlock held! 916static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag) 917{ 918 int good_diff, diff, diff2; 919 u64 *data_p, data; 920 u32 *s_ptr; 921 unsigned hwptr; 922 u32 status; 923 serdma_t *d; 924 serdma_descr_t *descr; 925 926 // update ADC pointer 927 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0; 928 929 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) { 930 d = &s->dma_adc; 931 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 932 d->descrtab_phys) / sizeof(serdma_descr_t)); 933 934 if (s->ena & FMODE_READ) { 935 CS_DBGOUT(CS_FUNCTION, 2, 936 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n", 937 d->swptr, d->hwptr, hwptr, intflag)); 938 /* Number of DMA buffers available for software: */ 939 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; 940 d->hwptr = hwptr; 941 good_diff = 0; 942 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]); 943 descr = &d->descrtab[d->swptr]; 944 while (diff2--) { 945 u64 data = be64_to_cpu(*(u64 *)s_ptr); 946 u64 descr_a; 947 u16 left, right; 948 descr_a = descr->descr_a; 949 descr->descr_a &= ~M_DMA_SERRX_SOP; 950 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) { 951 printk(KERN_ERR "cs4297a: RX Bad address (read)\n"); 952 } 953 if (((data & 0x9800000000000000) != 0x9800000000000000) || 954 (!(descr_a & M_DMA_SERRX_SOP)) || 955 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) { 956 s->stats.rx_bad++; 957 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n"); 958 continue; 959 } 960 s->stats.rx_good++; 961 if ((data >> 61) == 7) { 962 s->read_value = (data >> 12) & 0xffff; 963 s->read_reg = (data >> 40) & 0x7f; 964 wake_up(&d->reg_wait); 965 } 966 if (d->count && (d->sb_hwptr == d->sb_swptr)) { 967 s->stats.rx_overflow++; 968 printk(KERN_DEBUG "cs4297a: RX overflow\n"); 969 continue; 970 } 971 good_diff++; 972 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) | 973 ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff); 974 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff; 975 *d->sb_hwptr++ = cpu_to_be16(left); 976 *d->sb_hwptr++ = cpu_to_be16(right); 977 if (d->sb_hwptr == d->sb_end) 978 d->sb_hwptr = d->sample_buf; 979 descr++; 980 if (descr == d->descrtab_end) { 981 descr = d->descrtab; 982 s_ptr = (u32 *)s->dma_adc.dma_buf; 983 } else { 984 s_ptr += 8; 985 } 986 } 987 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES; 988 d->count += good_diff * FRAME_SAMPLE_BYTES; 989 if (d->count > d->sbufsz) { 990 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n"); 991 } 992 d->swptr = (d->swptr + diff) % d->ringsz; 993 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 994 if (d->mapped) { 995 if (d->count >= (signed) d->fragsize) 996 wake_up(&d->wait); 997 } else { 998 if (d->count > 0) { 999 CS_DBGOUT(CS_WAVE_READ, 4, 1000 printk(KERN_INFO 1001 "cs4297a: update count -> %d\n", d->count)); 1002 wake_up(&d->wait); 1003 } 1004 } 1005 } else { 1006 /* Receive is going even if no one is 1007 listening (for register accesses and to 1008 avoid FIFO overrun) */ 1009 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz; 1010 if (!diff) { 1011 printk(KERN_ERR "cs4297a: RX full or empty?\n"); 1012 } 1013 1014 descr = &d->descrtab[d->swptr]; 1015 data_p = &d->dma_buf[d->swptr*4]; 1016 1017 /* Force this to happen at least once; I got 1018 here because of an interrupt, so there must 1019 be a buffer to process. */ 1020 do { 1021 data = be64_to_cpu(*data_p); 1022 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) { 1023 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr, 1024 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR), 1025 (long)CPHYSADDR((long)data_p)); 1026 } 1027 if (!(data & (1LL << 63)) || 1028 !(descr->descr_a & M_DMA_SERRX_SOP) || 1029 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) { 1030 s->stats.rx_bad++; 1031 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n"); 1032 } else { 1033 s->stats.rx_good++; 1034 if ((data >> 61) == 7) { 1035 s->read_value = (data >> 12) & 0xffff; 1036 s->read_reg = (data >> 40) & 0x7f; 1037 wake_up(&d->reg_wait); 1038 } 1039 } 1040 descr->descr_a &= ~M_DMA_SERRX_SOP; 1041 descr++; 1042 d->swptr++; 1043 data_p += 4; 1044 if (descr == d->descrtab_end) { 1045 descr = d->descrtab; 1046 d->swptr = 0; 1047 data_p = d->dma_buf; 1048 } 1049 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 1050 } while (--diff); 1051 d->hwptr = hwptr; 1052 1053 CS_DBGOUT(CS_DESCR, 6, 1054 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr)); 1055 } 1056 1057 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO 1058 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", 1059 (unsigned)s, d->hwptr, 1060 d->total_bytes, d->count)); 1061 } 1062 1063 /* XXXKW worry about s->reg_request -- there is a starvation 1064 case if s->ena has FMODE_WRITE on, but the client isn't 1065 doing writes */ 1066 1067 // update DAC pointer 1068 // 1069 // check for end of buffer, means that we are going to wait for another interrupt 1070 // to allow silence to fill the fifos on the part, to keep pops down to a minimum. 1071 // 1072 if (s->ena & FMODE_WRITE) { 1073 serdma_t *d = &s->dma_dac; 1074 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1075 d->descrtab_phys) / sizeof(serdma_descr_t)); 1076 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; 1077 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO 1078 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n", 1079 d->hwptr, hwptr, d->swptr, diff, d->count)); 1080 d->hwptr = hwptr; 1081 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */ 1082 d->total_bytes += diff * FRAME_SAMPLE_BYTES; 1083 if (d->mapped) { 1084 d->count += diff * FRAME_SAMPLE_BYTES; 1085 if (d->count >= d->fragsize) { 1086 d->wakeup = 1; 1087 wake_up(&d->wait); 1088 if (d->count > d->sbufsz) 1089 d->count &= d->sbufsz - 1; 1090 } 1091 } else { 1092 d->count -= diff * FRAME_SAMPLE_BYTES; 1093 if (d->count <= 0) { 1094 // 1095 // fill with silence, and do not shut down the DAC. 1096 // Continue to play silence until the _release. 1097 // 1098 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO 1099 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n", 1100 (unsigned)(s->prop_dac.fmt & 1101 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, 1102 (unsigned)d->dma_buf, 1103 d->ringsz)); 1104 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES); 1105 if (d->count < 0) { 1106 d->underrun = 1; 1107 s->stats.tx_underrun++; 1108 d->count = 0; 1109 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO 1110 "cs4297a: cs4297a_update_ptr(): underrun\n")); 1111 } 1112 } else if (d->count <= 1113 (signed) d->fragsize 1114 && !d->endcleared) { 1115 /* XXXKW what is this for? */ 1116 clear_advance(d->dma_buf, 1117 d->sbufsz, 1118 d->swptr, 1119 d->fragsize, 1120 0); 1121 d->endcleared = 1; 1122 } 1123 if ( (d->count <= (signed) d->sbufsz/2) || intflag) 1124 { 1125 CS_DBGOUT(CS_WAVE_WRITE, 4, 1126 printk(KERN_INFO 1127 "cs4297a: update count -> %d\n", d->count)); 1128 wake_up(&d->wait); 1129 } 1130 } 1131 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO 1132 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", 1133 (unsigned) s, d->hwptr, 1134 d->total_bytes, d->count)); 1135 } 1136} 1137 1138static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd, 1139 unsigned long arg) 1140{ 1141 // Index to mixer_src[] is value of AC97 Input Mux Select Reg. 1142 // Value of array member is recording source Device ID Mask. 1143 static const unsigned int mixer_src[8] = { 1144 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1, 1145 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0 1146 }; 1147 1148 // Index of mixtable1[] member is Device ID 1149 // and must be <= SOUND_MIXER_NRDEVICES. 1150 // Value of array member is index into s->mix.vol[] 1151 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { 1152 [SOUND_MIXER_PCM] = 1, // voice 1153 [SOUND_MIXER_LINE1] = 2, // AUX 1154 [SOUND_MIXER_CD] = 3, // CD 1155 [SOUND_MIXER_LINE] = 4, // Line 1156 [SOUND_MIXER_SYNTH] = 5, // FM 1157 [SOUND_MIXER_MIC] = 6, // Mic 1158 [SOUND_MIXER_SPEAKER] = 7, // Speaker 1159 [SOUND_MIXER_RECLEV] = 8, // Recording level 1160 [SOUND_MIXER_VOLUME] = 9 // Master Volume 1161 }; 1162 1163 static const unsigned mixreg[] = { 1164 AC97_PCMOUT_VOL, 1165 AC97_AUX_VOL, 1166 AC97_CD_VOL, 1167 AC97_LINEIN_VOL 1168 }; 1169 unsigned char l, r, rl, rr, vidx; 1170 unsigned char attentbl[11] = 1171 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 }; 1172 unsigned temp1; 1173 int i, val; 1174 1175 VALIDATE_STATE(s); 1176 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO 1177 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n", 1178 (unsigned) s, cmd)); 1179#if CSDEBUG 1180 cs_printioctl(cmd); 1181#endif 1182#if CSDEBUG_INTERFACE 1183 1184 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) || 1185 (cmd == SOUND_MIXER_CS_SETDBGMASK) || 1186 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) || 1187 (cmd == SOUND_MIXER_CS_SETDBGLEVEL)) 1188 { 1189 switch (cmd) { 1190 1191 case SOUND_MIXER_CS_GETDBGMASK: 1192 return put_user(cs_debugmask, 1193 (unsigned long *) arg); 1194 1195 case SOUND_MIXER_CS_GETDBGLEVEL: 1196 return put_user(cs_debuglevel, 1197 (unsigned long *) arg); 1198 1199 case SOUND_MIXER_CS_SETDBGMASK: 1200 if (get_user(val, (unsigned long *) arg)) 1201 return -EFAULT; 1202 cs_debugmask = val; 1203 return 0; 1204 1205 case SOUND_MIXER_CS_SETDBGLEVEL: 1206 if (get_user(val, (unsigned long *) arg)) 1207 return -EFAULT; 1208 cs_debuglevel = val; 1209 return 0; 1210 default: 1211 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO 1212 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n")); 1213 return 0; 1214 } 1215 } 1216#endif 1217 1218 if (cmd == SOUND_MIXER_PRIVATE1) { 1219 return -EINVAL; 1220 } 1221 if (cmd == SOUND_MIXER_PRIVATE2) { 1222 // enable/disable/query spatializer 1223 if (get_user(val, (int *) arg)) 1224 return -EFAULT; 1225 if (val != -1) { 1226 temp1 = (val & 0x3f) >> 2; 1227 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1); 1228 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE, 1229 &temp1); 1230 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE, 1231 temp1 | 0x2000); 1232 } 1233 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1); 1234 return put_user((temp1 << 2) | 3, (int *) arg); 1235 } 1236 if (cmd == SOUND_MIXER_INFO) { 1237 mixer_info info; 1238 memset(&info, 0, sizeof(info)); 1239 strlcpy(info.id, "CS4297a", sizeof(info.id)); 1240 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name)); 1241 info.modify_counter = s->mix.modcnt; 1242 if (copy_to_user((void *) arg, &info, sizeof(info))) 1243 return -EFAULT; 1244 return 0; 1245 } 1246 if (cmd == SOUND_OLD_MIXER_INFO) { 1247 _old_mixer_info info; 1248 memset(&info, 0, sizeof(info)); 1249 strlcpy(info.id, "CS4297a", sizeof(info.id)); 1250 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name)); 1251 if (copy_to_user((void *) arg, &info, sizeof(info))) 1252 return -EFAULT; 1253 return 0; 1254 } 1255 if (cmd == OSS_GETVERSION) 1256 return put_user(SOUND_VERSION, (int *) arg); 1257 1258 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int)) 1259 return -EINVAL; 1260 1261 // If ioctl has only the SIOC_READ bit(bit 31) 1262 // on, process the only-read commands. 1263 if (_SIOC_DIR(cmd) == _SIOC_READ) { 1264 switch (_IOC_NR(cmd)) { 1265 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 1266 cs4297a_read_ac97(s, AC97_RECORD_SELECT, 1267 &temp1); 1268 return put_user(mixer_src[temp1 & 7], (int *) arg); 1269 1270 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device 1271 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE | 1272 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, 1273 (int *) arg); 1274 1275 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source 1276 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME, 1277 (int *) arg); 1278 1279 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo 1280 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE | 1281 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, 1282 (int *) arg); 1283 1284 case SOUND_MIXER_CAPS: 1285 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg); 1286 1287 default: 1288 i = _IOC_NR(cmd); 1289 if (i >= SOUND_MIXER_NRDEVICES 1290 || !(vidx = mixtable1[i])) 1291 return -EINVAL; 1292 return put_user(s->mix.vol[vidx - 1], (int *) arg); 1293 } 1294 } 1295 // If ioctl doesn't have both the SIOC_READ and 1296 // the SIOC_WRITE bit set, return invalid. 1297 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE)) 1298 return -EINVAL; 1299 1300 // Increment the count of volume writes. 1301 s->mix.modcnt++; 1302 1303 // Isolate the command; it must be a write. 1304 switch (_IOC_NR(cmd)) { 1305 1306 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 1307 if (get_user(val, (int *) arg)) 1308 return -EFAULT; 1309 i = hweight32(val); // i = # bits on in val. 1310 if (i != 1) // One & only 1 bit must be on. 1311 return 0; 1312 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) { 1313 if (val == mixer_src[i]) { 1314 temp1 = (i << 8) | i; 1315 cs4297a_write_ac97(s, 1316 AC97_RECORD_SELECT, 1317 temp1); 1318 return 0; 1319 } 1320 } 1321 return 0; 1322 1323 case SOUND_MIXER_VOLUME: 1324 if (get_user(val, (int *) arg)) 1325 return -EFAULT; 1326 l = val & 0xff; 1327 if (l > 100) 1328 l = 100; // Max soundcard.h vol is 100. 1329 if (l < 6) { 1330 rl = 63; 1331 l = 0; 1332 } else 1333 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten. 1334 1335 r = (val >> 8) & 0xff; 1336 if (r > 100) 1337 r = 100; // Max right volume is 100, too 1338 if (r < 6) { 1339 rr = 63; 1340 r = 0; 1341 } else 1342 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation. 1343 1344 if ((rl > 60) && (rr > 60)) // If both l & r are 'low', 1345 temp1 = 0x8000; // turn on the mute bit. 1346 else 1347 temp1 = 0; 1348 1349 temp1 |= (rl << 8) | rr; 1350 1351 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1); 1352 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1); 1353 1354#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1355 s->mix.vol[8] = ((unsigned int) r << 8) | l; 1356#else 1357 s->mix.vol[8] = val; 1358#endif 1359 return put_user(s->mix.vol[8], (int *) arg); 1360 1361 case SOUND_MIXER_SPEAKER: 1362 if (get_user(val, (int *) arg)) 1363 return -EFAULT; 1364 l = val & 0xff; 1365 if (l > 100) 1366 l = 100; 1367 if (l < 3) { 1368 rl = 0; 1369 l = 0; 1370 } else { 1371 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15. 1372 l = (rl * 13 + 5) / 2; 1373 } 1374 1375 if (rl < 3) { 1376 temp1 = 0x8000; 1377 rl = 0; 1378 } else 1379 temp1 = 0; 1380 rl = 15 - rl; // Convert volume to attenuation. 1381 temp1 |= rl << 1; 1382 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1); 1383 1384#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1385 s->mix.vol[6] = l << 8; 1386#else 1387 s->mix.vol[6] = val; 1388#endif 1389 return put_user(s->mix.vol[6], (int *) arg); 1390 1391 case SOUND_MIXER_RECLEV: 1392 if (get_user(val, (int *) arg)) 1393 return -EFAULT; 1394 l = val & 0xff; 1395 if (l > 100) 1396 l = 100; 1397 r = (val >> 8) & 0xff; 1398 if (r > 100) 1399 r = 100; 1400 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15. 1401 rr = (r * 2 - 5) / 13; 1402 if (rl < 3 && rr < 3) 1403 temp1 = 0x8000; 1404 else 1405 temp1 = 0; 1406 1407 temp1 = temp1 | (rl << 8) | rr; 1408 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1); 1409 1410#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1411 s->mix.vol[7] = ((unsigned int) r << 8) | l; 1412#else 1413 s->mix.vol[7] = val; 1414#endif 1415 return put_user(s->mix.vol[7], (int *) arg); 1416 1417 case SOUND_MIXER_MIC: 1418 if (get_user(val, (int *) arg)) 1419 return -EFAULT; 1420 l = val & 0xff; 1421 if (l > 100) 1422 l = 100; 1423 if (l < 1) { 1424 l = 0; 1425 rl = 0; 1426 } else { 1427 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31. 1428 l = (rl * 16 + 4) / 5; 1429 } 1430 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1); 1431 temp1 &= 0x40; // Isolate 20db gain bit. 1432 if (rl < 3) { 1433 temp1 |= 0x8000; 1434 rl = 0; 1435 } 1436 rl = 31 - rl; // Convert volume to attenuation. 1437 temp1 |= rl; 1438 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1); 1439 1440#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1441 s->mix.vol[5] = val << 8; 1442#else 1443 s->mix.vol[5] = val; 1444#endif 1445 return put_user(s->mix.vol[5], (int *) arg); 1446 1447 1448 case SOUND_MIXER_SYNTH: 1449 if (get_user(val, (int *) arg)) 1450 return -EFAULT; 1451 l = val & 0xff; 1452 if (l > 100) 1453 l = 100; 1454 if (get_user(val, (int *) arg)) 1455 return -EFAULT; 1456 r = (val >> 8) & 0xff; 1457 if (r > 100) 1458 r = 100; 1459 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63. 1460 rr = (r * 2 - 11) / 3; 1461 if (rl < 3) // If l is low, turn on 1462 temp1 = 0x0080; // the mute bit. 1463 else 1464 temp1 = 0; 1465 1466 rl = 63 - rl; // Convert vol to attenuation. 1467// writel(temp1 | rl, s->pBA0 + FMLVC); 1468 if (rr < 3) // If rr is low, turn on 1469 temp1 = 0x0080; // the mute bit. 1470 else 1471 temp1 = 0; 1472 rr = 63 - rr; // Convert vol to attenuation. 1473// writel(temp1 | rr, s->pBA0 + FMRVC); 1474 1475#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1476 s->mix.vol[4] = (r << 8) | l; 1477#else 1478 s->mix.vol[4] = val; 1479#endif 1480 return put_user(s->mix.vol[4], (int *) arg); 1481 1482 1483 default: 1484 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1485 "cs4297a: mixer_ioctl(): default\n")); 1486 1487 i = _IOC_NR(cmd); 1488 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i])) 1489 return -EINVAL; 1490 if (get_user(val, (int *) arg)) 1491 return -EFAULT; 1492 l = val & 0xff; 1493 if (l > 100) 1494 l = 100; 1495 if (l < 1) { 1496 l = 0; 1497 rl = 31; 1498 } else 1499 rl = (attentbl[(l * 10) / 100]) >> 1; 1500 1501 r = (val >> 8) & 0xff; 1502 if (r > 100) 1503 r = 100; 1504 if (r < 1) { 1505 r = 0; 1506 rr = 31; 1507 } else 1508 rr = (attentbl[(r * 10) / 100]) >> 1; 1509 if ((rl > 30) && (rr > 30)) 1510 temp1 = 0x8000; 1511 else 1512 temp1 = 0; 1513 temp1 = temp1 | (rl << 8) | rr; 1514 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1); 1515 1516#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1517 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l; 1518#else 1519 s->mix.vol[vidx - 1] = val; 1520#endif 1521 return put_user(s->mix.vol[vidx - 1], (int *) arg); 1522 } 1523} 1524 1525 1526// --------------------------------------------------------------------- 1527 1528static int cs4297a_open_mixdev(struct inode *inode, struct file *file) 1529{ 1530 int minor = iminor(inode); 1531 struct cs4297a_state *s=NULL; 1532 struct list_head *entry; 1533 1534 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, 1535 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n")); 1536 1537 list_for_each(entry, &cs4297a_devs) 1538 { 1539 s = list_entry(entry, struct cs4297a_state, list); 1540 if(s->dev_mixer == minor) 1541 break; 1542 } 1543 if (!s) 1544 { 1545 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, 1546 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n")); 1547 return -ENODEV; 1548 } 1549 VALIDATE_STATE(s); 1550 file->private_data = s; 1551 1552 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, 1553 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n")); 1554 1555 return nonseekable_open(inode, file); 1556} 1557 1558 1559static int cs4297a_release_mixdev(struct inode *inode, struct file *file) 1560{ 1561 struct cs4297a_state *s = 1562 (struct cs4297a_state *) file->private_data; 1563 1564 VALIDATE_STATE(s); 1565 return 0; 1566} 1567 1568 1569static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file, 1570 unsigned int cmd, unsigned long arg) 1571{ 1572 return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd, 1573 arg); 1574} 1575 1576 1577// ****************************************************************************************** 1578// Mixer file operations struct. 1579// ****************************************************************************************** 1580static const struct file_operations cs4297a_mixer_fops = { 1581 .owner = THIS_MODULE, 1582 .llseek = no_llseek, 1583 .ioctl = cs4297a_ioctl_mixdev, 1584 .open = cs4297a_open_mixdev, 1585 .release = cs4297a_release_mixdev, 1586}; 1587 1588// --------------------------------------------------------------------- 1589 1590 1591static int drain_adc(struct cs4297a_state *s, int nonblock) 1592{ 1593 /* This routine serves no purpose currently - any samples 1594 sitting in the receive queue will just be processed by the 1595 background consumer. This would be different if DMA 1596 actually stopped when there were no clients. */ 1597 return 0; 1598} 1599 1600static int drain_dac(struct cs4297a_state *s, int nonblock) 1601{ 1602 DECLARE_WAITQUEUE(wait, current); 1603 unsigned long flags; 1604 unsigned hwptr; 1605 unsigned tmo; 1606 int count; 1607 1608 if (s->dma_dac.mapped) 1609 return 0; 1610 if (nonblock) 1611 return -EBUSY; 1612 add_wait_queue(&s->dma_dac.wait, &wait); 1613 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) || 1614 (s->dma_dac.count > 0)) { 1615 if (!signal_pending(current)) { 1616 set_current_state(TASK_INTERRUPTIBLE); 1617 /* XXXKW is this calculation working? */ 1618 tmo = ((count * FRAME_TX_US) * HZ) / 1000000; 1619 schedule_timeout(tmo + 1); 1620 } else { 1621 /* XXXKW do I care if there is a signal pending? */ 1622 } 1623 } 1624 spin_lock_irqsave(&s->lock, flags); 1625 /* Reset the bookkeeping */ 1626 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1627 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); 1628 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr; 1629 spin_unlock_irqrestore(&s->lock, flags); 1630 remove_wait_queue(&s->dma_dac.wait, &wait); 1631 current->state = TASK_RUNNING; 1632 return 0; 1633} 1634 1635 1636// --------------------------------------------------------------------- 1637 1638static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count, 1639 loff_t * ppos) 1640{ 1641 struct cs4297a_state *s = 1642 (struct cs4297a_state *) file->private_data; 1643 ssize_t ret; 1644 unsigned long flags; 1645 int cnt, count_fr, cnt_by; 1646 unsigned copied = 0; 1647 1648 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, 1649 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count)); 1650 1651 VALIDATE_STATE(s); 1652 if (s->dma_adc.mapped) 1653 return -ENXIO; 1654 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) 1655 return ret; 1656 if (!access_ok(VERIFY_WRITE, buffer, count)) 1657 return -EFAULT; 1658 ret = 0; 1659// 1660// "count" is the amount of bytes to read (from app), is decremented each loop 1661// by the amount of bytes that have been returned to the user buffer. 1662// "cnt" is the running total of each read from the buffer (changes each loop) 1663// "buffer" points to the app's buffer 1664// "ret" keeps a running total of the amount of bytes that have been copied 1665// to the user buffer. 1666// "copied" is the total bytes copied into the user buffer for each loop. 1667// 1668 while (count > 0) { 1669 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO 1670 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n", 1671 count, s->dma_adc.count, 1672 s->dma_adc.swptr, s->dma_adc.hwptr)); 1673 spin_lock_irqsave(&s->lock, flags); 1674 1675 /* cnt will be the number of available samples (16-bit 1676 stereo); it starts out as the maxmimum consequetive 1677 samples */ 1678 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2; 1679 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES; 1680 1681 // dma_adc.count is the current total bytes that have not been read. 1682 // if the amount of unread bytes from the current sw pointer to the 1683 // end of the buffer is greater than the current total bytes that 1684 // have not been read, then set the "cnt" (unread bytes) to the 1685 // amount of unread bytes. 1686 1687 if (count_fr < cnt) 1688 cnt = count_fr; 1689 cnt_by = cnt * FRAME_SAMPLE_BYTES; 1690 spin_unlock_irqrestore(&s->lock, flags); 1691 // 1692 // if we are converting from 8/16 then we need to copy 1693 // twice the number of 16 bit bytes then 8 bit bytes. 1694 // 1695 if (s->conversion) { 1696 if (cnt_by > (count * 2)) { 1697 cnt = (count * 2) / FRAME_SAMPLE_BYTES; 1698 cnt_by = count * 2; 1699 } 1700 } else { 1701 if (cnt_by > count) { 1702 cnt = count / FRAME_SAMPLE_BYTES; 1703 cnt_by = count; 1704 } 1705 } 1706 // 1707 // "cnt" NOW is the smaller of the amount that will be read, 1708 // and the amount that is requested in this read (or partial). 1709 // if there are no bytes in the buffer to read, then start the 1710 // ADC and wait for the interrupt handler to wake us up. 1711 // 1712 if (cnt <= 0) { 1713 1714 // start up the dma engine and then continue back to the top of 1715 // the loop when wake up occurs. 1716 start_adc(s); 1717 if (file->f_flags & O_NONBLOCK) 1718 return ret ? ret : -EAGAIN; 1719 interruptible_sleep_on(&s->dma_adc.wait); 1720 if (signal_pending(current)) 1721 return ret ? ret : -ERESTARTSYS; 1722 continue; 1723 } 1724 // there are bytes in the buffer to read. 1725 // copy from the hw buffer over to the user buffer. 1726 // user buffer is designated by "buffer" 1727 // virtual address to copy from is dma_buf+swptr 1728 // the "cnt" is the number of bytes to read. 1729 1730 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO 1731 "_read() copy_to cnt=%d count=%d ", cnt_by, count)); 1732 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO 1733 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n", 1734 s->dma_adc.sbufsz, s->dma_adc.count, 1735 (unsigned) buffer, ret)); 1736 1737 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by)) 1738 return ret ? ret : -EFAULT; 1739 copied = cnt_by; 1740 1741 /* Return the descriptors */ 1742 spin_lock_irqsave(&s->lock, flags); 1743 CS_DBGOUT(CS_FUNCTION, 2, 1744 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr)); 1745 s->dma_adc.count -= cnt_by; 1746 s->dma_adc.sb_swptr += cnt * 2; 1747 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end) 1748 s->dma_adc.sb_swptr = s->dma_adc.sample_buf; 1749 spin_unlock_irqrestore(&s->lock, flags); 1750 count -= copied; 1751 buffer += copied; 1752 ret += copied; 1753 start_adc(s); 1754 } 1755 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, 1756 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret)); 1757 return ret; 1758} 1759 1760 1761static ssize_t cs4297a_write(struct file *file, const char *buffer, 1762 size_t count, loff_t * ppos) 1763{ 1764 struct cs4297a_state *s = 1765 (struct cs4297a_state *) file->private_data; 1766 ssize_t ret; 1767 unsigned long flags; 1768 unsigned swptr, hwptr; 1769 int cnt; 1770 1771 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, 1772 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n", 1773 count)); 1774 VALIDATE_STATE(s); 1775 1776 if (s->dma_dac.mapped) 1777 return -ENXIO; 1778 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s))) 1779 return ret; 1780 if (!access_ok(VERIFY_READ, buffer, count)) 1781 return -EFAULT; 1782 ret = 0; 1783 while (count > 0) { 1784 serdma_t *d = &s->dma_dac; 1785 int copy_cnt; 1786 u32 *s_tmpl; 1787 u32 *t_tmpl; 1788 u32 left, right; 1789 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE); 1790 1791 /* XXXXXX this is broken for BLOAT_FACTOR */ 1792 spin_lock_irqsave(&s->lock, flags); 1793 if (d->count < 0) { 1794 d->count = 0; 1795 d->swptr = d->hwptr; 1796 } 1797 if (d->underrun) { 1798 d->underrun = 0; 1799 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1800 d->descrtab_phys) / sizeof(serdma_descr_t)); 1801 d->swptr = d->hwptr = hwptr; 1802 } 1803 swptr = d->swptr; 1804 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES); 1805 /* Will this write fill up the buffer? */ 1806 if (d->count + cnt > d->sbufsz) 1807 cnt = d->sbufsz - d->count; 1808 spin_unlock_irqrestore(&s->lock, flags); 1809 if (cnt > count) 1810 cnt = count; 1811 if (cnt <= 0) { 1812 start_dac(s); 1813 if (file->f_flags & O_NONBLOCK) 1814 return ret ? ret : -EAGAIN; 1815 interruptible_sleep_on(&d->wait); 1816 if (signal_pending(current)) 1817 return ret ? ret : -ERESTARTSYS; 1818 continue; 1819 } 1820 if (copy_from_user(d->sample_buf, buffer, cnt)) 1821 return ret ? ret : -EFAULT; 1822 1823 copy_cnt = cnt; 1824 s_tmpl = (u32 *)d->sample_buf; 1825 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4)); 1826 1827 /* XXXKW assuming 16-bit stereo! */ 1828 do { 1829 u32 tmp; 1830 1831 t_tmpl[0] = cpu_to_be32(0x98000000); 1832 1833 tmp = be32_to_cpu(s_tmpl[0]); 1834 left = tmp & 0xffff; 1835 right = tmp >> 16; 1836 if (swap) { 1837 left = swab16(left); 1838 right = swab16(right); 1839 } 1840 t_tmpl[1] = cpu_to_be32(left >> 8); 1841 t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) | 1842 (right << 4)); 1843 1844 s_tmpl++; 1845 t_tmpl += 8; 1846 copy_cnt -= 4; 1847 } while (copy_cnt); 1848 1849 /* Mux in any pending read/write accesses */ 1850 if (s->reg_request) { 1851 *(u64 *)(d->dma_buf + (swptr * 4)) |= 1852 cpu_to_be64(s->reg_request); 1853 s->reg_request = 0; 1854 wake_up(&s->dma_dac.reg_wait); 1855 } 1856 1857 CS_DBGOUT(CS_WAVE_WRITE, 4, 1858 printk(KERN_INFO 1859 "cs4297a: copy in %d to swptr %x\n", cnt, swptr)); 1860 1861 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz; 1862 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); 1863 spin_lock_irqsave(&s->lock, flags); 1864 d->swptr = swptr; 1865 d->count += cnt; 1866 d->endcleared = 0; 1867 spin_unlock_irqrestore(&s->lock, flags); 1868 count -= cnt; 1869 buffer += cnt; 1870 ret += cnt; 1871 start_dac(s); 1872 } 1873 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, 1874 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret)); 1875 return ret; 1876} 1877 1878 1879static unsigned int cs4297a_poll(struct file *file, 1880 struct poll_table_struct *wait) 1881{ 1882 struct cs4297a_state *s = 1883 (struct cs4297a_state *) file->private_data; 1884 unsigned long flags; 1885 unsigned int mask = 0; 1886 1887 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1888 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n")); 1889 VALIDATE_STATE(s); 1890 if (file->f_mode & FMODE_WRITE) { 1891 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1892 printk(KERN_INFO 1893 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n")); 1894 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 1895 return 0; 1896 poll_wait(file, &s->dma_dac.wait, wait); 1897 } 1898 if (file->f_mode & FMODE_READ) { 1899 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1900 printk(KERN_INFO 1901 "cs4297a: cs4297a_poll() wait on FMODE_READ\n")); 1902 if(!s->dma_dac.ready && prog_dmabuf_adc(s)) 1903 return 0; 1904 poll_wait(file, &s->dma_adc.wait, wait); 1905 } 1906 spin_lock_irqsave(&s->lock, flags); 1907 cs4297a_update_ptr(s,CS_FALSE); 1908 if (file->f_mode & FMODE_WRITE) { 1909 if (s->dma_dac.mapped) { 1910 if (s->dma_dac.count >= 1911 (signed) s->dma_dac.fragsize) { 1912 if (s->dma_dac.wakeup) 1913 mask |= POLLOUT | POLLWRNORM; 1914 else 1915 mask = 0; 1916 s->dma_dac.wakeup = 0; 1917 } 1918 } else { 1919 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count) 1920 mask |= POLLOUT | POLLWRNORM; 1921 } 1922 } else if (file->f_mode & FMODE_READ) { 1923 if (s->dma_adc.mapped) { 1924 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) 1925 mask |= POLLIN | POLLRDNORM; 1926 } else { 1927 if (s->dma_adc.count > 0) 1928 mask |= POLLIN | POLLRDNORM; 1929 } 1930 } 1931 spin_unlock_irqrestore(&s->lock, flags); 1932 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1933 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n", 1934 mask)); 1935 return mask; 1936} 1937 1938 1939static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma) 1940{ 1941 /* XXXKW currently no mmap support */ 1942 return -EINVAL; 1943 return 0; 1944} 1945 1946 1947static int cs4297a_ioctl(struct inode *inode, struct file *file, 1948 unsigned int cmd, unsigned long arg) 1949{ 1950 struct cs4297a_state *s = 1951 (struct cs4297a_state *) file->private_data; 1952 unsigned long flags; 1953 audio_buf_info abinfo; 1954 count_info cinfo; 1955 int val, mapped, ret; 1956 1957 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO 1958 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n", 1959 (unsigned) file, cmd)); 1960#if CSDEBUG 1961 cs_printioctl(cmd); 1962#endif 1963 VALIDATE_STATE(s); 1964 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) || 1965 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); 1966 switch (cmd) { 1967 case OSS_GETVERSION: 1968 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 1969 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n", 1970 SOUND_VERSION)); 1971 return put_user(SOUND_VERSION, (int *) arg); 1972 1973 case SNDCTL_DSP_SYNC: 1974 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1975 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n")); 1976 if (file->f_mode & FMODE_WRITE) 1977 return drain_dac(s, 1978 0 /*file->f_flags & O_NONBLOCK */ 1979 ); 1980 return 0; 1981 1982 case SNDCTL_DSP_SETDUPLEX: 1983 return 0; 1984 1985 case SNDCTL_DSP_GETCAPS: 1986 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | 1987 DSP_CAP_TRIGGER | DSP_CAP_MMAP, 1988 (int *) arg); 1989 1990 case SNDCTL_DSP_RESET: 1991 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1992 "cs4297a: cs4297a_ioctl(): DSP_RESET\n")); 1993 if (file->f_mode & FMODE_WRITE) { 1994 stop_dac(s); 1995 synchronize_irq(s->irq); 1996 s->dma_dac.count = s->dma_dac.total_bytes = 1997 s->dma_dac.blocks = s->dma_dac.wakeup = 0; 1998 s->dma_dac.swptr = s->dma_dac.hwptr = 1999 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 2000 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); 2001 } 2002 if (file->f_mode & FMODE_READ) { 2003 stop_adc(s); 2004 synchronize_irq(s->irq); 2005 s->dma_adc.count = s->dma_adc.total_bytes = 2006 s->dma_adc.blocks = s->dma_dac.wakeup = 0; 2007 s->dma_adc.swptr = s->dma_adc.hwptr = 2008 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 2009 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); 2010 } 2011 return 0; 2012 2013 case SNDCTL_DSP_SPEED: 2014 if (get_user(val, (int *) arg)) 2015 return -EFAULT; 2016 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2017 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val)); 2018 val = 48000; 2019 return put_user(val, (int *) arg); 2020 2021 case SNDCTL_DSP_STEREO: 2022 if (get_user(val, (int *) arg)) 2023 return -EFAULT; 2024 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2025 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val)); 2026 if (file->f_mode & FMODE_READ) { 2027 stop_adc(s); 2028 s->dma_adc.ready = 0; 2029 s->prop_adc.channels = val ? 2 : 1; 2030 } 2031 if (file->f_mode & FMODE_WRITE) { 2032 stop_dac(s); 2033 s->dma_dac.ready = 0; 2034 s->prop_dac.channels = val ? 2 : 1; 2035 } 2036 return 0; 2037 2038 case SNDCTL_DSP_CHANNELS: 2039 if (get_user(val, (int *) arg)) 2040 return -EFAULT; 2041 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2042 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n", 2043 val)); 2044 if (val != 0) { 2045 if (file->f_mode & FMODE_READ) { 2046 stop_adc(s); 2047 s->dma_adc.ready = 0; 2048 if (val >= 2) 2049 s->prop_adc.channels = 2; 2050 else 2051 s->prop_adc.channels = 1; 2052 } 2053 if (file->f_mode & FMODE_WRITE) { 2054 stop_dac(s); 2055 s->dma_dac.ready = 0; 2056 if (val >= 2) 2057 s->prop_dac.channels = 2; 2058 else 2059 s->prop_dac.channels = 1; 2060 } 2061 } 2062 2063 if (file->f_mode & FMODE_WRITE) 2064 val = s->prop_dac.channels; 2065 else if (file->f_mode & FMODE_READ) 2066 val = s->prop_adc.channels; 2067 2068 return put_user(val, (int *) arg); 2069 2070 case SNDCTL_DSP_GETFMTS: // Returns a mask 2071 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2072 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n", 2073 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | 2074 AFMT_U8)); 2075 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | 2076 AFMT_U8, (int *) arg); 2077 2078 case SNDCTL_DSP_SETFMT: 2079 if (get_user(val, (int *) arg)) 2080 return -EFAULT; 2081 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2082 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n", 2083 val)); 2084 if (val != AFMT_QUERY) { 2085 if (file->f_mode & FMODE_READ) { 2086 stop_adc(s); 2087 s->dma_adc.ready = 0; 2088 if (val != AFMT_S16_LE 2089 && val != AFMT_U16_LE && val != AFMT_S8 2090 && val != AFMT_U8) 2091 val = AFMT_U8; 2092 s->prop_adc.fmt = val; 2093 s->prop_adc.fmt_original = s->prop_adc.fmt; 2094 } 2095 if (file->f_mode & FMODE_WRITE) { 2096 stop_dac(s); 2097 s->dma_dac.ready = 0; 2098 if (val != AFMT_S16_LE 2099 && val != AFMT_U16_LE && val != AFMT_S8 2100 && val != AFMT_U8) 2101 val = AFMT_U8; 2102 s->prop_dac.fmt = val; 2103 s->prop_dac.fmt_original = s->prop_dac.fmt; 2104 } 2105 } else { 2106 if (file->f_mode & FMODE_WRITE) 2107 val = s->prop_dac.fmt_original; 2108 else if (file->f_mode & FMODE_READ) 2109 val = s->prop_adc.fmt_original; 2110 } 2111 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2112 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n", 2113 val)); 2114 return put_user(val, (int *) arg); 2115 2116 case SNDCTL_DSP_POST: 2117 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 2118 "cs4297a: cs4297a_ioctl(): DSP_POST\n")); 2119 return 0; 2120 2121 case SNDCTL_DSP_GETTRIGGER: 2122 val = 0; 2123 if (file->f_mode & s->ena & FMODE_READ) 2124 val |= PCM_ENABLE_INPUT; 2125 if (file->f_mode & s->ena & FMODE_WRITE) 2126 val |= PCM_ENABLE_OUTPUT; 2127 return put_user(val, (int *) arg); 2128 2129 case SNDCTL_DSP_SETTRIGGER: 2130 if (get_user(val, (int *) arg)) 2131 return -EFAULT; 2132 if (file->f_mode & FMODE_READ) { 2133 if (val & PCM_ENABLE_INPUT) { 2134 if (!s->dma_adc.ready 2135 && (ret = prog_dmabuf_adc(s))) 2136 return ret; 2137 start_adc(s); 2138 } else 2139 stop_adc(s); 2140 } 2141 if (file->f_mode & FMODE_WRITE) { 2142 if (val & PCM_ENABLE_OUTPUT) { 2143 if (!s->dma_dac.ready 2144 && (ret = prog_dmabuf_dac(s))) 2145 return ret; 2146 start_dac(s); 2147 } else 2148 stop_dac(s); 2149 } 2150 return 0; 2151 2152 case SNDCTL_DSP_GETOSPACE: 2153 if (!(file->f_mode & FMODE_WRITE)) 2154 return -EINVAL; 2155 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s))) 2156 return val; 2157 spin_lock_irqsave(&s->lock, flags); 2158 cs4297a_update_ptr(s,CS_FALSE); 2159 abinfo.fragsize = s->dma_dac.fragsize; 2160 if (s->dma_dac.mapped) 2161 abinfo.bytes = s->dma_dac.sbufsz; 2162 else 2163 abinfo.bytes = 2164 s->dma_dac.sbufsz - s->dma_dac.count; 2165 abinfo.fragstotal = s->dma_dac.numfrag; 2166 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; 2167 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO 2168 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n", 2169 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal, 2170 abinfo.fragments)); 2171 spin_unlock_irqrestore(&s->lock, flags); 2172 return copy_to_user((void *) arg, &abinfo, 2173 sizeof(abinfo)) ? -EFAULT : 0; 2174 2175 case SNDCTL_DSP_GETISPACE: 2176 if (!(file->f_mode & FMODE_READ)) 2177 return -EINVAL; 2178 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s))) 2179 return val; 2180 spin_lock_irqsave(&s->lock, flags); 2181 cs4297a_update_ptr(s,CS_FALSE); 2182 if (s->conversion) { 2183 abinfo.fragsize = s->dma_adc.fragsize / 2; 2184 abinfo.bytes = s->dma_adc.count / 2; 2185 abinfo.fragstotal = s->dma_adc.numfrag; 2186 abinfo.fragments = 2187 abinfo.bytes >> (s->dma_adc.fragshift - 1); 2188 } else { 2189 abinfo.fragsize = s->dma_adc.fragsize; 2190 abinfo.bytes = s->dma_adc.count; 2191 abinfo.fragstotal = s->dma_adc.numfrag; 2192 abinfo.fragments = 2193 abinfo.bytes >> s->dma_adc.fragshift; 2194 } 2195 spin_unlock_irqrestore(&s->lock, flags); 2196 return copy_to_user((void *) arg, &abinfo, 2197 sizeof(abinfo)) ? -EFAULT : 0; 2198 2199 case SNDCTL_DSP_NONBLOCK: 2200 spin_lock(&file->f_lock); 2201 file->f_flags |= O_NONBLOCK; 2202 spin_unlock(&file->f_lock); 2203 return 0; 2204 2205 case SNDCTL_DSP_GETODELAY: 2206 if (!(file->f_mode & FMODE_WRITE)) 2207 return -EINVAL; 2208 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 2209 return 0; 2210 spin_lock_irqsave(&s->lock, flags); 2211 cs4297a_update_ptr(s,CS_FALSE); 2212 val = s->dma_dac.count; 2213 spin_unlock_irqrestore(&s->lock, flags); 2214 return put_user(val, (int *) arg); 2215 2216 case SNDCTL_DSP_GETIPTR: 2217 if (!(file->f_mode & FMODE_READ)) 2218 return -EINVAL; 2219 if(!s->dma_adc.ready && prog_dmabuf_adc(s)) 2220 return 0; 2221 spin_lock_irqsave(&s->lock, flags); 2222 cs4297a_update_ptr(s,CS_FALSE); 2223 cinfo.bytes = s->dma_adc.total_bytes; 2224 if (s->dma_adc.mapped) { 2225 cinfo.blocks = 2226 (cinfo.bytes >> s->dma_adc.fragshift) - 2227 s->dma_adc.blocks; 2228 s->dma_adc.blocks = 2229 cinfo.bytes >> s->dma_adc.fragshift; 2230 } else { 2231 if (s->conversion) { 2232 cinfo.blocks = 2233 s->dma_adc.count / 2234 2 >> (s->dma_adc.fragshift - 1); 2235 } else 2236 cinfo.blocks = 2237 s->dma_adc.count >> s->dma_adc. 2238 fragshift; 2239 } 2240 if (s->conversion) 2241 cinfo.ptr = s->dma_adc.hwptr / 2; 2242 else 2243 cinfo.ptr = s->dma_adc.hwptr; 2244 if (s->dma_adc.mapped) 2245 s->dma_adc.count &= s->dma_adc.fragsize - 1; 2246 spin_unlock_irqrestore(&s->lock, flags); 2247 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2248 2249 case SNDCTL_DSP_GETOPTR: 2250 if (!(file->f_mode & FMODE_WRITE)) 2251 return -EINVAL; 2252 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 2253 return 0; 2254 spin_lock_irqsave(&s->lock, flags); 2255 cs4297a_update_ptr(s,CS_FALSE); 2256 cinfo.bytes = s->dma_dac.total_bytes; 2257 if (s->dma_dac.mapped) { 2258 cinfo.blocks = 2259 (cinfo.bytes >> s->dma_dac.fragshift) - 2260 s->dma_dac.blocks; 2261 s->dma_dac.blocks = 2262 cinfo.bytes >> s->dma_dac.fragshift; 2263 } else { 2264 cinfo.blocks = 2265 s->dma_dac.count >> s->dma_dac.fragshift; 2266 } 2267 cinfo.ptr = s->dma_dac.hwptr; 2268 if (s->dma_dac.mapped) 2269 s->dma_dac.count &= s->dma_dac.fragsize - 1; 2270 spin_unlock_irqrestore(&s->lock, flags); 2271 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2272 2273 case SNDCTL_DSP_GETBLKSIZE: 2274 if (file->f_mode & FMODE_WRITE) { 2275 if ((val = prog_dmabuf_dac(s))) 2276 return val; 2277 return put_user(s->dma_dac.fragsize, (int *) arg); 2278 } 2279 if ((val = prog_dmabuf_adc(s))) 2280 return val; 2281 if (s->conversion) 2282 return put_user(s->dma_adc.fragsize / 2, 2283 (int *) arg); 2284 else 2285 return put_user(s->dma_adc.fragsize, (int *) arg); 2286 2287 case SNDCTL_DSP_SETFRAGMENT: 2288 if (get_user(val, (int *) arg)) 2289 return -EFAULT; 2290 return 0; // Say OK, but do nothing. 2291 2292 case SNDCTL_DSP_SUBDIVIDE: 2293 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) 2294 || (file->f_mode & FMODE_WRITE 2295 && s->dma_dac.subdivision)) return -EINVAL; 2296 if (get_user(val, (int *) arg)) 2297 return -EFAULT; 2298 if (val != 1 && val != 2 && val != 4) 2299 return -EINVAL; 2300 if (file->f_mode & FMODE_READ) 2301 s->dma_adc.subdivision = val; 2302 else if (file->f_mode & FMODE_WRITE) 2303 s->dma_dac.subdivision = val; 2304 return 0; 2305 2306 case SOUND_PCM_READ_RATE: 2307 if (file->f_mode & FMODE_READ) 2308 return put_user(s->prop_adc.rate, (int *) arg); 2309 else if (file->f_mode & FMODE_WRITE) 2310 return put_user(s->prop_dac.rate, (int *) arg); 2311 2312 case SOUND_PCM_READ_CHANNELS: 2313 if (file->f_mode & FMODE_READ) 2314 return put_user(s->prop_adc.channels, (int *) arg); 2315 else if (file->f_mode & FMODE_WRITE) 2316 return put_user(s->prop_dac.channels, (int *) arg); 2317 2318 case SOUND_PCM_READ_BITS: 2319 if (file->f_mode & FMODE_READ) 2320 return 2321 put_user( 2322 (s->prop_adc. 2323 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, 2324 (int *) arg); 2325 else if (file->f_mode & FMODE_WRITE) 2326 return 2327 put_user( 2328 (s->prop_dac. 2329 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, 2330 (int *) arg); 2331 2332 case SOUND_PCM_WRITE_FILTER: 2333 case SNDCTL_DSP_SETSYNCRO: 2334 case SOUND_PCM_READ_FILTER: 2335 return -EINVAL; 2336 } 2337 return mixer_ioctl(s, cmd, arg); 2338} 2339 2340 2341static int cs4297a_release(struct inode *inode, struct file *file) 2342{ 2343 struct cs4297a_state *s = 2344 (struct cs4297a_state *) file->private_data; 2345 2346 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO 2347 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", 2348 (unsigned) inode, (unsigned) file, file->f_mode)); 2349 VALIDATE_STATE(s); 2350 2351 if (file->f_mode & FMODE_WRITE) { 2352 drain_dac(s, file->f_flags & O_NONBLOCK); 2353 mutex_lock(&s->open_sem_dac); 2354 stop_dac(s); 2355 dealloc_dmabuf(s, &s->dma_dac); 2356 s->open_mode &= ~FMODE_WRITE; 2357 mutex_unlock(&s->open_sem_dac); 2358 wake_up(&s->open_wait_dac); 2359 } 2360 if (file->f_mode & FMODE_READ) { 2361 drain_adc(s, file->f_flags & O_NONBLOCK); 2362 mutex_lock(&s->open_sem_adc); 2363 stop_adc(s); 2364 dealloc_dmabuf(s, &s->dma_adc); 2365 s->open_mode &= ~FMODE_READ; 2366 mutex_unlock(&s->open_sem_adc); 2367 wake_up(&s->open_wait_adc); 2368 } 2369 return 0; 2370} 2371 2372static int cs4297a_open(struct inode *inode, struct file *file) 2373{ 2374 int minor = iminor(inode); 2375 struct cs4297a_state *s=NULL; 2376 struct list_head *entry; 2377 2378 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2379 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", 2380 (unsigned) inode, (unsigned) file, file->f_mode)); 2381 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2382 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG)))); 2383 2384 list_for_each(entry, &cs4297a_devs) 2385 { 2386 s = list_entry(entry, struct cs4297a_state, list); 2387 2388 if (!((s->dev_audio ^ minor) & ~0xf)) 2389 break; 2390 } 2391 if (entry == &cs4297a_devs) 2392 return -ENODEV; 2393 if (!s) { 2394 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2395 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n")); 2396 return -ENODEV; 2397 } 2398 VALIDATE_STATE(s); 2399 file->private_data = s; 2400 2401 // wait for device to become free 2402 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) { 2403 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO 2404 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n")); 2405 return -ENODEV; 2406 } 2407 if (file->f_mode & FMODE_WRITE) { 2408 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) { 2409 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n"); 2410 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) 2411 ; 2412 } 2413 2414 mutex_lock(&s->open_sem_dac); 2415 while (s->open_mode & FMODE_WRITE) { 2416 if (file->f_flags & O_NONBLOCK) { 2417 mutex_unlock(&s->open_sem_dac); 2418 return -EBUSY; 2419 } 2420 mutex_unlock(&s->open_sem_dac); 2421 interruptible_sleep_on(&s->open_wait_dac); 2422 2423 if (signal_pending(current)) { 2424 printk("open - sig pending\n"); 2425 return -ERESTARTSYS; 2426 } 2427 mutex_lock(&s->open_sem_dac); 2428 } 2429 } 2430 if (file->f_mode & FMODE_READ) { 2431 mutex_lock(&s->open_sem_adc); 2432 while (s->open_mode & FMODE_READ) { 2433 if (file->f_flags & O_NONBLOCK) { 2434 mutex_unlock(&s->open_sem_adc); 2435 return -EBUSY; 2436 } 2437 mutex_unlock(&s->open_sem_adc); 2438 interruptible_sleep_on(&s->open_wait_adc); 2439 2440 if (signal_pending(current)) { 2441 printk("open - sig pending\n"); 2442 return -ERESTARTSYS; 2443 } 2444 mutex_lock(&s->open_sem_adc); 2445 } 2446 } 2447 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); 2448 if (file->f_mode & FMODE_READ) { 2449 s->prop_adc.fmt = AFMT_S16_BE; 2450 s->prop_adc.fmt_original = s->prop_adc.fmt; 2451 s->prop_adc.channels = 2; 2452 s->prop_adc.rate = 48000; 2453 s->conversion = 0; 2454 s->ena &= ~FMODE_READ; 2455 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = 2456 s->dma_adc.subdivision = 0; 2457 mutex_unlock(&s->open_sem_adc); 2458 2459 if (prog_dmabuf_adc(s)) { 2460 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR 2461 "cs4297a: adc Program dmabufs failed.\n")); 2462 cs4297a_release(inode, file); 2463 return -ENOMEM; 2464 } 2465 } 2466 if (file->f_mode & FMODE_WRITE) { 2467 s->prop_dac.fmt = AFMT_S16_BE; 2468 s->prop_dac.fmt_original = s->prop_dac.fmt; 2469 s->prop_dac.channels = 2; 2470 s->prop_dac.rate = 48000; 2471 s->conversion = 0; 2472 s->ena &= ~FMODE_WRITE; 2473 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = 2474 s->dma_dac.subdivision = 0; 2475 mutex_unlock(&s->open_sem_dac); 2476 2477 if (prog_dmabuf_dac(s)) { 2478 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR 2479 "cs4297a: dac Program dmabufs failed.\n")); 2480 cs4297a_release(inode, file); 2481 return -ENOMEM; 2482 } 2483 } 2484 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, 2485 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n")); 2486 return nonseekable_open(inode, file); 2487} 2488 2489 2490// ****************************************************************************************** 2491// Wave (audio) file operations struct. 2492// ****************************************************************************************** 2493static const struct file_operations cs4297a_audio_fops = { 2494 .owner = THIS_MODULE, 2495 .llseek = no_llseek, 2496 .read = cs4297a_read, 2497 .write = cs4297a_write, 2498 .poll = cs4297a_poll, 2499 .ioctl = cs4297a_ioctl, 2500 .mmap = cs4297a_mmap, 2501 .open = cs4297a_open, 2502 .release = cs4297a_release, 2503}; 2504 2505static void cs4297a_interrupt(int irq, void *dev_id) 2506{ 2507 struct cs4297a_state *s = (struct cs4297a_state *) dev_id; 2508 u32 status; 2509 2510 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG)); 2511 2512 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO 2513 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status)); 2514 2515#if 0 2516 /* XXXKW what check *should* be done here? */ 2517 if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) { 2518 status = __raw_readq(SS_CSR(R_SER_STATUS)); 2519 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status); 2520 return; 2521 } 2522#endif 2523 2524 if (status & M_SYNCSER_RX_SYNC_ERR) { 2525 status = __raw_readq(SS_CSR(R_SER_STATUS)); 2526 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status); 2527 return; 2528 } 2529 2530 if (status & M_SYNCSER_RX_OVERRUN) { 2531 int newptr, i; 2532 s->stats.rx_ovrrn++; 2533 printk(KERN_ERR "cs4297a: receive FIFO overrun\n"); 2534 2535 /* Fix things up: get the receive descriptor pool 2536 clean and give them back to the hardware */ 2537 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))) 2538 ; 2539 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 2540 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); 2541 for (i=0; i<DMA_DESCR; i++) { 2542 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP; 2543 } 2544 s->dma_adc.swptr = s->dma_adc.hwptr = newptr; 2545 s->dma_adc.count = 0; 2546 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf; 2547 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 2548 } 2549 2550 spin_lock(&s->lock); 2551 cs4297a_update_ptr(s,CS_TRUE); 2552 spin_unlock(&s->lock); 2553 2554 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO 2555 "cs4297a: cs4297a_interrupt()-\n")); 2556} 2557 2558#if 0 2559static struct initvol { 2560 int mixch; 2561 int vol; 2562} initvol[] __initdata = { 2563 2564 {SOUND_MIXER_WRITE_VOLUME, 0x4040}, 2565 {SOUND_MIXER_WRITE_PCM, 0x4040}, 2566 {SOUND_MIXER_WRITE_SYNTH, 0x4040}, 2567 {SOUND_MIXER_WRITE_CD, 0x4040}, 2568 {SOUND_MIXER_WRITE_LINE, 0x4040}, 2569 {SOUND_MIXER_WRITE_LINE1, 0x4040}, 2570 {SOUND_MIXER_WRITE_RECLEV, 0x0000}, 2571 {SOUND_MIXER_WRITE_SPEAKER, 0x4040}, 2572 {SOUND_MIXER_WRITE_MIC, 0x0000} 2573}; 2574#endif 2575 2576static int __init cs4297a_init(void) 2577{ 2578 struct cs4297a_state *s; 2579 u32 pwr, id; 2580 mm_segment_t fs; 2581 int rval; 2582#ifndef CONFIG_BCM_CS4297A_CSWARM 2583 u64 cfg; 2584 int mdio_val; 2585#endif 2586 2587 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO 2588 "cs4297a: cs4297a_init_module()+ \n")); 2589 2590#ifndef CONFIG_BCM_CS4297A_CSWARM 2591 mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) & 2592 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT); 2593 2594 /* Check syscfg for synchronous serial on port 1 */ 2595 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); 2596 if (!(cfg & M_SYS_SER1_ENABLE)) { 2597 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG); 2598 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); 2599 if (!(cfg & M_SYS_SER1_ENABLE)) { 2600 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n"); 2601 return -1; 2602 } 2603 2604 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n"); 2605 2606 /* Force the codec (on SWARM) to reset by clearing 2607 GENO, preserving MDIO (no effect on CSWARM) */ 2608 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); 2609 udelay(10); 2610 } 2611 2612 /* Now set GENO */ 2613 __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); 2614 /* Give the codec some time to finish resetting (start the bit clock) */ 2615 udelay(100); 2616#endif 2617 2618 if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) { 2619 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR 2620 "cs4297a: probe() no memory for state struct.\n")); 2621 return -1; 2622 } 2623 s->magic = CS4297a_MAGIC; 2624 init_waitqueue_head(&s->dma_adc.wait); 2625 init_waitqueue_head(&s->dma_dac.wait); 2626 init_waitqueue_head(&s->dma_adc.reg_wait); 2627 init_waitqueue_head(&s->dma_dac.reg_wait); 2628 init_waitqueue_head(&s->open_wait); 2629 init_waitqueue_head(&s->open_wait_adc); 2630 init_waitqueue_head(&s->open_wait_dac); 2631 mutex_init(&s->open_sem_adc); 2632 mutex_init(&s->open_sem_dac); 2633 spin_lock_init(&s->lock); 2634 2635 s->irq = K_INT_SER_1; 2636 2637 if (request_irq 2638 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) { 2639 CS_DBGOUT(CS_INIT | CS_ERROR, 1, 2640 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq)); 2641 goto err_irq; 2642 } 2643 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) < 2644 0) { 2645 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2646 "cs4297a: probe() register_sound_dsp() failed.\n")); 2647 goto err_dev1; 2648 } 2649 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) < 2650 0) { 2651 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2652 "cs4297a: probe() register_sound_mixer() failed.\n")); 2653 goto err_dev2; 2654 } 2655 2656 if (ser_init(s) || dma_init(s)) { 2657 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2658 "cs4297a: ser_init failed.\n")); 2659 goto err_dev3; 2660 } 2661 2662 do { 2663 udelay(4000); 2664 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr); 2665 } while (!rval && (pwr != 0xf)); 2666 2667 if (!rval) { 2668 char *sb1250_duart_present; 2669 2670 fs = get_fs(); 2671 set_fs(KERNEL_DS); 2672#if 0 2673 val = SOUND_MASK_LINE; 2674 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val); 2675 for (i = 0; i < ARRAY_SIZE(initvol); i++) { 2676 val = initvol[i].vol; 2677 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val); 2678 } 2679// cs4297a_write_ac97(s, 0x18, 0x0808); 2680#else 2681 // cs4297a_write_ac97(s, 0x5e, 0x180); 2682 cs4297a_write_ac97(s, 0x02, 0x0808); 2683 cs4297a_write_ac97(s, 0x18, 0x0808); 2684#endif 2685 set_fs(fs); 2686 2687 list_add(&s->list, &cs4297a_devs); 2688 2689 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id); 2690 2691 sb1250_duart_present = symbol_get(sb1250_duart_present); 2692 if (sb1250_duart_present) 2693 sb1250_duart_present[1] = 0; 2694 2695 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id); 2696 2697 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, 2698 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n")); 2699 2700 return 0; 2701 } 2702 2703 err_dev3: 2704 unregister_sound_mixer(s->dev_mixer); 2705 err_dev2: 2706 unregister_sound_dsp(s->dev_audio); 2707 err_dev1: 2708 free_irq(s->irq, s); 2709 err_irq: 2710 kfree(s); 2711 2712 printk(KERN_INFO "cs4297a: initialization failed\n"); 2713 2714 return -1; 2715} 2716 2717static void __exit cs4297a_cleanup(void) 2718{ 2719 /* 2720 XXXKW 2721 disable_irq, free_irq 2722 drain DMA queue 2723 disable DMA 2724 disable TX/RX 2725 free memory 2726 */ 2727 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, 2728 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n")); 2729} 2730 2731// --------------------------------------------------------------------- 2732 2733MODULE_AUTHOR("Kip Walker, Broadcom Corp."); 2734MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board"); 2735 2736// --------------------------------------------------------------------- 2737 2738module_init(cs4297a_init); 2739module_exit(cs4297a_cleanup);