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Linux kernel mirror (for testing)
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linux
1/*
2 * arch/arm/include/asm/io.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21#ifndef __ASM_ARM_IO_H
22#define __ASM_ARM_IO_H
23
24#ifdef __KERNEL__
25
26#include <linux/types.h>
27#include <asm/byteorder.h>
28#include <asm/memory.h>
29
30/*
31 * ISA I/O bus memory addresses are 1:1 with the physical address.
32 */
33#define isa_virt_to_bus virt_to_phys
34#define isa_page_to_bus page_to_phys
35#define isa_bus_to_virt phys_to_virt
36
37/*
38 * Generic IO read/write. These perform native-endian accesses. Note
39 * that some architectures will want to re-define __raw_{read,write}w.
40 */
41extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
42extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
43extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
44
45extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
46extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
47extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
48
49#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
50#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
51#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
52
53#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
54#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
55#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
56
57/*
58 * Architecture ioremap implementation.
59 */
60#define MT_DEVICE 0
61#define MT_DEVICE_NONSHARED 1
62#define MT_DEVICE_CACHED 2
63#define MT_DEVICE_WC 3
64/*
65 * types 4 onwards can be found in asm/mach/map.h and are undefined
66 * for ioremap
67 */
68
69/*
70 * __arm_ioremap takes CPU physical address.
71 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
72 * The _caller variety takes a __builtin_return_address(0) value for
73 * /proc/vmalloc to use - and should only be used in non-inline functions.
74 */
75extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
76 size_t, unsigned int, void *);
77extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
78 void *);
79
80extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
81extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
82extern void __iounmap(volatile void __iomem *addr);
83
84/*
85 * Bad read/write accesses...
86 */
87extern void __readwrite_bug(const char *fn);
88
89/*
90 * A typesafe __io() helper
91 */
92static inline void __iomem *__typesafe_io(unsigned long addr)
93{
94 return (void __iomem *)addr;
95}
96
97/*
98 * Now, pick up the machine-defined IO definitions
99 */
100#include <mach/io.h>
101
102/*
103 * IO port access primitives
104 * -------------------------
105 *
106 * The ARM doesn't have special IO access instructions; all IO is memory
107 * mapped. Note that these are defined to perform little endian accesses
108 * only. Their primary purpose is to access PCI and ISA peripherals.
109 *
110 * Note that for a big endian machine, this implies that the following
111 * big endian mode connectivity is in place, as described by numerous
112 * ARM documents:
113 *
114 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
115 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
116 *
117 * The machine specific io.h include defines __io to translate an "IO"
118 * address to a memory address.
119 *
120 * Note that we prevent GCC re-ordering or caching values in expressions
121 * by introducing sequence points into the in*() definitions. Note that
122 * __raw_* do not guarantee this behaviour.
123 *
124 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
125 */
126#ifdef __io
127#define outb(v,p) __raw_writeb(v,__io(p))
128#define outw(v,p) __raw_writew((__force __u16) \
129 cpu_to_le16(v),__io(p))
130#define outl(v,p) __raw_writel((__force __u32) \
131 cpu_to_le32(v),__io(p))
132
133#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; })
134#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
135 __raw_readw(__io(p))); __v; })
136#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
137 __raw_readl(__io(p))); __v; })
138
139#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
140#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
141#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
142
143#define insb(p,d,l) __raw_readsb(__io(p),d,l)
144#define insw(p,d,l) __raw_readsw(__io(p),d,l)
145#define insl(p,d,l) __raw_readsl(__io(p),d,l)
146#endif
147
148#define outb_p(val,port) outb((val),(port))
149#define outw_p(val,port) outw((val),(port))
150#define outl_p(val,port) outl((val),(port))
151#define inb_p(port) inb((port))
152#define inw_p(port) inw((port))
153#define inl_p(port) inl((port))
154
155#define outsb_p(port,from,len) outsb(port,from,len)
156#define outsw_p(port,from,len) outsw(port,from,len)
157#define outsl_p(port,from,len) outsl(port,from,len)
158#define insb_p(port,to,len) insb(port,to,len)
159#define insw_p(port,to,len) insw(port,to,len)
160#define insl_p(port,to,len) insl(port,to,len)
161
162/*
163 * String version of IO memory access ops:
164 */
165extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
166extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
167extern void _memset_io(volatile void __iomem *, int, size_t);
168
169#define mmiowb()
170
171/*
172 * Memory access primitives
173 * ------------------------
174 *
175 * These perform PCI memory accesses via an ioremap region. They don't
176 * take an address as such, but a cookie.
177 *
178 * Again, this are defined to perform little endian accesses. See the
179 * IO port primitives for more information.
180 */
181#ifdef __mem_pci
182#define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; })
183#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
184 __raw_readw(__mem_pci(c))); __v; })
185#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
186 __raw_readl(__mem_pci(c))); __v; })
187#define readb_relaxed(addr) readb(addr)
188#define readw_relaxed(addr) readw(addr)
189#define readl_relaxed(addr) readl(addr)
190
191#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
192#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
193#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
194
195#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
196#define writew(v,c) __raw_writew((__force __u16) \
197 cpu_to_le16(v),__mem_pci(c))
198#define writel(v,c) __raw_writel((__force __u32) \
199 cpu_to_le32(v),__mem_pci(c))
200
201#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
202#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
203#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
204
205#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
206#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
207#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
208
209#elif !defined(readb)
210
211#define readb(c) (__readwrite_bug("readb"),0)
212#define readw(c) (__readwrite_bug("readw"),0)
213#define readl(c) (__readwrite_bug("readl"),0)
214#define writeb(v,c) __readwrite_bug("writeb")
215#define writew(v,c) __readwrite_bug("writew")
216#define writel(v,c) __readwrite_bug("writel")
217
218#define check_signature(io,sig,len) (0)
219
220#endif /* __mem_pci */
221
222/*
223 * ioremap and friends.
224 *
225 * ioremap takes a PCI memory address, as specified in
226 * Documentation/IO-mapping.txt.
227 *
228 */
229#ifndef __arch_ioremap
230#define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
231#define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
232#define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
233#define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC)
234#define iounmap(cookie) __iounmap(cookie)
235#else
236#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
237#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
238#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
239#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
240#define iounmap(cookie) __arch_iounmap(cookie)
241#endif
242
243/*
244 * io{read,write}{8,16,32} macros
245 */
246#ifndef ioread8
247#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
248#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; })
249#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; })
250
251#define iowrite8(v,p) __raw_writeb(v, p)
252#define iowrite16(v,p) __raw_writew((__force __u16)cpu_to_le16(v), p)
253#define iowrite32(v,p) __raw_writel((__force __u32)cpu_to_le32(v), p)
254
255#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
256#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
257#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
258
259#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
260#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
261#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
262
263extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
264extern void ioport_unmap(void __iomem *addr);
265#endif
266
267struct pci_dev;
268
269extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
270extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
271
272/*
273 * can the hardware map this into one segment or not, given no other
274 * constraints.
275 */
276#define BIOVEC_MERGEABLE(vec1, vec2) \
277 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
278
279#ifdef CONFIG_MMU
280#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
281extern int valid_phys_addr_range(unsigned long addr, size_t size);
282extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
283#endif
284
285/*
286 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
287 * access
288 */
289#define xlate_dev_mem_ptr(p) __va(p)
290
291/*
292 * Convert a virtual cached pointer to an uncached pointer
293 */
294#define xlate_dev_kmem_ptr(p) p
295
296/*
297 * Register ISA memory and port locations for glibc iopl/inb/outb
298 * emulation.
299 */
300extern void register_isa_ports(unsigned int mmio, unsigned int io,
301 unsigned int io_shift);
302
303#endif /* __KERNEL__ */
304#endif /* __ASM_ARM_IO_H */