tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _E1000_HW_H_
29#define _E1000_HW_H_
30
31#include <linux/types.h>
32#include <linux/delay.h>
33#include <linux/io.h>
34
35#include "e1000_regs.h"
36#include "e1000_defines.h"
37
38struct e1000_hw;
39
40#define E1000_DEV_ID_82576 0x10C9
41#define E1000_DEV_ID_82576_FIBER 0x10E6
42#define E1000_DEV_ID_82576_SERDES 0x10E7
43#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
44#define E1000_DEV_ID_82576_NS 0x150A
45#define E1000_DEV_ID_82576_NS_SERDES 0x1518
46#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
47#define E1000_DEV_ID_82575EB_COPPER 0x10A7
48#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
49#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
50#define E1000_DEV_ID_82580_COPPER 0x150E
51#define E1000_DEV_ID_82580_FIBER 0x150F
52#define E1000_DEV_ID_82580_SERDES 0x1510
53#define E1000_DEV_ID_82580_SGMII 0x1511
54#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
55
56#define E1000_REVISION_2 2
57#define E1000_REVISION_4 4
58
59#define E1000_FUNC_0 0
60#define E1000_FUNC_1 1
61#define E1000_FUNC_2 2
62#define E1000_FUNC_3 3
63
64#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
65#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
66#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
67#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
68
69enum e1000_mac_type {
70 e1000_undefined = 0,
71 e1000_82575,
72 e1000_82576,
73 e1000_82580,
74 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
75};
76
77enum e1000_media_type {
78 e1000_media_type_unknown = 0,
79 e1000_media_type_copper = 1,
80 e1000_media_type_internal_serdes = 2,
81 e1000_num_media_types
82};
83
84enum e1000_nvm_type {
85 e1000_nvm_unknown = 0,
86 e1000_nvm_none,
87 e1000_nvm_eeprom_spi,
88 e1000_nvm_flash_hw,
89 e1000_nvm_flash_sw
90};
91
92enum e1000_nvm_override {
93 e1000_nvm_override_none = 0,
94 e1000_nvm_override_spi_small,
95 e1000_nvm_override_spi_large,
96};
97
98enum e1000_phy_type {
99 e1000_phy_unknown = 0,
100 e1000_phy_none,
101 e1000_phy_m88,
102 e1000_phy_igp,
103 e1000_phy_igp_2,
104 e1000_phy_gg82563,
105 e1000_phy_igp_3,
106 e1000_phy_ife,
107 e1000_phy_82580,
108};
109
110enum e1000_bus_type {
111 e1000_bus_type_unknown = 0,
112 e1000_bus_type_pci,
113 e1000_bus_type_pcix,
114 e1000_bus_type_pci_express,
115 e1000_bus_type_reserved
116};
117
118enum e1000_bus_speed {
119 e1000_bus_speed_unknown = 0,
120 e1000_bus_speed_33,
121 e1000_bus_speed_66,
122 e1000_bus_speed_100,
123 e1000_bus_speed_120,
124 e1000_bus_speed_133,
125 e1000_bus_speed_2500,
126 e1000_bus_speed_5000,
127 e1000_bus_speed_reserved
128};
129
130enum e1000_bus_width {
131 e1000_bus_width_unknown = 0,
132 e1000_bus_width_pcie_x1,
133 e1000_bus_width_pcie_x2,
134 e1000_bus_width_pcie_x4 = 4,
135 e1000_bus_width_pcie_x8 = 8,
136 e1000_bus_width_32,
137 e1000_bus_width_64,
138 e1000_bus_width_reserved
139};
140
141enum e1000_1000t_rx_status {
142 e1000_1000t_rx_status_not_ok = 0,
143 e1000_1000t_rx_status_ok,
144 e1000_1000t_rx_status_undefined = 0xFF
145};
146
147enum e1000_rev_polarity {
148 e1000_rev_polarity_normal = 0,
149 e1000_rev_polarity_reversed,
150 e1000_rev_polarity_undefined = 0xFF
151};
152
153enum e1000_fc_mode {
154 e1000_fc_none = 0,
155 e1000_fc_rx_pause,
156 e1000_fc_tx_pause,
157 e1000_fc_full,
158 e1000_fc_default = 0xFF
159};
160
161/* Statistics counters collected by the MAC */
162struct e1000_hw_stats {
163 u64 crcerrs;
164 u64 algnerrc;
165 u64 symerrs;
166 u64 rxerrc;
167 u64 mpc;
168 u64 scc;
169 u64 ecol;
170 u64 mcc;
171 u64 latecol;
172 u64 colc;
173 u64 dc;
174 u64 tncrs;
175 u64 sec;
176 u64 cexterr;
177 u64 rlec;
178 u64 xonrxc;
179 u64 xontxc;
180 u64 xoffrxc;
181 u64 xofftxc;
182 u64 fcruc;
183 u64 prc64;
184 u64 prc127;
185 u64 prc255;
186 u64 prc511;
187 u64 prc1023;
188 u64 prc1522;
189 u64 gprc;
190 u64 bprc;
191 u64 mprc;
192 u64 gptc;
193 u64 gorc;
194 u64 gotc;
195 u64 rnbc;
196 u64 ruc;
197 u64 rfc;
198 u64 roc;
199 u64 rjc;
200 u64 mgprc;
201 u64 mgpdc;
202 u64 mgptc;
203 u64 tor;
204 u64 tot;
205 u64 tpr;
206 u64 tpt;
207 u64 ptc64;
208 u64 ptc127;
209 u64 ptc255;
210 u64 ptc511;
211 u64 ptc1023;
212 u64 ptc1522;
213 u64 mptc;
214 u64 bptc;
215 u64 tsctc;
216 u64 tsctfc;
217 u64 iac;
218 u64 icrxptc;
219 u64 icrxatc;
220 u64 ictxptc;
221 u64 ictxatc;
222 u64 ictxqec;
223 u64 ictxqmtc;
224 u64 icrxdmtc;
225 u64 icrxoc;
226 u64 cbtmpc;
227 u64 htdpmc;
228 u64 cbrdpc;
229 u64 cbrmpc;
230 u64 rpthc;
231 u64 hgptc;
232 u64 htcbdpc;
233 u64 hgorc;
234 u64 hgotc;
235 u64 lenerrs;
236 u64 scvpc;
237 u64 hrmpc;
238 u64 doosync;
239};
240
241struct e1000_phy_stats {
242 u32 idle_errors;
243 u32 receive_errors;
244};
245
246struct e1000_host_mng_dhcp_cookie {
247 u32 signature;
248 u8 status;
249 u8 reserved0;
250 u16 vlan_id;
251 u32 reserved1;
252 u16 reserved2;
253 u8 reserved3;
254 u8 checksum;
255};
256
257/* Host Interface "Rev 1" */
258struct e1000_host_command_header {
259 u8 command_id;
260 u8 command_length;
261 u8 command_options;
262 u8 checksum;
263};
264
265#define E1000_HI_MAX_DATA_LENGTH 252
266struct e1000_host_command_info {
267 struct e1000_host_command_header command_header;
268 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
269};
270
271/* Host Interface "Rev 2" */
272struct e1000_host_mng_command_header {
273 u8 command_id;
274 u8 checksum;
275 u16 reserved1;
276 u16 reserved2;
277 u16 command_length;
278};
279
280#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
281struct e1000_host_mng_command_info {
282 struct e1000_host_mng_command_header command_header;
283 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
284};
285
286#include "e1000_mac.h"
287#include "e1000_phy.h"
288#include "e1000_nvm.h"
289#include "e1000_mbx.h"
290
291struct e1000_mac_operations {
292 s32 (*check_for_link)(struct e1000_hw *);
293 s32 (*reset_hw)(struct e1000_hw *);
294 s32 (*init_hw)(struct e1000_hw *);
295 bool (*check_mng_mode)(struct e1000_hw *);
296 s32 (*setup_physical_interface)(struct e1000_hw *);
297 void (*rar_set)(struct e1000_hw *, u8 *, u32);
298 s32 (*read_mac_addr)(struct e1000_hw *);
299 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
300};
301
302struct e1000_phy_operations {
303 s32 (*acquire)(struct e1000_hw *);
304 s32 (*check_polarity)(struct e1000_hw *);
305 s32 (*check_reset_block)(struct e1000_hw *);
306 s32 (*force_speed_duplex)(struct e1000_hw *);
307 s32 (*get_cfg_done)(struct e1000_hw *hw);
308 s32 (*get_cable_length)(struct e1000_hw *);
309 s32 (*get_phy_info)(struct e1000_hw *);
310 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
311 void (*release)(struct e1000_hw *);
312 s32 (*reset)(struct e1000_hw *);
313 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
314 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
315 s32 (*write_reg)(struct e1000_hw *, u32, u16);
316};
317
318struct e1000_nvm_operations {
319 s32 (*acquire)(struct e1000_hw *);
320 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
321 void (*release)(struct e1000_hw *);
322 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
323};
324
325struct e1000_info {
326 s32 (*get_invariants)(struct e1000_hw *);
327 struct e1000_mac_operations *mac_ops;
328 struct e1000_phy_operations *phy_ops;
329 struct e1000_nvm_operations *nvm_ops;
330};
331
332extern const struct e1000_info e1000_82575_info;
333
334struct e1000_mac_info {
335 struct e1000_mac_operations ops;
336
337 u8 addr[6];
338 u8 perm_addr[6];
339
340 enum e1000_mac_type type;
341
342 u32 ledctl_default;
343 u32 ledctl_mode1;
344 u32 ledctl_mode2;
345 u32 mc_filter_type;
346 u32 txcw;
347
348 u16 mta_reg_count;
349 u16 uta_reg_count;
350
351 /* Maximum size of the MTA register table in all supported adapters */
352 #define MAX_MTA_REG 128
353 u32 mta_shadow[MAX_MTA_REG];
354 u16 rar_entry_count;
355
356 u8 forced_speed_duplex;
357
358 bool adaptive_ifs;
359 bool arc_subsystem_valid;
360 bool asf_firmware_present;
361 bool autoneg;
362 bool autoneg_failed;
363 bool disable_hw_init_bits;
364 bool get_link_status;
365 bool ifs_params_forced;
366 bool in_ifs_mode;
367 bool report_tx_early;
368 bool serdes_has_link;
369 bool tx_pkt_filtering;
370};
371
372struct e1000_phy_info {
373 struct e1000_phy_operations ops;
374
375 enum e1000_phy_type type;
376
377 enum e1000_1000t_rx_status local_rx;
378 enum e1000_1000t_rx_status remote_rx;
379 enum e1000_ms_type ms_type;
380 enum e1000_ms_type original_ms_type;
381 enum e1000_rev_polarity cable_polarity;
382 enum e1000_smart_speed smart_speed;
383
384 u32 addr;
385 u32 id;
386 u32 reset_delay_us; /* in usec */
387 u32 revision;
388
389 enum e1000_media_type media_type;
390
391 u16 autoneg_advertised;
392 u16 autoneg_mask;
393 u16 cable_length;
394 u16 max_cable_length;
395 u16 min_cable_length;
396
397 u8 mdix;
398
399 bool disable_polarity_correction;
400 bool is_mdix;
401 bool polarity_correction;
402 bool reset_disable;
403 bool speed_downgraded;
404 bool autoneg_wait_to_complete;
405};
406
407struct e1000_nvm_info {
408 struct e1000_nvm_operations ops;
409
410 enum e1000_nvm_type type;
411 enum e1000_nvm_override override;
412
413 u32 flash_bank_size;
414 u32 flash_base_addr;
415
416 u16 word_size;
417 u16 delay_usec;
418 u16 address_bits;
419 u16 opcode_bits;
420 u16 page_size;
421};
422
423struct e1000_bus_info {
424 enum e1000_bus_type type;
425 enum e1000_bus_speed speed;
426 enum e1000_bus_width width;
427
428 u32 snoop;
429
430 u16 func;
431 u16 pci_cmd_word;
432};
433
434struct e1000_fc_info {
435 u32 high_water; /* Flow control high-water mark */
436 u32 low_water; /* Flow control low-water mark */
437 u16 pause_time; /* Flow control pause timer */
438 bool send_xon; /* Flow control send XON */
439 bool strict_ieee; /* Strict IEEE mode */
440 enum e1000_fc_mode current_mode; /* Type of flow control */
441 enum e1000_fc_mode requested_mode;
442};
443
444struct e1000_mbx_operations {
445 s32 (*init_params)(struct e1000_hw *hw);
446 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
447 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
448 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
449 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
450 s32 (*check_for_msg)(struct e1000_hw *, u16);
451 s32 (*check_for_ack)(struct e1000_hw *, u16);
452 s32 (*check_for_rst)(struct e1000_hw *, u16);
453};
454
455struct e1000_mbx_stats {
456 u32 msgs_tx;
457 u32 msgs_rx;
458
459 u32 acks;
460 u32 reqs;
461 u32 rsts;
462};
463
464struct e1000_mbx_info {
465 struct e1000_mbx_operations ops;
466 struct e1000_mbx_stats stats;
467 u32 timeout;
468 u32 usec_delay;
469 u16 size;
470};
471
472struct e1000_dev_spec_82575 {
473 bool sgmii_active;
474 bool global_device_reset;
475};
476
477struct e1000_hw {
478 void *back;
479
480 u8 __iomem *hw_addr;
481 u8 __iomem *flash_address;
482 unsigned long io_base;
483
484 struct e1000_mac_info mac;
485 struct e1000_fc_info fc;
486 struct e1000_phy_info phy;
487 struct e1000_nvm_info nvm;
488 struct e1000_bus_info bus;
489 struct e1000_mbx_info mbx;
490 struct e1000_host_mng_dhcp_cookie mng_cookie;
491
492 union {
493 struct e1000_dev_spec_82575 _82575;
494 } dev_spec;
495
496 u16 device_id;
497 u16 subsystem_vendor_id;
498 u16 subsystem_device_id;
499 u16 vendor_id;
500
501 u8 revision_id;
502};
503
504#ifdef DEBUG
505extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
506#define hw_dbg(format, arg...) \
507 printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
508#else
509#define hw_dbg(format, arg...)
510#endif
511#endif
512/* These functions must be implemented by drivers */
513s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
514s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);