tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2006, 2007 Eugene Konev
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/moduleparam.h>
22
23#include <linux/sched.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/errno.h>
27#include <linux/types.h>
28#include <linux/delay.h>
29
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/phy_fixed.h>
37#include <linux/platform_device.h>
38#include <linux/dma-mapping.h>
39#include <linux/clk.h>
40#include <asm/gpio.h>
41#include <asm/atomic.h>
42
43MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
44MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
45MODULE_LICENSE("GPL");
46MODULE_ALIAS("platform:cpmac");
47
48static int debug_level = 8;
49static int dumb_switch;
50
51/* Next 2 are only used in cpmac_probe, so it's pointless to change them */
52module_param(debug_level, int, 0444);
53module_param(dumb_switch, int, 0444);
54
55MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
56MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
57
58#define CPMAC_VERSION "0.5.1"
59/* frame size + 802.1q tag */
60#define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
61#define CPMAC_QUEUES 8
62
63/* Ethernet registers */
64#define CPMAC_TX_CONTROL 0x0004
65#define CPMAC_TX_TEARDOWN 0x0008
66#define CPMAC_RX_CONTROL 0x0014
67#define CPMAC_RX_TEARDOWN 0x0018
68#define CPMAC_MBP 0x0100
69# define MBP_RXPASSCRC 0x40000000
70# define MBP_RXQOS 0x20000000
71# define MBP_RXNOCHAIN 0x10000000
72# define MBP_RXCMF 0x01000000
73# define MBP_RXSHORT 0x00800000
74# define MBP_RXCEF 0x00400000
75# define MBP_RXPROMISC 0x00200000
76# define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
77# define MBP_RXBCAST 0x00002000
78# define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
79# define MBP_RXMCAST 0x00000020
80# define MBP_MCASTCHAN(channel) ((channel) & 0x7)
81#define CPMAC_UNICAST_ENABLE 0x0104
82#define CPMAC_UNICAST_CLEAR 0x0108
83#define CPMAC_MAX_LENGTH 0x010c
84#define CPMAC_BUFFER_OFFSET 0x0110
85#define CPMAC_MAC_CONTROL 0x0160
86# define MAC_TXPTYPE 0x00000200
87# define MAC_TXPACE 0x00000040
88# define MAC_MII 0x00000020
89# define MAC_TXFLOW 0x00000010
90# define MAC_RXFLOW 0x00000008
91# define MAC_MTEST 0x00000004
92# define MAC_LOOPBACK 0x00000002
93# define MAC_FDX 0x00000001
94#define CPMAC_MAC_STATUS 0x0164
95# define MAC_STATUS_QOS 0x00000004
96# define MAC_STATUS_RXFLOW 0x00000002
97# define MAC_STATUS_TXFLOW 0x00000001
98#define CPMAC_TX_INT_ENABLE 0x0178
99#define CPMAC_TX_INT_CLEAR 0x017c
100#define CPMAC_MAC_INT_VECTOR 0x0180
101# define MAC_INT_STATUS 0x00080000
102# define MAC_INT_HOST 0x00040000
103# define MAC_INT_RX 0x00020000
104# define MAC_INT_TX 0x00010000
105#define CPMAC_MAC_EOI_VECTOR 0x0184
106#define CPMAC_RX_INT_ENABLE 0x0198
107#define CPMAC_RX_INT_CLEAR 0x019c
108#define CPMAC_MAC_INT_ENABLE 0x01a8
109#define CPMAC_MAC_INT_CLEAR 0x01ac
110#define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
111#define CPMAC_MAC_ADDR_MID 0x01d0
112#define CPMAC_MAC_ADDR_HI 0x01d4
113#define CPMAC_MAC_HASH_LO 0x01d8
114#define CPMAC_MAC_HASH_HI 0x01dc
115#define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
116#define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
117#define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
118#define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
119#define CPMAC_REG_END 0x0680
120/*
121 * Rx/Tx statistics
122 * TODO: use some of them to fill stats in cpmac_stats()
123 */
124#define CPMAC_STATS_RX_GOOD 0x0200
125#define CPMAC_STATS_RX_BCAST 0x0204
126#define CPMAC_STATS_RX_MCAST 0x0208
127#define CPMAC_STATS_RX_PAUSE 0x020c
128#define CPMAC_STATS_RX_CRC 0x0210
129#define CPMAC_STATS_RX_ALIGN 0x0214
130#define CPMAC_STATS_RX_OVER 0x0218
131#define CPMAC_STATS_RX_JABBER 0x021c
132#define CPMAC_STATS_RX_UNDER 0x0220
133#define CPMAC_STATS_RX_FRAG 0x0224
134#define CPMAC_STATS_RX_FILTER 0x0228
135#define CPMAC_STATS_RX_QOSFILTER 0x022c
136#define CPMAC_STATS_RX_OCTETS 0x0230
137
138#define CPMAC_STATS_TX_GOOD 0x0234
139#define CPMAC_STATS_TX_BCAST 0x0238
140#define CPMAC_STATS_TX_MCAST 0x023c
141#define CPMAC_STATS_TX_PAUSE 0x0240
142#define CPMAC_STATS_TX_DEFER 0x0244
143#define CPMAC_STATS_TX_COLLISION 0x0248
144#define CPMAC_STATS_TX_SINGLECOLL 0x024c
145#define CPMAC_STATS_TX_MULTICOLL 0x0250
146#define CPMAC_STATS_TX_EXCESSCOLL 0x0254
147#define CPMAC_STATS_TX_LATECOLL 0x0258
148#define CPMAC_STATS_TX_UNDERRUN 0x025c
149#define CPMAC_STATS_TX_CARRIERSENSE 0x0260
150#define CPMAC_STATS_TX_OCTETS 0x0264
151
152#define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
153#define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
154 (reg)))
155
156/* MDIO bus */
157#define CPMAC_MDIO_VERSION 0x0000
158#define CPMAC_MDIO_CONTROL 0x0004
159# define MDIOC_IDLE 0x80000000
160# define MDIOC_ENABLE 0x40000000
161# define MDIOC_PREAMBLE 0x00100000
162# define MDIOC_FAULT 0x00080000
163# define MDIOC_FAULTDETECT 0x00040000
164# define MDIOC_INTTEST 0x00020000
165# define MDIOC_CLKDIV(div) ((div) & 0xff)
166#define CPMAC_MDIO_ALIVE 0x0008
167#define CPMAC_MDIO_LINK 0x000c
168#define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
169# define MDIO_BUSY 0x80000000
170# define MDIO_WRITE 0x40000000
171# define MDIO_REG(reg) (((reg) & 0x1f) << 21)
172# define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
173# define MDIO_DATA(data) ((data) & 0xffff)
174#define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
175# define PHYSEL_LINKSEL 0x00000040
176# define PHYSEL_LINKINT 0x00000020
177
178struct cpmac_desc {
179 u32 hw_next;
180 u32 hw_data;
181 u16 buflen;
182 u16 bufflags;
183 u16 datalen;
184 u16 dataflags;
185#define CPMAC_SOP 0x8000
186#define CPMAC_EOP 0x4000
187#define CPMAC_OWN 0x2000
188#define CPMAC_EOQ 0x1000
189 struct sk_buff *skb;
190 struct cpmac_desc *next;
191 struct cpmac_desc *prev;
192 dma_addr_t mapping;
193 dma_addr_t data_mapping;
194};
195
196struct cpmac_priv {
197 spinlock_t lock;
198 spinlock_t rx_lock;
199 struct cpmac_desc *rx_head;
200 int ring_size;
201 struct cpmac_desc *desc_ring;
202 dma_addr_t dma_ring;
203 void __iomem *regs;
204 struct mii_bus *mii_bus;
205 struct phy_device *phy;
206 char phy_name[MII_BUS_ID_SIZE + 3];
207 int oldlink, oldspeed, oldduplex;
208 u32 msg_enable;
209 struct net_device *dev;
210 struct work_struct reset_work;
211 struct platform_device *pdev;
212 struct napi_struct napi;
213 atomic_t reset_pending;
214};
215
216static irqreturn_t cpmac_irq(int, void *);
217static void cpmac_hw_start(struct net_device *dev);
218static void cpmac_hw_stop(struct net_device *dev);
219static int cpmac_stop(struct net_device *dev);
220static int cpmac_open(struct net_device *dev);
221
222static void cpmac_dump_regs(struct net_device *dev)
223{
224 int i;
225 struct cpmac_priv *priv = netdev_priv(dev);
226 for (i = 0; i < CPMAC_REG_END; i += 4) {
227 if (i % 16 == 0) {
228 if (i)
229 printk("\n");
230 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
231 priv->regs + i);
232 }
233 printk(" %08x", cpmac_read(priv->regs, i));
234 }
235 printk("\n");
236}
237
238static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
239{
240 int i;
241 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
242 for (i = 0; i < sizeof(*desc) / 4; i++)
243 printk(" %08x", ((u32 *)desc)[i]);
244 printk("\n");
245}
246
247static void cpmac_dump_all_desc(struct net_device *dev)
248{
249 struct cpmac_priv *priv = netdev_priv(dev);
250 struct cpmac_desc *dump = priv->rx_head;
251 do {
252 cpmac_dump_desc(dev, dump);
253 dump = dump->next;
254 } while (dump != priv->rx_head);
255}
256
257static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
258{
259 int i;
260 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
261 for (i = 0; i < skb->len; i++) {
262 if (i % 16 == 0) {
263 if (i)
264 printk("\n");
265 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
266 skb->data + i);
267 }
268 printk(" %02x", ((u8 *)skb->data)[i]);
269 }
270 printk("\n");
271}
272
273static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
274{
275 u32 val;
276
277 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
278 cpu_relax();
279 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
280 MDIO_PHY(phy_id));
281 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
282 cpu_relax();
283 return MDIO_DATA(val);
284}
285
286static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
287 int reg, u16 val)
288{
289 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
290 cpu_relax();
291 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
292 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
293 return 0;
294}
295
296static int cpmac_mdio_reset(struct mii_bus *bus)
297{
298 struct clk *cpmac_clk;
299
300 cpmac_clk = clk_get(&bus->dev, "cpmac");
301 if (IS_ERR(cpmac_clk)) {
302 printk(KERN_ERR "unable to get cpmac clock\n");
303 return -1;
304 }
305 ar7_device_reset(AR7_RESET_BIT_MDIO);
306 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
307 MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
308 return 0;
309}
310
311static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
312
313static struct mii_bus *cpmac_mii;
314
315static int cpmac_config(struct net_device *dev, struct ifmap *map)
316{
317 if (dev->flags & IFF_UP)
318 return -EBUSY;
319
320 /* Don't allow changing the I/O address */
321 if (map->base_addr != dev->base_addr)
322 return -EOPNOTSUPP;
323
324 /* ignore other fields */
325 return 0;
326}
327
328static void cpmac_set_multicast_list(struct net_device *dev)
329{
330 struct dev_mc_list *iter;
331 u8 tmp;
332 u32 mbp, bit, hash[2] = { 0, };
333 struct cpmac_priv *priv = netdev_priv(dev);
334
335 mbp = cpmac_read(priv->regs, CPMAC_MBP);
336 if (dev->flags & IFF_PROMISC) {
337 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
338 MBP_RXPROMISC);
339 } else {
340 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
341 if (dev->flags & IFF_ALLMULTI) {
342 /* enable all multicast mode */
343 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
344 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
345 } else {
346 /*
347 * cpmac uses some strange mac address hashing
348 * (not crc32)
349 */
350 netdev_for_each_mc_addr(iter, dev) {
351 bit = 0;
352 tmp = iter->dmi_addr[0];
353 bit ^= (tmp >> 2) ^ (tmp << 4);
354 tmp = iter->dmi_addr[1];
355 bit ^= (tmp >> 4) ^ (tmp << 2);
356 tmp = iter->dmi_addr[2];
357 bit ^= (tmp >> 6) ^ tmp;
358 tmp = iter->dmi_addr[3];
359 bit ^= (tmp >> 2) ^ (tmp << 4);
360 tmp = iter->dmi_addr[4];
361 bit ^= (tmp >> 4) ^ (tmp << 2);
362 tmp = iter->dmi_addr[5];
363 bit ^= (tmp >> 6) ^ tmp;
364 bit &= 0x3f;
365 hash[bit / 32] |= 1 << (bit % 32);
366 }
367
368 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
369 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
370 }
371 }
372}
373
374static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
375 struct cpmac_desc *desc)
376{
377 struct sk_buff *skb, *result = NULL;
378
379 if (unlikely(netif_msg_hw(priv)))
380 cpmac_dump_desc(priv->dev, desc);
381 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
382 if (unlikely(!desc->datalen)) {
383 if (netif_msg_rx_err(priv) && net_ratelimit())
384 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
385 priv->dev->name);
386 return NULL;
387 }
388
389 skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
390 if (likely(skb)) {
391 skb_put(desc->skb, desc->datalen);
392 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
393 desc->skb->ip_summed = CHECKSUM_NONE;
394 priv->dev->stats.rx_packets++;
395 priv->dev->stats.rx_bytes += desc->datalen;
396 result = desc->skb;
397 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
398 CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
399 desc->skb = skb;
400 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
401 CPMAC_SKB_SIZE,
402 DMA_FROM_DEVICE);
403 desc->hw_data = (u32)desc->data_mapping;
404 if (unlikely(netif_msg_pktdata(priv))) {
405 printk(KERN_DEBUG "%s: received packet:\n",
406 priv->dev->name);
407 cpmac_dump_skb(priv->dev, result);
408 }
409 } else {
410 if (netif_msg_rx_err(priv) && net_ratelimit())
411 printk(KERN_WARNING
412 "%s: low on skbs, dropping packet\n",
413 priv->dev->name);
414 priv->dev->stats.rx_dropped++;
415 }
416
417 desc->buflen = CPMAC_SKB_SIZE;
418 desc->dataflags = CPMAC_OWN;
419
420 return result;
421}
422
423static int cpmac_poll(struct napi_struct *napi, int budget)
424{
425 struct sk_buff *skb;
426 struct cpmac_desc *desc, *restart;
427 struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
428 int received = 0, processed = 0;
429
430 spin_lock(&priv->rx_lock);
431 if (unlikely(!priv->rx_head)) {
432 if (netif_msg_rx_err(priv) && net_ratelimit())
433 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
434 priv->dev->name);
435 spin_unlock(&priv->rx_lock);
436 napi_complete(napi);
437 return 0;
438 }
439
440 desc = priv->rx_head;
441 restart = NULL;
442 while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
443 processed++;
444
445 if ((desc->dataflags & CPMAC_EOQ) != 0) {
446 /* The last update to eoq->hw_next didn't happen
447 * soon enough, and the receiver stopped here.
448 *Remember this descriptor so we can restart
449 * the receiver after freeing some space.
450 */
451 if (unlikely(restart)) {
452 if (netif_msg_rx_err(priv))
453 printk(KERN_ERR "%s: poll found a"
454 " duplicate EOQ: %p and %p\n",
455 priv->dev->name, restart, desc);
456 goto fatal_error;
457 }
458
459 restart = desc->next;
460 }
461
462 skb = cpmac_rx_one(priv, desc);
463 if (likely(skb)) {
464 netif_receive_skb(skb);
465 received++;
466 }
467 desc = desc->next;
468 }
469
470 if (desc != priv->rx_head) {
471 /* We freed some buffers, but not the whole ring,
472 * add what we did free to the rx list */
473 desc->prev->hw_next = (u32)0;
474 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
475 }
476
477 /* Optimization: If we did not actually process an EOQ (perhaps because
478 * of quota limits), check to see if the tail of the queue has EOQ set.
479 * We should immediately restart in that case so that the receiver can
480 * restart and run in parallel with more packet processing.
481 * This lets us handle slightly larger bursts before running
482 * out of ring space (assuming dev->weight < ring_size) */
483
484 if (!restart &&
485 (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
486 == CPMAC_EOQ &&
487 (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
488 /* reset EOQ so the poll loop (above) doesn't try to
489 * restart this when it eventually gets to this descriptor.
490 */
491 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
492 restart = priv->rx_head;
493 }
494
495 if (restart) {
496 priv->dev->stats.rx_errors++;
497 priv->dev->stats.rx_fifo_errors++;
498 if (netif_msg_rx_err(priv) && net_ratelimit())
499 printk(KERN_WARNING "%s: rx dma ring overrun\n",
500 priv->dev->name);
501
502 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
503 if (netif_msg_drv(priv))
504 printk(KERN_ERR "%s: cpmac_poll is trying to "
505 "restart rx from a descriptor that's "
506 "not free: %p\n",
507 priv->dev->name, restart);
508 goto fatal_error;
509 }
510
511 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
512 }
513
514 priv->rx_head = desc;
515 spin_unlock(&priv->rx_lock);
516 if (unlikely(netif_msg_rx_status(priv)))
517 printk(KERN_DEBUG "%s: poll processed %d packets\n",
518 priv->dev->name, received);
519 if (processed == 0) {
520 /* we ran out of packets to read,
521 * revert to interrupt-driven mode */
522 napi_complete(napi);
523 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
524 return 0;
525 }
526
527 return 1;
528
529fatal_error:
530 /* Something went horribly wrong.
531 * Reset hardware to try to recover rather than wedging. */
532
533 if (netif_msg_drv(priv)) {
534 printk(KERN_ERR "%s: cpmac_poll is confused. "
535 "Resetting hardware\n", priv->dev->name);
536 cpmac_dump_all_desc(priv->dev);
537 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
538 priv->dev->name,
539 cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
540 cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
541 }
542
543 spin_unlock(&priv->rx_lock);
544 napi_complete(napi);
545 netif_tx_stop_all_queues(priv->dev);
546 napi_disable(&priv->napi);
547
548 atomic_inc(&priv->reset_pending);
549 cpmac_hw_stop(priv->dev);
550 if (!schedule_work(&priv->reset_work))
551 atomic_dec(&priv->reset_pending);
552 return 0;
553
554}
555
556static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
557{
558 int queue, len;
559 struct cpmac_desc *desc;
560 struct cpmac_priv *priv = netdev_priv(dev);
561
562 if (unlikely(atomic_read(&priv->reset_pending)))
563 return NETDEV_TX_BUSY;
564
565 if (unlikely(skb_padto(skb, ETH_ZLEN)))
566 return NETDEV_TX_OK;
567
568 len = max(skb->len, ETH_ZLEN);
569 queue = skb_get_queue_mapping(skb);
570 netif_stop_subqueue(dev, queue);
571
572 desc = &priv->desc_ring[queue];
573 if (unlikely(desc->dataflags & CPMAC_OWN)) {
574 if (netif_msg_tx_err(priv) && net_ratelimit())
575 printk(KERN_WARNING "%s: tx dma ring full\n",
576 dev->name);
577 return NETDEV_TX_BUSY;
578 }
579
580 spin_lock(&priv->lock);
581 dev->trans_start = jiffies;
582 spin_unlock(&priv->lock);
583 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
584 desc->skb = skb;
585 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
586 DMA_TO_DEVICE);
587 desc->hw_data = (u32)desc->data_mapping;
588 desc->datalen = len;
589 desc->buflen = len;
590 if (unlikely(netif_msg_tx_queued(priv)))
591 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
592 skb->len);
593 if (unlikely(netif_msg_hw(priv)))
594 cpmac_dump_desc(dev, desc);
595 if (unlikely(netif_msg_pktdata(priv)))
596 cpmac_dump_skb(dev, skb);
597 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
598
599 return NETDEV_TX_OK;
600}
601
602static void cpmac_end_xmit(struct net_device *dev, int queue)
603{
604 struct cpmac_desc *desc;
605 struct cpmac_priv *priv = netdev_priv(dev);
606
607 desc = &priv->desc_ring[queue];
608 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
609 if (likely(desc->skb)) {
610 spin_lock(&priv->lock);
611 dev->stats.tx_packets++;
612 dev->stats.tx_bytes += desc->skb->len;
613 spin_unlock(&priv->lock);
614 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
615 DMA_TO_DEVICE);
616
617 if (unlikely(netif_msg_tx_done(priv)))
618 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
619 desc->skb, desc->skb->len);
620
621 dev_kfree_skb_irq(desc->skb);
622 desc->skb = NULL;
623 if (__netif_subqueue_stopped(dev, queue))
624 netif_wake_subqueue(dev, queue);
625 } else {
626 if (netif_msg_tx_err(priv) && net_ratelimit())
627 printk(KERN_WARNING
628 "%s: end_xmit: spurious interrupt\n", dev->name);
629 if (__netif_subqueue_stopped(dev, queue))
630 netif_wake_subqueue(dev, queue);
631 }
632}
633
634static void cpmac_hw_stop(struct net_device *dev)
635{
636 int i;
637 struct cpmac_priv *priv = netdev_priv(dev);
638 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
639
640 ar7_device_reset(pdata->reset_bit);
641 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
642 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
643 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
644 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
645 for (i = 0; i < 8; i++) {
646 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
647 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
648 }
649 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
650 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
651 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
652 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
653 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
654 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
655}
656
657static void cpmac_hw_start(struct net_device *dev)
658{
659 int i;
660 struct cpmac_priv *priv = netdev_priv(dev);
661 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
662
663 ar7_device_reset(pdata->reset_bit);
664 for (i = 0; i < 8; i++) {
665 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
666 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
667 }
668 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
669
670 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
671 MBP_RXMCAST);
672 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
673 for (i = 0; i < 8; i++)
674 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
675 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
676 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
677 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
678 (dev->dev_addr[3] << 24));
679 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
680 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
681 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
682 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
683 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
684 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
685 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
686 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
687 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
688
689 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
690 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
691 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
692 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
693 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
694 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
695 MAC_FDX);
696}
697
698static void cpmac_clear_rx(struct net_device *dev)
699{
700 struct cpmac_priv *priv = netdev_priv(dev);
701 struct cpmac_desc *desc;
702 int i;
703 if (unlikely(!priv->rx_head))
704 return;
705 desc = priv->rx_head;
706 for (i = 0; i < priv->ring_size; i++) {
707 if ((desc->dataflags & CPMAC_OWN) == 0) {
708 if (netif_msg_rx_err(priv) && net_ratelimit())
709 printk(KERN_WARNING "%s: packet dropped\n",
710 dev->name);
711 if (unlikely(netif_msg_hw(priv)))
712 cpmac_dump_desc(dev, desc);
713 desc->dataflags = CPMAC_OWN;
714 dev->stats.rx_dropped++;
715 }
716 desc->hw_next = desc->next->mapping;
717 desc = desc->next;
718 }
719 priv->rx_head->prev->hw_next = 0;
720}
721
722static void cpmac_clear_tx(struct net_device *dev)
723{
724 struct cpmac_priv *priv = netdev_priv(dev);
725 int i;
726 if (unlikely(!priv->desc_ring))
727 return;
728 for (i = 0; i < CPMAC_QUEUES; i++) {
729 priv->desc_ring[i].dataflags = 0;
730 if (priv->desc_ring[i].skb) {
731 dev_kfree_skb_any(priv->desc_ring[i].skb);
732 priv->desc_ring[i].skb = NULL;
733 }
734 }
735}
736
737static void cpmac_hw_error(struct work_struct *work)
738{
739 struct cpmac_priv *priv =
740 container_of(work, struct cpmac_priv, reset_work);
741
742 spin_lock(&priv->rx_lock);
743 cpmac_clear_rx(priv->dev);
744 spin_unlock(&priv->rx_lock);
745 cpmac_clear_tx(priv->dev);
746 cpmac_hw_start(priv->dev);
747 barrier();
748 atomic_dec(&priv->reset_pending);
749
750 netif_tx_wake_all_queues(priv->dev);
751 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
752}
753
754static void cpmac_check_status(struct net_device *dev)
755{
756 struct cpmac_priv *priv = netdev_priv(dev);
757
758 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
759 int rx_channel = (macstatus >> 8) & 7;
760 int rx_code = (macstatus >> 12) & 15;
761 int tx_channel = (macstatus >> 16) & 7;
762 int tx_code = (macstatus >> 20) & 15;
763
764 if (rx_code || tx_code) {
765 if (netif_msg_drv(priv) && net_ratelimit()) {
766 /* Can't find any documentation on what these
767 *error codes actually are. So just log them and hope..
768 */
769 if (rx_code)
770 printk(KERN_WARNING "%s: host error %d on rx "
771 "channel %d (macstatus %08x), resetting\n",
772 dev->name, rx_code, rx_channel, macstatus);
773 if (tx_code)
774 printk(KERN_WARNING "%s: host error %d on tx "
775 "channel %d (macstatus %08x), resetting\n",
776 dev->name, tx_code, tx_channel, macstatus);
777 }
778
779 netif_tx_stop_all_queues(dev);
780 cpmac_hw_stop(dev);
781 if (schedule_work(&priv->reset_work))
782 atomic_inc(&priv->reset_pending);
783 if (unlikely(netif_msg_hw(priv)))
784 cpmac_dump_regs(dev);
785 }
786 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
787}
788
789static irqreturn_t cpmac_irq(int irq, void *dev_id)
790{
791 struct net_device *dev = dev_id;
792 struct cpmac_priv *priv;
793 int queue;
794 u32 status;
795
796 priv = netdev_priv(dev);
797
798 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
799
800 if (unlikely(netif_msg_intr(priv)))
801 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
802 status);
803
804 if (status & MAC_INT_TX)
805 cpmac_end_xmit(dev, (status & 7));
806
807 if (status & MAC_INT_RX) {
808 queue = (status >> 8) & 7;
809 if (napi_schedule_prep(&priv->napi)) {
810 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
811 __napi_schedule(&priv->napi);
812 }
813 }
814
815 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
816
817 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
818 cpmac_check_status(dev);
819
820 return IRQ_HANDLED;
821}
822
823static void cpmac_tx_timeout(struct net_device *dev)
824{
825 struct cpmac_priv *priv = netdev_priv(dev);
826
827 spin_lock(&priv->lock);
828 dev->stats.tx_errors++;
829 spin_unlock(&priv->lock);
830 if (netif_msg_tx_err(priv) && net_ratelimit())
831 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
832
833 atomic_inc(&priv->reset_pending);
834 barrier();
835 cpmac_clear_tx(dev);
836 barrier();
837 atomic_dec(&priv->reset_pending);
838
839 netif_tx_wake_all_queues(priv->dev);
840}
841
842static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
843{
844 struct cpmac_priv *priv = netdev_priv(dev);
845 if (!(netif_running(dev)))
846 return -EINVAL;
847 if (!priv->phy)
848 return -EINVAL;
849 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
850 (cmd == SIOCSMIIREG))
851 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
852
853 return -EOPNOTSUPP;
854}
855
856static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
857{
858 struct cpmac_priv *priv = netdev_priv(dev);
859
860 if (priv->phy)
861 return phy_ethtool_gset(priv->phy, cmd);
862
863 return -EINVAL;
864}
865
866static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
867{
868 struct cpmac_priv *priv = netdev_priv(dev);
869
870 if (!capable(CAP_NET_ADMIN))
871 return -EPERM;
872
873 if (priv->phy)
874 return phy_ethtool_sset(priv->phy, cmd);
875
876 return -EINVAL;
877}
878
879static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
880{
881 struct cpmac_priv *priv = netdev_priv(dev);
882
883 ring->rx_max_pending = 1024;
884 ring->rx_mini_max_pending = 1;
885 ring->rx_jumbo_max_pending = 1;
886 ring->tx_max_pending = 1;
887
888 ring->rx_pending = priv->ring_size;
889 ring->rx_mini_pending = 1;
890 ring->rx_jumbo_pending = 1;
891 ring->tx_pending = 1;
892}
893
894static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
895{
896 struct cpmac_priv *priv = netdev_priv(dev);
897
898 if (netif_running(dev))
899 return -EBUSY;
900 priv->ring_size = ring->rx_pending;
901 return 0;
902}
903
904static void cpmac_get_drvinfo(struct net_device *dev,
905 struct ethtool_drvinfo *info)
906{
907 strcpy(info->driver, "cpmac");
908 strcpy(info->version, CPMAC_VERSION);
909 info->fw_version[0] = '\0';
910 sprintf(info->bus_info, "%s", "cpmac");
911 info->regdump_len = 0;
912}
913
914static const struct ethtool_ops cpmac_ethtool_ops = {
915 .get_settings = cpmac_get_settings,
916 .set_settings = cpmac_set_settings,
917 .get_drvinfo = cpmac_get_drvinfo,
918 .get_link = ethtool_op_get_link,
919 .get_ringparam = cpmac_get_ringparam,
920 .set_ringparam = cpmac_set_ringparam,
921};
922
923static void cpmac_adjust_link(struct net_device *dev)
924{
925 struct cpmac_priv *priv = netdev_priv(dev);
926 int new_state = 0;
927
928 spin_lock(&priv->lock);
929 if (priv->phy->link) {
930 netif_tx_start_all_queues(dev);
931 if (priv->phy->duplex != priv->oldduplex) {
932 new_state = 1;
933 priv->oldduplex = priv->phy->duplex;
934 }
935
936 if (priv->phy->speed != priv->oldspeed) {
937 new_state = 1;
938 priv->oldspeed = priv->phy->speed;
939 }
940
941 if (!priv->oldlink) {
942 new_state = 1;
943 priv->oldlink = 1;
944 }
945 } else if (priv->oldlink) {
946 new_state = 1;
947 priv->oldlink = 0;
948 priv->oldspeed = 0;
949 priv->oldduplex = -1;
950 }
951
952 if (new_state && netif_msg_link(priv) && net_ratelimit())
953 phy_print_status(priv->phy);
954
955 spin_unlock(&priv->lock);
956}
957
958static int cpmac_open(struct net_device *dev)
959{
960 int i, size, res;
961 struct cpmac_priv *priv = netdev_priv(dev);
962 struct resource *mem;
963 struct cpmac_desc *desc;
964 struct sk_buff *skb;
965
966 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
967 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
968 if (netif_msg_drv(priv))
969 printk(KERN_ERR "%s: failed to request registers\n",
970 dev->name);
971 res = -ENXIO;
972 goto fail_reserve;
973 }
974
975 priv->regs = ioremap(mem->start, mem->end - mem->start);
976 if (!priv->regs) {
977 if (netif_msg_drv(priv))
978 printk(KERN_ERR "%s: failed to remap registers\n",
979 dev->name);
980 res = -ENXIO;
981 goto fail_remap;
982 }
983
984 size = priv->ring_size + CPMAC_QUEUES;
985 priv->desc_ring = dma_alloc_coherent(&dev->dev,
986 sizeof(struct cpmac_desc) * size,
987 &priv->dma_ring,
988 GFP_KERNEL);
989 if (!priv->desc_ring) {
990 res = -ENOMEM;
991 goto fail_alloc;
992 }
993
994 for (i = 0; i < size; i++)
995 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
996
997 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
998 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
999 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
1000 if (unlikely(!skb)) {
1001 res = -ENOMEM;
1002 goto fail_desc;
1003 }
1004 desc->skb = skb;
1005 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
1006 CPMAC_SKB_SIZE,
1007 DMA_FROM_DEVICE);
1008 desc->hw_data = (u32)desc->data_mapping;
1009 desc->buflen = CPMAC_SKB_SIZE;
1010 desc->dataflags = CPMAC_OWN;
1011 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1012 desc->next->prev = desc;
1013 desc->hw_next = (u32)desc->next->mapping;
1014 }
1015
1016 priv->rx_head->prev->hw_next = (u32)0;
1017
1018 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
1019 dev->name, dev))) {
1020 if (netif_msg_drv(priv))
1021 printk(KERN_ERR "%s: failed to obtain irq\n",
1022 dev->name);
1023 goto fail_irq;
1024 }
1025
1026 atomic_set(&priv->reset_pending, 0);
1027 INIT_WORK(&priv->reset_work, cpmac_hw_error);
1028 cpmac_hw_start(dev);
1029
1030 napi_enable(&priv->napi);
1031 priv->phy->state = PHY_CHANGELINK;
1032 phy_start(priv->phy);
1033
1034 return 0;
1035
1036fail_irq:
1037fail_desc:
1038 for (i = 0; i < priv->ring_size; i++) {
1039 if (priv->rx_head[i].skb) {
1040 dma_unmap_single(&dev->dev,
1041 priv->rx_head[i].data_mapping,
1042 CPMAC_SKB_SIZE,
1043 DMA_FROM_DEVICE);
1044 kfree_skb(priv->rx_head[i].skb);
1045 }
1046 }
1047fail_alloc:
1048 kfree(priv->desc_ring);
1049 iounmap(priv->regs);
1050
1051fail_remap:
1052 release_mem_region(mem->start, mem->end - mem->start);
1053
1054fail_reserve:
1055 return res;
1056}
1057
1058static int cpmac_stop(struct net_device *dev)
1059{
1060 int i;
1061 struct cpmac_priv *priv = netdev_priv(dev);
1062 struct resource *mem;
1063
1064 netif_tx_stop_all_queues(dev);
1065
1066 cancel_work_sync(&priv->reset_work);
1067 napi_disable(&priv->napi);
1068 phy_stop(priv->phy);
1069
1070 cpmac_hw_stop(dev);
1071
1072 for (i = 0; i < 8; i++)
1073 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1074 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1075 cpmac_write(priv->regs, CPMAC_MBP, 0);
1076
1077 free_irq(dev->irq, dev);
1078 iounmap(priv->regs);
1079 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1080 release_mem_region(mem->start, mem->end - mem->start);
1081 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1082 for (i = 0; i < priv->ring_size; i++) {
1083 if (priv->rx_head[i].skb) {
1084 dma_unmap_single(&dev->dev,
1085 priv->rx_head[i].data_mapping,
1086 CPMAC_SKB_SIZE,
1087 DMA_FROM_DEVICE);
1088 kfree_skb(priv->rx_head[i].skb);
1089 }
1090 }
1091
1092 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1093 (CPMAC_QUEUES + priv->ring_size),
1094 priv->desc_ring, priv->dma_ring);
1095 return 0;
1096}
1097
1098static const struct net_device_ops cpmac_netdev_ops = {
1099 .ndo_open = cpmac_open,
1100 .ndo_stop = cpmac_stop,
1101 .ndo_start_xmit = cpmac_start_xmit,
1102 .ndo_tx_timeout = cpmac_tx_timeout,
1103 .ndo_set_multicast_list = cpmac_set_multicast_list,
1104 .ndo_do_ioctl = cpmac_ioctl,
1105 .ndo_set_config = cpmac_config,
1106 .ndo_change_mtu = eth_change_mtu,
1107 .ndo_validate_addr = eth_validate_addr,
1108 .ndo_set_mac_address = eth_mac_addr,
1109};
1110
1111static int external_switch;
1112
1113static int __devinit cpmac_probe(struct platform_device *pdev)
1114{
1115 int rc, phy_id;
1116 char mdio_bus_id[MII_BUS_ID_SIZE];
1117 struct resource *mem;
1118 struct cpmac_priv *priv;
1119 struct net_device *dev;
1120 struct plat_cpmac_data *pdata;
1121
1122 pdata = pdev->dev.platform_data;
1123
1124 if (external_switch || dumb_switch) {
1125 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
1126 phy_id = pdev->id;
1127 } else {
1128 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1129 if (!(pdata->phy_mask & (1 << phy_id)))
1130 continue;
1131 if (!cpmac_mii->phy_map[phy_id])
1132 continue;
1133 strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1134 break;
1135 }
1136 }
1137
1138 if (phy_id == PHY_MAX_ADDR) {
1139 dev_err(&pdev->dev, "no PHY present\n");
1140 return -ENODEV;
1141 }
1142
1143 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1144
1145 if (!dev) {
1146 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1147 return -ENOMEM;
1148 }
1149
1150 platform_set_drvdata(pdev, dev);
1151 priv = netdev_priv(dev);
1152
1153 priv->pdev = pdev;
1154 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1155 if (!mem) {
1156 rc = -ENODEV;
1157 goto fail;
1158 }
1159
1160 dev->irq = platform_get_irq_byname(pdev, "irq");
1161
1162 dev->netdev_ops = &cpmac_netdev_ops;
1163 dev->ethtool_ops = &cpmac_ethtool_ops;
1164
1165 netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1166
1167 spin_lock_init(&priv->lock);
1168 spin_lock_init(&priv->rx_lock);
1169 priv->dev = dev;
1170 priv->ring_size = 64;
1171 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1172 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1173
1174 snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
1175
1176 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
1177 PHY_INTERFACE_MODE_MII);
1178
1179 if (IS_ERR(priv->phy)) {
1180 if (netif_msg_drv(priv))
1181 printk(KERN_ERR "%s: Could not attach to PHY\n",
1182 dev->name);
1183 return PTR_ERR(priv->phy);
1184 }
1185
1186 if ((rc = register_netdev(dev))) {
1187 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1188 dev->name);
1189 goto fail;
1190 }
1191
1192 if (netif_msg_probe(priv)) {
1193 printk(KERN_INFO
1194 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1195 "mac: %pM)\n", dev->name, (void *)mem->start, dev->irq,
1196 priv->phy_name, dev->dev_addr);
1197 }
1198 return 0;
1199
1200fail:
1201 free_netdev(dev);
1202 return rc;
1203}
1204
1205static int __devexit cpmac_remove(struct platform_device *pdev)
1206{
1207 struct net_device *dev = platform_get_drvdata(pdev);
1208 unregister_netdev(dev);
1209 free_netdev(dev);
1210 return 0;
1211}
1212
1213static struct platform_driver cpmac_driver = {
1214 .driver.name = "cpmac",
1215 .driver.owner = THIS_MODULE,
1216 .probe = cpmac_probe,
1217 .remove = __devexit_p(cpmac_remove),
1218};
1219
1220int __devinit cpmac_init(void)
1221{
1222 u32 mask;
1223 int i, res;
1224
1225 cpmac_mii = mdiobus_alloc();
1226 if (cpmac_mii == NULL)
1227 return -ENOMEM;
1228
1229 cpmac_mii->name = "cpmac-mii";
1230 cpmac_mii->read = cpmac_mdio_read;
1231 cpmac_mii->write = cpmac_mdio_write;
1232 cpmac_mii->reset = cpmac_mdio_reset;
1233 cpmac_mii->irq = mii_irqs;
1234
1235 cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1236
1237 if (!cpmac_mii->priv) {
1238 printk(KERN_ERR "Can't ioremap mdio registers\n");
1239 res = -ENXIO;
1240 goto fail_alloc;
1241 }
1242
1243#warning FIXME: unhardcode gpio&reset bits
1244 ar7_gpio_disable(26);
1245 ar7_gpio_disable(27);
1246 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1247 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1248 ar7_device_reset(AR7_RESET_BIT_EPHY);
1249
1250 cpmac_mii->reset(cpmac_mii);
1251
1252 for (i = 0; i < 300; i++)
1253 if ((mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE)))
1254 break;
1255 else
1256 msleep(10);
1257
1258 mask &= 0x7fffffff;
1259 if (mask & (mask - 1)) {
1260 external_switch = 1;
1261 mask = 0;
1262 }
1263
1264 cpmac_mii->phy_mask = ~(mask | 0x80000000);
1265 snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1");
1266
1267 res = mdiobus_register(cpmac_mii);
1268 if (res)
1269 goto fail_mii;
1270
1271 res = platform_driver_register(&cpmac_driver);
1272 if (res)
1273 goto fail_cpmac;
1274
1275 return 0;
1276
1277fail_cpmac:
1278 mdiobus_unregister(cpmac_mii);
1279
1280fail_mii:
1281 iounmap(cpmac_mii->priv);
1282
1283fail_alloc:
1284 mdiobus_free(cpmac_mii);
1285
1286 return res;
1287}
1288
1289void __devexit cpmac_exit(void)
1290{
1291 platform_driver_unregister(&cpmac_driver);
1292 mdiobus_unregister(cpmac_mii);
1293 mdiobus_free(cpmac_mii);
1294 iounmap(cpmac_mii->priv);
1295}
1296
1297module_init(cpmac_init);
1298module_exit(cpmac_exit);