tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / mfd / wm831x / core.h
at v2.6.33 310 lines 14 kB view raw
1/* 2 * include/linux/mfd/wm831x/core.h -- Core interface for WM831x 3 * 4 * Copyright 2009 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15#ifndef __MFD_WM831X_CORE_H__ 16#define __MFD_WM831X_CORE_H__ 17 18#include <linux/interrupt.h> 19 20/* 21 * Register values. 22 */ 23#define WM831X_RESET_ID 0x00 24#define WM831X_REVISION 0x01 25#define WM831X_PARENT_ID 0x4000 26#define WM831X_SYSVDD_CONTROL 0x4001 27#define WM831X_THERMAL_MONITORING 0x4002 28#define WM831X_POWER_STATE 0x4003 29#define WM831X_WATCHDOG 0x4004 30#define WM831X_ON_PIN_CONTROL 0x4005 31#define WM831X_RESET_CONTROL 0x4006 32#define WM831X_CONTROL_INTERFACE 0x4007 33#define WM831X_SECURITY_KEY 0x4008 34#define WM831X_SOFTWARE_SCRATCH 0x4009 35#define WM831X_OTP_CONTROL 0x400A 36#define WM831X_GPIO_LEVEL 0x400C 37#define WM831X_SYSTEM_STATUS 0x400D 38#define WM831X_ON_SOURCE 0x400E 39#define WM831X_OFF_SOURCE 0x400F 40#define WM831X_SYSTEM_INTERRUPTS 0x4010 41#define WM831X_INTERRUPT_STATUS_1 0x4011 42#define WM831X_INTERRUPT_STATUS_2 0x4012 43#define WM831X_INTERRUPT_STATUS_3 0x4013 44#define WM831X_INTERRUPT_STATUS_4 0x4014 45#define WM831X_INTERRUPT_STATUS_5 0x4015 46#define WM831X_IRQ_CONFIG 0x4017 47#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018 48#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019 49#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A 50#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B 51#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C 52#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D 53#define WM831X_RTC_WRITE_COUNTER 0x4020 54#define WM831X_RTC_TIME_1 0x4021 55#define WM831X_RTC_TIME_2 0x4022 56#define WM831X_RTC_ALARM_1 0x4023 57#define WM831X_RTC_ALARM_2 0x4024 58#define WM831X_RTC_CONTROL 0x4025 59#define WM831X_RTC_TRIM 0x4026 60#define WM831X_TOUCH_CONTROL_1 0x4028 61#define WM831X_TOUCH_CONTROL_2 0x4029 62#define WM831X_TOUCH_DATA_X 0x402A 63#define WM831X_TOUCH_DATA_Y 0x402B 64#define WM831X_TOUCH_DATA_Z 0x402C 65#define WM831X_AUXADC_DATA 0x402D 66#define WM831X_AUXADC_CONTROL 0x402E 67#define WM831X_AUXADC_SOURCE 0x402F 68#define WM831X_COMPARATOR_CONTROL 0x4030 69#define WM831X_COMPARATOR_1 0x4031 70#define WM831X_COMPARATOR_2 0x4032 71#define WM831X_COMPARATOR_3 0x4033 72#define WM831X_COMPARATOR_4 0x4034 73#define WM831X_GPIO1_CONTROL 0x4038 74#define WM831X_GPIO2_CONTROL 0x4039 75#define WM831X_GPIO3_CONTROL 0x403A 76#define WM831X_GPIO4_CONTROL 0x403B 77#define WM831X_GPIO5_CONTROL 0x403C 78#define WM831X_GPIO6_CONTROL 0x403D 79#define WM831X_GPIO7_CONTROL 0x403E 80#define WM831X_GPIO8_CONTROL 0x403F 81#define WM831X_GPIO9_CONTROL 0x4040 82#define WM831X_GPIO10_CONTROL 0x4041 83#define WM831X_GPIO11_CONTROL 0x4042 84#define WM831X_GPIO12_CONTROL 0x4043 85#define WM831X_GPIO13_CONTROL 0x4044 86#define WM831X_GPIO14_CONTROL 0x4045 87#define WM831X_GPIO15_CONTROL 0x4046 88#define WM831X_GPIO16_CONTROL 0x4047 89#define WM831X_CHARGER_CONTROL_1 0x4048 90#define WM831X_CHARGER_CONTROL_2 0x4049 91#define WM831X_CHARGER_STATUS 0x404A 92#define WM831X_BACKUP_CHARGER_CONTROL 0x404B 93#define WM831X_STATUS_LED_1 0x404C 94#define WM831X_STATUS_LED_2 0x404D 95#define WM831X_CURRENT_SINK_1 0x404E 96#define WM831X_CURRENT_SINK_2 0x404F 97#define WM831X_DCDC_ENABLE 0x4050 98#define WM831X_LDO_ENABLE 0x4051 99#define WM831X_DCDC_STATUS 0x4052 100#define WM831X_LDO_STATUS 0x4053 101#define WM831X_DCDC_UV_STATUS 0x4054 102#define WM831X_LDO_UV_STATUS 0x4055 103#define WM831X_DC1_CONTROL_1 0x4056 104#define WM831X_DC1_CONTROL_2 0x4057 105#define WM831X_DC1_ON_CONFIG 0x4058 106#define WM831X_DC1_SLEEP_CONTROL 0x4059 107#define WM831X_DC1_DVS_CONTROL 0x405A 108#define WM831X_DC2_CONTROL_1 0x405B 109#define WM831X_DC2_CONTROL_2 0x405C 110#define WM831X_DC2_ON_CONFIG 0x405D 111#define WM831X_DC2_SLEEP_CONTROL 0x405E 112#define WM831X_DC2_DVS_CONTROL 0x405F 113#define WM831X_DC3_CONTROL_1 0x4060 114#define WM831X_DC3_CONTROL_2 0x4061 115#define WM831X_DC3_ON_CONFIG 0x4062 116#define WM831X_DC3_SLEEP_CONTROL 0x4063 117#define WM831X_DC4_CONTROL 0x4064 118#define WM831X_DC4_SLEEP_CONTROL 0x4065 119#define WM832X_DC4_SLEEP_CONTROL 0x4067 120#define WM831X_EPE1_CONTROL 0x4066 121#define WM831X_EPE2_CONTROL 0x4067 122#define WM831X_LDO1_CONTROL 0x4068 123#define WM831X_LDO1_ON_CONTROL 0x4069 124#define WM831X_LDO1_SLEEP_CONTROL 0x406A 125#define WM831X_LDO2_CONTROL 0x406B 126#define WM831X_LDO2_ON_CONTROL 0x406C 127#define WM831X_LDO2_SLEEP_CONTROL 0x406D 128#define WM831X_LDO3_CONTROL 0x406E 129#define WM831X_LDO3_ON_CONTROL 0x406F 130#define WM831X_LDO3_SLEEP_CONTROL 0x4070 131#define WM831X_LDO4_CONTROL 0x4071 132#define WM831X_LDO4_ON_CONTROL 0x4072 133#define WM831X_LDO4_SLEEP_CONTROL 0x4073 134#define WM831X_LDO5_CONTROL 0x4074 135#define WM831X_LDO5_ON_CONTROL 0x4075 136#define WM831X_LDO5_SLEEP_CONTROL 0x4076 137#define WM831X_LDO6_CONTROL 0x4077 138#define WM831X_LDO6_ON_CONTROL 0x4078 139#define WM831X_LDO6_SLEEP_CONTROL 0x4079 140#define WM831X_LDO7_CONTROL 0x407A 141#define WM831X_LDO7_ON_CONTROL 0x407B 142#define WM831X_LDO7_SLEEP_CONTROL 0x407C 143#define WM831X_LDO8_CONTROL 0x407D 144#define WM831X_LDO8_ON_CONTROL 0x407E 145#define WM831X_LDO8_SLEEP_CONTROL 0x407F 146#define WM831X_LDO9_CONTROL 0x4080 147#define WM831X_LDO9_ON_CONTROL 0x4081 148#define WM831X_LDO9_SLEEP_CONTROL 0x4082 149#define WM831X_LDO10_CONTROL 0x4083 150#define WM831X_LDO10_ON_CONTROL 0x4084 151#define WM831X_LDO10_SLEEP_CONTROL 0x4085 152#define WM831X_LDO11_ON_CONTROL 0x4087 153#define WM831X_LDO11_SLEEP_CONTROL 0x4088 154#define WM831X_POWER_GOOD_SOURCE_1 0x408E 155#define WM831X_POWER_GOOD_SOURCE_2 0x408F 156#define WM831X_CLOCK_CONTROL_1 0x4090 157#define WM831X_CLOCK_CONTROL_2 0x4091 158#define WM831X_FLL_CONTROL_1 0x4092 159#define WM831X_FLL_CONTROL_2 0x4093 160#define WM831X_FLL_CONTROL_3 0x4094 161#define WM831X_FLL_CONTROL_4 0x4095 162#define WM831X_FLL_CONTROL_5 0x4096 163#define WM831X_UNIQUE_ID_1 0x7800 164#define WM831X_UNIQUE_ID_2 0x7801 165#define WM831X_UNIQUE_ID_3 0x7802 166#define WM831X_UNIQUE_ID_4 0x7803 167#define WM831X_UNIQUE_ID_5 0x7804 168#define WM831X_UNIQUE_ID_6 0x7805 169#define WM831X_UNIQUE_ID_7 0x7806 170#define WM831X_UNIQUE_ID_8 0x7807 171#define WM831X_FACTORY_OTP_ID 0x7808 172#define WM831X_FACTORY_OTP_1 0x7809 173#define WM831X_FACTORY_OTP_2 0x780A 174#define WM831X_FACTORY_OTP_3 0x780B 175#define WM831X_FACTORY_OTP_4 0x780C 176#define WM831X_FACTORY_OTP_5 0x780D 177#define WM831X_CUSTOMER_OTP_ID 0x7810 178#define WM831X_DC1_OTP_CONTROL 0x7811 179#define WM831X_DC2_OTP_CONTROL 0x7812 180#define WM831X_DC3_OTP_CONTROL 0x7813 181#define WM831X_LDO1_2_OTP_CONTROL 0x7814 182#define WM831X_LDO3_4_OTP_CONTROL 0x7815 183#define WM831X_LDO5_6_OTP_CONTROL 0x7816 184#define WM831X_LDO7_8_OTP_CONTROL 0x7817 185#define WM831X_LDO9_10_OTP_CONTROL 0x7818 186#define WM831X_LDO11_EPE_CONTROL 0x7819 187#define WM831X_GPIO1_OTP_CONTROL 0x781A 188#define WM831X_GPIO2_OTP_CONTROL 0x781B 189#define WM831X_GPIO3_OTP_CONTROL 0x781C 190#define WM831X_GPIO4_OTP_CONTROL 0x781D 191#define WM831X_GPIO5_OTP_CONTROL 0x781E 192#define WM831X_GPIO6_OTP_CONTROL 0x781F 193#define WM831X_DBE_CHECK_DATA 0x7827 194 195/* 196 * R0 (0x00) - Reset ID 197 */ 198#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */ 199#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */ 200#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */ 201 202/* 203 * R1 (0x01) - Revision 204 */ 205#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */ 206#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */ 207#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */ 208#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */ 209#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */ 210#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */ 211 212/* 213 * R16384 (0x4000) - Parent ID 214 */ 215#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */ 216#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */ 217#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */ 218 219/* 220 * R16389 (0x4005) - ON Pin Control 221 */ 222#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */ 223#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */ 224#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */ 225#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */ 226#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */ 227#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */ 228#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */ 229#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */ 230#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */ 231#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */ 232#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */ 233#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */ 234#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */ 235 236struct regulator_dev; 237 238#define WM831X_NUM_IRQ_REGS 5 239 240struct wm831x { 241 struct mutex io_lock; 242 243 struct device *dev; 244 int (*read_dev)(struct wm831x *wm831x, unsigned short reg, 245 int bytes, void *dest); 246 int (*write_dev)(struct wm831x *wm831x, unsigned short reg, 247 int bytes, void *src); 248 249 void *control_data; 250 251 int irq; /* Our chip IRQ */ 252 struct mutex irq_lock; 253 unsigned int irq_base; 254 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ 255 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 256 257 int num_gpio; 258 259 struct mutex auxadc_lock; 260 261 /* The WM831x has a security key blocking access to certain 262 * registers. The mutex is taken by the accessors for locking 263 * and unlocking the security key, locked is used to fail 264 * writes if the lock is held. 265 */ 266 struct mutex key_lock; 267 unsigned int locked:1; 268}; 269 270/* Device I/O API */ 271int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg); 272int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg, 273 unsigned short val); 274void wm831x_reg_lock(struct wm831x *wm831x); 275int wm831x_reg_unlock(struct wm831x *wm831x); 276int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg, 277 unsigned short mask, unsigned short val); 278int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, 279 int count, u16 *buf); 280 281int wm831x_irq_init(struct wm831x *wm831x, int irq); 282void wm831x_irq_exit(struct wm831x *wm831x); 283 284static inline int __must_check wm831x_request_irq(struct wm831x *wm831x, 285 unsigned int irq, 286 irq_handler_t handler, 287 unsigned long flags, 288 const char *name, 289 void *dev) 290{ 291 return request_threaded_irq(irq, NULL, handler, flags, name, dev); 292} 293 294static inline void wm831x_free_irq(struct wm831x *wm831x, 295 unsigned int irq, void *dev) 296{ 297 free_irq(irq, dev); 298} 299 300static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq) 301{ 302 disable_irq(irq); 303} 304 305static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq) 306{ 307 enable_irq(irq); 308} 309 310#endif