tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
23 *
24 */
25
26#include "netxen_nic.h"
27#include "netxen_nic_hw.h"
28
29#include <net/ip.h>
30
31#define MASK(n) ((1ULL<<(n))-1)
32#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34#define MS_WIN(addr) (addr & 0x0ffc0000)
35
36#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
37
38#define CRB_BLK(off) ((off >> 20) & 0x3f)
39#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
40#define CRB_WINDOW_2M (0x130060)
41#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
42#define CRB_INDIRECT_2M (0x1e0000UL)
43
44#ifndef readq
45static inline u64 readq(void __iomem *addr)
46{
47 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
48}
49#endif
50
51#ifndef writeq
52static inline void writeq(u64 val, void __iomem *addr)
53{
54 writel(((u32) (val)), (addr));
55 writel(((u32) (val >> 32)), (addr + 4));
56}
57#endif
58
59#define ADDR_IN_RANGE(addr, low, high) \
60 (((addr) < (high)) && ((addr) >= (low)))
61
62#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
63 ((adapter)->ahw.pci_base0 + (off))
64#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
65 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
66#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
67 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
68
69static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
70 unsigned long off)
71{
72 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
73 return PCI_OFFSET_FIRST_RANGE(adapter, off);
74
75 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
76 return PCI_OFFSET_SECOND_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
79 return PCI_OFFSET_THIRD_RANGE(adapter, off);
80
81 return NULL;
82}
83
84static crb_128M_2M_block_map_t
85crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
86 {{{0, 0, 0, 0} } }, /* 0: PCI */
87 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
88 {1, 0x0110000, 0x0120000, 0x130000},
89 {1, 0x0120000, 0x0122000, 0x124000},
90 {1, 0x0130000, 0x0132000, 0x126000},
91 {1, 0x0140000, 0x0142000, 0x128000},
92 {1, 0x0150000, 0x0152000, 0x12a000},
93 {1, 0x0160000, 0x0170000, 0x110000},
94 {1, 0x0170000, 0x0172000, 0x12e000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {1, 0x01e0000, 0x01e0800, 0x122000},
102 {0, 0x0000000, 0x0000000, 0x000000} } },
103 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
104 {{{0, 0, 0, 0} } }, /* 3: */
105 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
106 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
107 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
108 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
109 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x08f0000, 0x08f2000, 0x172000} } },
125 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x09f0000, 0x09f2000, 0x176000} } },
141 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
157 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
173 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
174 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
175 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
176 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
177 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
178 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
179 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
180 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
181 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
182 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
183 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
184 {{{0, 0, 0, 0} } }, /* 23: */
185 {{{0, 0, 0, 0} } }, /* 24: */
186 {{{0, 0, 0, 0} } }, /* 25: */
187 {{{0, 0, 0, 0} } }, /* 26: */
188 {{{0, 0, 0, 0} } }, /* 27: */
189 {{{0, 0, 0, 0} } }, /* 28: */
190 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
191 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
192 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
193 {{{0} } }, /* 32: PCI */
194 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
195 {1, 0x2110000, 0x2120000, 0x130000},
196 {1, 0x2120000, 0x2122000, 0x124000},
197 {1, 0x2130000, 0x2132000, 0x126000},
198 {1, 0x2140000, 0x2142000, 0x128000},
199 {1, 0x2150000, 0x2152000, 0x12a000},
200 {1, 0x2160000, 0x2170000, 0x110000},
201 {1, 0x2170000, 0x2172000, 0x12e000},
202 {0, 0x0000000, 0x0000000, 0x000000},
203 {0, 0x0000000, 0x0000000, 0x000000},
204 {0, 0x0000000, 0x0000000, 0x000000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000} } },
210 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
211 {{{0} } }, /* 35: */
212 {{{0} } }, /* 36: */
213 {{{0} } }, /* 37: */
214 {{{0} } }, /* 38: */
215 {{{0} } }, /* 39: */
216 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
217 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
218 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
219 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
220 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
221 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
222 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
223 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
224 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
225 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
226 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
227 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
228 {{{0} } }, /* 52: */
229 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
230 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
231 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
232 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
233 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
234 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
235 {{{0} } }, /* 59: I2C0 */
236 {{{0} } }, /* 60: I2C1 */
237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
238 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
239 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
240};
241
242/*
243 * top 12 bits of crb internal address (hub, agent)
244 */
245static unsigned crb_hub_agt[64] =
246{
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
249 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
250 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
251 0,
252 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
253 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
254 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
260 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
261 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
281 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
282 0,
283 0,
284 0,
285 0,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
288 0,
289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
290 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
296 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
297 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
298 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
299 0,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
303 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
308 0,
309 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
310 0,
311};
312
313/* PCI Windowing for DDR regions. */
314
315#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
316
317#define NETXEN_PCIE_SEM_TIMEOUT 10000
318
319int
320netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
321{
322 int done = 0, timeout = 0;
323
324 while (!done) {
325 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
326 if (done == 1)
327 break;
328 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
329 return -1;
330 msleep(1);
331 }
332
333 if (id_reg)
334 NXWR32(adapter, id_reg, adapter->portnum);
335
336 return 0;
337}
338
339void
340netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
341{
342 int val;
343 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
344}
345
346int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
347{
348 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
349 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
350 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
351 }
352
353 return 0;
354}
355
356/* Disable an XG interface */
357int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
358{
359 __u32 mac_cfg;
360 u32 port = adapter->physical_port;
361
362 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
363 return 0;
364
365 if (port > NETXEN_NIU_MAX_XG_PORTS)
366 return -EINVAL;
367
368 mac_cfg = 0;
369 if (NXWR32(adapter,
370 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
371 return -EIO;
372 return 0;
373}
374
375#define NETXEN_UNICAST_ADDR(port, index) \
376 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
377#define NETXEN_MCAST_ADDR(port, index) \
378 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
379#define MAC_HI(addr) \
380 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
381#define MAC_LO(addr) \
382 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
383
384int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
385{
386 u32 mac_cfg;
387 u32 cnt = 0;
388 __u32 reg = 0x0200;
389 u32 port = adapter->physical_port;
390 u16 board_type = adapter->ahw.board_type;
391
392 if (port > NETXEN_NIU_MAX_XG_PORTS)
393 return -EINVAL;
394
395 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
396 mac_cfg &= ~0x4;
397 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
398
399 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
400 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
401 reg = (0x20 << port);
402
403 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
404
405 mdelay(10);
406
407 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
408 mdelay(10);
409
410 if (cnt < 20) {
411
412 reg = NXRD32(adapter,
413 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
414
415 if (mode == NETXEN_NIU_PROMISC_MODE)
416 reg = (reg | 0x2000UL);
417 else
418 reg = (reg & ~0x2000UL);
419
420 if (mode == NETXEN_NIU_ALLMULTI_MODE)
421 reg = (reg | 0x1000UL);
422 else
423 reg = (reg & ~0x1000UL);
424
425 NXWR32(adapter,
426 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
427 }
428
429 mac_cfg |= 0x4;
430 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
431
432 return 0;
433}
434
435int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
436{
437 u32 mac_hi, mac_lo;
438 u32 reg_hi, reg_lo;
439
440 u8 phy = adapter->physical_port;
441
442 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
443 return -EINVAL;
444
445 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
446 mac_hi = addr[2] | ((u32)addr[3] << 8) |
447 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
448
449 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
450 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
451
452 /* write twice to flush */
453 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
454 return -EIO;
455 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
456 return -EIO;
457
458 return 0;
459}
460
461static int
462netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
463{
464 u32 val = 0;
465 u16 port = adapter->physical_port;
466 u8 *addr = adapter->mac_addr;
467
468 if (adapter->mc_enabled)
469 return 0;
470
471 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
472 val |= (1UL << (28+port));
473 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
474
475 /* add broadcast addr to filter */
476 val = 0xffffff;
477 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
478 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
479
480 /* add station addr to filter */
481 val = MAC_HI(addr);
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
483 val = MAC_LO(addr);
484 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
485
486 adapter->mc_enabled = 1;
487 return 0;
488}
489
490static int
491netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
492{
493 u32 val = 0;
494 u16 port = adapter->physical_port;
495 u8 *addr = adapter->mac_addr;
496
497 if (!adapter->mc_enabled)
498 return 0;
499
500 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
501 val &= ~(1UL << (28+port));
502 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
503
504 val = MAC_HI(addr);
505 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
506 val = MAC_LO(addr);
507 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
508
509 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
511
512 adapter->mc_enabled = 0;
513 return 0;
514}
515
516static int
517netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
518 int index, u8 *addr)
519{
520 u32 hi = 0, lo = 0;
521 u16 port = adapter->physical_port;
522
523 lo = MAC_LO(addr);
524 hi = MAC_HI(addr);
525
526 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
527 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
528
529 return 0;
530}
531
532void netxen_p2_nic_set_multi(struct net_device *netdev)
533{
534 struct netxen_adapter *adapter = netdev_priv(netdev);
535 struct dev_mc_list *mc_ptr;
536 u8 null_addr[6];
537 int index = 0;
538
539 memset(null_addr, 0, 6);
540
541 if (netdev->flags & IFF_PROMISC) {
542
543 adapter->set_promisc(adapter,
544 NETXEN_NIU_PROMISC_MODE);
545
546 /* Full promiscuous mode */
547 netxen_nic_disable_mcast_filter(adapter);
548
549 return;
550 }
551
552 if (netdev->mc_count == 0) {
553 adapter->set_promisc(adapter,
554 NETXEN_NIU_NON_PROMISC_MODE);
555 netxen_nic_disable_mcast_filter(adapter);
556 return;
557 }
558
559 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
560 if (netdev->flags & IFF_ALLMULTI ||
561 netdev->mc_count > adapter->max_mc_count) {
562 netxen_nic_disable_mcast_filter(adapter);
563 return;
564 }
565
566 netxen_nic_enable_mcast_filter(adapter);
567
568 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
569 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
570
571 if (index != netdev->mc_count)
572 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
573 netxen_nic_driver_name, netdev->name);
574
575 /* Clear out remaining addresses */
576 for (; index < adapter->max_mc_count; index++)
577 netxen_nic_set_mcast_addr(adapter, index, null_addr);
578}
579
580static int
581netxen_send_cmd_descs(struct netxen_adapter *adapter,
582 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
583{
584 u32 i, producer, consumer;
585 struct netxen_cmd_buffer *pbuf;
586 struct cmd_desc_type0 *cmd_desc;
587 struct nx_host_tx_ring *tx_ring;
588
589 i = 0;
590
591 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
592 return -EIO;
593
594 tx_ring = adapter->tx_ring;
595 __netif_tx_lock_bh(tx_ring->txq);
596
597 producer = tx_ring->producer;
598 consumer = tx_ring->sw_consumer;
599
600 if (nr_desc >= netxen_tx_avail(tx_ring)) {
601 netif_tx_stop_queue(tx_ring->txq);
602 __netif_tx_unlock_bh(tx_ring->txq);
603 return -EBUSY;
604 }
605
606 do {
607 cmd_desc = &cmd_desc_arr[i];
608
609 pbuf = &tx_ring->cmd_buf_arr[producer];
610 pbuf->skb = NULL;
611 pbuf->frag_count = 0;
612
613 memcpy(&tx_ring->desc_head[producer],
614 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
615
616 producer = get_next_index(producer, tx_ring->num_desc);
617 i++;
618
619 } while (i != nr_desc);
620
621 tx_ring->producer = producer;
622
623 netxen_nic_update_cmd_producer(adapter, tx_ring);
624
625 __netif_tx_unlock_bh(tx_ring->txq);
626
627 return 0;
628}
629
630static int
631nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
632{
633 nx_nic_req_t req;
634 nx_mac_req_t *mac_req;
635 u64 word;
636
637 memset(&req, 0, sizeof(nx_nic_req_t));
638 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
639
640 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
641 req.req_hdr = cpu_to_le64(word);
642
643 mac_req = (nx_mac_req_t *)&req.words[0];
644 mac_req->op = op;
645 memcpy(mac_req->mac_addr, addr, 6);
646
647 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
648}
649
650static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
651 u8 *addr, struct list_head *del_list)
652{
653 struct list_head *head;
654 nx_mac_list_t *cur;
655
656 /* look up if already exists */
657 list_for_each(head, del_list) {
658 cur = list_entry(head, nx_mac_list_t, list);
659
660 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
661 list_move_tail(head, &adapter->mac_list);
662 return 0;
663 }
664 }
665
666 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
667 if (cur == NULL) {
668 printk(KERN_ERR "%s: failed to add mac address filter\n",
669 adapter->netdev->name);
670 return -ENOMEM;
671 }
672 memcpy(cur->mac_addr, addr, ETH_ALEN);
673 list_add_tail(&cur->list, &adapter->mac_list);
674 return nx_p3_sre_macaddr_change(adapter,
675 cur->mac_addr, NETXEN_MAC_ADD);
676}
677
678void netxen_p3_nic_set_multi(struct net_device *netdev)
679{
680 struct netxen_adapter *adapter = netdev_priv(netdev);
681 struct dev_mc_list *mc_ptr;
682 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
683 u32 mode = VPORT_MISS_MODE_DROP;
684 LIST_HEAD(del_list);
685 struct list_head *head;
686 nx_mac_list_t *cur;
687
688 list_splice_tail_init(&adapter->mac_list, &del_list);
689
690 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
691 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
692
693 if (netdev->flags & IFF_PROMISC) {
694 mode = VPORT_MISS_MODE_ACCEPT_ALL;
695 goto send_fw_cmd;
696 }
697
698 if ((netdev->flags & IFF_ALLMULTI) ||
699 (netdev->mc_count > adapter->max_mc_count)) {
700 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
701 goto send_fw_cmd;
702 }
703
704 if (netdev->mc_count > 0) {
705 for (mc_ptr = netdev->mc_list; mc_ptr;
706 mc_ptr = mc_ptr->next) {
707 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
708 }
709 }
710
711send_fw_cmd:
712 adapter->set_promisc(adapter, mode);
713 head = &del_list;
714 while (!list_empty(head)) {
715 cur = list_entry(head->next, nx_mac_list_t, list);
716
717 nx_p3_sre_macaddr_change(adapter,
718 cur->mac_addr, NETXEN_MAC_DEL);
719 list_del(&cur->list);
720 kfree(cur);
721 }
722}
723
724int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
725{
726 nx_nic_req_t req;
727 u64 word;
728
729 memset(&req, 0, sizeof(nx_nic_req_t));
730
731 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
732
733 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
734 ((u64)adapter->portnum << 16);
735 req.req_hdr = cpu_to_le64(word);
736
737 req.words[0] = cpu_to_le64(mode);
738
739 return netxen_send_cmd_descs(adapter,
740 (struct cmd_desc_type0 *)&req, 1);
741}
742
743void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
744{
745 nx_mac_list_t *cur;
746 struct list_head *head = &adapter->mac_list;
747
748 while (!list_empty(head)) {
749 cur = list_entry(head->next, nx_mac_list_t, list);
750 nx_p3_sre_macaddr_change(adapter,
751 cur->mac_addr, NETXEN_MAC_DEL);
752 list_del(&cur->list);
753 kfree(cur);
754 }
755}
756
757int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
758{
759 /* assuming caller has already copied new addr to netdev */
760 netxen_p3_nic_set_multi(adapter->netdev);
761 return 0;
762}
763
764#define NETXEN_CONFIG_INTR_COALESCE 3
765
766/*
767 * Send the interrupt coalescing parameter set by ethtool to the card.
768 */
769int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
770{
771 nx_nic_req_t req;
772 u64 word;
773 int rv;
774
775 memset(&req, 0, sizeof(nx_nic_req_t));
776
777 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
778
779 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
780 req.req_hdr = cpu_to_le64(word);
781
782 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
783
784 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
785 if (rv != 0) {
786 printk(KERN_ERR "ERROR. Could not send "
787 "interrupt coalescing parameters\n");
788 }
789
790 return rv;
791}
792
793int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
794{
795 nx_nic_req_t req;
796 u64 word;
797 int rv = 0;
798
799 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
800 return 0;
801
802 memset(&req, 0, sizeof(nx_nic_req_t));
803
804 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
805
806 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
807 req.req_hdr = cpu_to_le64(word);
808
809 req.words[0] = cpu_to_le64(enable);
810
811 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
812 if (rv != 0) {
813 printk(KERN_ERR "ERROR. Could not send "
814 "configure hw lro request\n");
815 }
816
817 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
818
819 return rv;
820}
821
822int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
823{
824 nx_nic_req_t req;
825 u64 word;
826 int rv = 0;
827
828 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
829 return rv;
830
831 memset(&req, 0, sizeof(nx_nic_req_t));
832
833 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
834
835 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
836 ((u64)adapter->portnum << 16);
837 req.req_hdr = cpu_to_le64(word);
838
839 req.words[0] = cpu_to_le64(enable);
840
841 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
842 if (rv != 0) {
843 printk(KERN_ERR "ERROR. Could not send "
844 "configure bridge mode request\n");
845 }
846
847 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
848
849 return rv;
850}
851
852
853#define RSS_HASHTYPE_IP_TCP 0x3
854
855int netxen_config_rss(struct netxen_adapter *adapter, int enable)
856{
857 nx_nic_req_t req;
858 u64 word;
859 int i, rv;
860
861 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
862 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
863 0x255b0ec26d5a56daULL };
864
865
866 memset(&req, 0, sizeof(nx_nic_req_t));
867 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
868
869 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
870 req.req_hdr = cpu_to_le64(word);
871
872 /*
873 * RSS request:
874 * bits 3-0: hash_method
875 * 5-4: hash_type_ipv4
876 * 7-6: hash_type_ipv6
877 * 8: enable
878 * 9: use indirection table
879 * 47-10: reserved
880 * 63-48: indirection table mask
881 */
882 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
883 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
884 ((u64)(enable & 0x1) << 8) |
885 ((0x7ULL) << 48);
886 req.words[0] = cpu_to_le64(word);
887 for (i = 0; i < 5; i++)
888 req.words[i+1] = cpu_to_le64(key[i]);
889
890
891 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
892 if (rv != 0) {
893 printk(KERN_ERR "%s: could not configure RSS\n",
894 adapter->netdev->name);
895 }
896
897 return rv;
898}
899
900int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
901{
902 nx_nic_req_t req;
903 u64 word;
904 int rv;
905
906 memset(&req, 0, sizeof(nx_nic_req_t));
907 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
908
909 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
910 req.req_hdr = cpu_to_le64(word);
911
912 req.words[0] = cpu_to_le64(cmd);
913 req.words[1] = cpu_to_le64(ip);
914
915 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
916 if (rv != 0) {
917 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
918 adapter->netdev->name,
919 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
920 }
921 return rv;
922}
923
924int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
925{
926 nx_nic_req_t req;
927 u64 word;
928 int rv;
929
930 memset(&req, 0, sizeof(nx_nic_req_t));
931 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
932
933 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
934 req.req_hdr = cpu_to_le64(word);
935 req.words[0] = cpu_to_le64(enable | (enable << 8));
936
937 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
938 if (rv != 0) {
939 printk(KERN_ERR "%s: could not configure link notification\n",
940 adapter->netdev->name);
941 }
942
943 return rv;
944}
945
946int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
947{
948 nx_nic_req_t req;
949 u64 word;
950 int rv;
951
952 memset(&req, 0, sizeof(nx_nic_req_t));
953 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
954
955 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
956 ((u64)adapter->portnum << 16) |
957 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
958
959 req.req_hdr = cpu_to_le64(word);
960
961 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
962 if (rv != 0) {
963 printk(KERN_ERR "%s: could not cleanup lro flows\n",
964 adapter->netdev->name);
965 }
966 return rv;
967}
968
969/*
970 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
971 * @returns 0 on success, negative on failure
972 */
973
974#define MTU_FUDGE_FACTOR 100
975
976int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
977{
978 struct netxen_adapter *adapter = netdev_priv(netdev);
979 int max_mtu;
980 int rc = 0;
981
982 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
983 max_mtu = P3_MAX_MTU;
984 else
985 max_mtu = P2_MAX_MTU;
986
987 if (mtu > max_mtu) {
988 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
989 netdev->name, max_mtu);
990 return -EINVAL;
991 }
992
993 if (adapter->set_mtu)
994 rc = adapter->set_mtu(adapter, mtu);
995
996 if (!rc)
997 netdev->mtu = mtu;
998
999 return rc;
1000}
1001
1002static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1003 int size, __le32 * buf)
1004{
1005 int i, v, addr;
1006 __le32 *ptr32;
1007
1008 addr = base;
1009 ptr32 = buf;
1010 for (i = 0; i < size / sizeof(u32); i++) {
1011 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1012 return -1;
1013 *ptr32 = cpu_to_le32(v);
1014 ptr32++;
1015 addr += sizeof(u32);
1016 }
1017 if ((char *)buf + size > (char *)ptr32) {
1018 __le32 local;
1019 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1020 return -1;
1021 local = cpu_to_le32(v);
1022 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1023 }
1024
1025 return 0;
1026}
1027
1028int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1029{
1030 __le32 *pmac = (__le32 *) mac;
1031 u32 offset;
1032
1033 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1034
1035 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1036 return -1;
1037
1038 if (*mac == cpu_to_le64(~0ULL)) {
1039
1040 offset = NX_OLD_MAC_ADDR_OFFSET +
1041 (adapter->portnum * sizeof(u64));
1042
1043 if (netxen_get_flash_block(adapter,
1044 offset, sizeof(u64), pmac) == -1)
1045 return -1;
1046
1047 if (*mac == cpu_to_le64(~0ULL))
1048 return -1;
1049 }
1050 return 0;
1051}
1052
1053int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1054{
1055 uint32_t crbaddr, mac_hi, mac_lo;
1056 int pci_func = adapter->ahw.pci_func;
1057
1058 crbaddr = CRB_MAC_BLOCK_START +
1059 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1060
1061 mac_lo = NXRD32(adapter, crbaddr);
1062 mac_hi = NXRD32(adapter, crbaddr+4);
1063
1064 if (pci_func & 1)
1065 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1066 else
1067 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1068
1069 return 0;
1070}
1071
1072/*
1073 * Changes the CRB window to the specified window.
1074 */
1075static void
1076netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
1077{
1078 void __iomem *offset;
1079 u32 tmp;
1080 int count = 0;
1081 uint8_t func = adapter->ahw.pci_func;
1082
1083 if (adapter->curr_window == wndw)
1084 return;
1085 /*
1086 * Move the CRB window.
1087 * We need to write to the "direct access" region of PCI
1088 * to avoid a race condition where the window register has
1089 * not been successfully written across CRB before the target
1090 * register address is received by PCI. The direct region bypasses
1091 * the CRB bus.
1092 */
1093 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1094 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1095
1096 if (wndw & 0x1)
1097 wndw = NETXEN_WINDOW_ONE;
1098
1099 writel(wndw, offset);
1100
1101 /* MUST make sure window is set before we forge on... */
1102 while ((tmp = readl(offset)) != wndw) {
1103 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1104 "registered properly: 0x%08x.\n",
1105 netxen_nic_driver_name, __func__, tmp);
1106 mdelay(1);
1107 if (count >= 10)
1108 break;
1109 count++;
1110 }
1111
1112 if (wndw == NETXEN_WINDOW_ONE)
1113 adapter->curr_window = 1;
1114 else
1115 adapter->curr_window = 0;
1116}
1117
1118/*
1119 * Return -1 if off is not valid,
1120 * 1 if window access is needed. 'off' is set to offset from
1121 * CRB space in 128M pci map
1122 * 0 if no window access is needed. 'off' is set to 2M addr
1123 * In: 'off' is offset from base in 128M pci map
1124 */
1125static int
1126netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1127{
1128 crb_128M_2M_sub_block_map_t *m;
1129
1130
1131 if (*off >= NETXEN_CRB_MAX)
1132 return -1;
1133
1134 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1135 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1136 (ulong)adapter->ahw.pci_base0;
1137 return 0;
1138 }
1139
1140 if (*off < NETXEN_PCI_CRBSPACE)
1141 return -1;
1142
1143 *off -= NETXEN_PCI_CRBSPACE;
1144
1145 /*
1146 * Try direct map
1147 */
1148 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1149
1150 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1151 *off = *off + m->start_2M - m->start_128M +
1152 (ulong)adapter->ahw.pci_base0;
1153 return 0;
1154 }
1155
1156 /*
1157 * Not in direct map, use crb window
1158 */
1159 return 1;
1160}
1161
1162/*
1163 * In: 'off' is offset from CRB space in 128M pci map
1164 * Out: 'off' is 2M pci map addr
1165 * side effect: lock crb window
1166 */
1167static void
1168netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1169{
1170 u32 win_read;
1171
1172 adapter->crb_win = CRB_HI(*off);
1173 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1174 /*
1175 * Read back value to make sure write has gone through before trying
1176 * to use it.
1177 */
1178 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1179 if (win_read != adapter->crb_win) {
1180 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1181 "Read crbwin (0x%x), off=0x%lx\n",
1182 __func__, adapter->crb_win, win_read, *off);
1183 }
1184 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1185 (ulong)adapter->ahw.pci_base0;
1186}
1187
1188static int
1189netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1190{
1191 unsigned long flags;
1192 void __iomem *addr;
1193
1194 if (ADDR_IN_WINDOW1(off))
1195 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1196 else
1197 addr = pci_base_offset(adapter, off);
1198
1199 BUG_ON(!addr);
1200
1201 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1202 read_lock(&adapter->adapter_lock);
1203 writel(data, addr);
1204 read_unlock(&adapter->adapter_lock);
1205 } else { /* Window 0 */
1206 write_lock_irqsave(&adapter->adapter_lock, flags);
1207 addr = pci_base_offset(adapter, off);
1208 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1209 writel(data, addr);
1210 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1211 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1212 }
1213
1214 return 0;
1215}
1216
1217static u32
1218netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1219{
1220 unsigned long flags;
1221 void __iomem *addr;
1222 u32 data;
1223
1224 if (ADDR_IN_WINDOW1(off))
1225 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1226 else
1227 addr = pci_base_offset(adapter, off);
1228
1229 BUG_ON(!addr);
1230
1231 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1232 read_lock(&adapter->adapter_lock);
1233 data = readl(addr);
1234 read_unlock(&adapter->adapter_lock);
1235 } else { /* Window 0 */
1236 write_lock_irqsave(&adapter->adapter_lock, flags);
1237 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1238 data = readl(addr);
1239 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1240 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1241 }
1242
1243 return data;
1244}
1245
1246static int
1247netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1248{
1249 unsigned long flags;
1250 int rv;
1251
1252 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1253
1254 if (rv == -1) {
1255 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1256 __func__, off);
1257 dump_stack();
1258 return -1;
1259 }
1260
1261 if (rv == 1) {
1262 write_lock_irqsave(&adapter->adapter_lock, flags);
1263 crb_win_lock(adapter);
1264 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1265 writel(data, (void __iomem *)off);
1266 crb_win_unlock(adapter);
1267 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1268 } else
1269 writel(data, (void __iomem *)off);
1270
1271
1272 return 0;
1273}
1274
1275static u32
1276netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1277{
1278 unsigned long flags;
1279 int rv;
1280 u32 data;
1281
1282 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1283
1284 if (rv == -1) {
1285 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1286 __func__, off);
1287 dump_stack();
1288 return -1;
1289 }
1290
1291 if (rv == 1) {
1292 write_lock_irqsave(&adapter->adapter_lock, flags);
1293 crb_win_lock(adapter);
1294 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1295 data = readl((void __iomem *)off);
1296 crb_win_unlock(adapter);
1297 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1298 } else
1299 data = readl((void __iomem *)off);
1300
1301 return data;
1302}
1303
1304static int netxen_pci_set_window_warning_count;
1305
1306static unsigned long
1307netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1308 unsigned long long addr)
1309{
1310 void __iomem *offset;
1311 int window;
1312 unsigned long long qdr_max;
1313 uint8_t func = adapter->ahw.pci_func;
1314
1315 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1316 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1317 } else {
1318 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1319 }
1320
1321 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1322 /* DDR network side */
1323 addr -= NETXEN_ADDR_DDR_NET;
1324 window = (addr >> 25) & 0x3ff;
1325 if (adapter->ahw.ddr_mn_window != window) {
1326 adapter->ahw.ddr_mn_window = window;
1327 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1328 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1329 writel(window, offset);
1330 /* MUST make sure window is set before we forge on... */
1331 readl(offset);
1332 }
1333 addr -= (window * NETXEN_WINDOW_ONE);
1334 addr += NETXEN_PCI_DDR_NET;
1335 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1336 addr -= NETXEN_ADDR_OCM0;
1337 addr += NETXEN_PCI_OCM0;
1338 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1339 addr -= NETXEN_ADDR_OCM1;
1340 addr += NETXEN_PCI_OCM1;
1341 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1342 /* QDR network side */
1343 addr -= NETXEN_ADDR_QDR_NET;
1344 window = (addr >> 22) & 0x3f;
1345 if (adapter->ahw.qdr_sn_window != window) {
1346 adapter->ahw.qdr_sn_window = window;
1347 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1348 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1349 writel((window << 22), offset);
1350 /* MUST make sure window is set before we forge on... */
1351 readl(offset);
1352 }
1353 addr -= (window * 0x400000);
1354 addr += NETXEN_PCI_QDR_NET;
1355 } else {
1356 /*
1357 * peg gdb frequently accesses memory that doesn't exist,
1358 * this limits the chit chat so debugging isn't slowed down.
1359 */
1360 if ((netxen_pci_set_window_warning_count++ < 8)
1361 || (netxen_pci_set_window_warning_count % 64 == 0))
1362 printk("%s: Warning:netxen_nic_pci_set_window()"
1363 " Unknown address range!\n",
1364 netxen_nic_driver_name);
1365 addr = -1UL;
1366 }
1367 return addr;
1368}
1369
1370/* window 1 registers only */
1371static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1372 void __iomem *addr, u32 data)
1373{
1374 read_lock(&adapter->adapter_lock);
1375 writel(data, addr);
1376 read_unlock(&adapter->adapter_lock);
1377}
1378
1379static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1380 void __iomem *addr)
1381{
1382 u32 val;
1383
1384 read_lock(&adapter->adapter_lock);
1385 val = readl(addr);
1386 read_unlock(&adapter->adapter_lock);
1387
1388 return val;
1389}
1390
1391static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1392 void __iomem *addr, u32 data)
1393{
1394 writel(data, addr);
1395}
1396
1397static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1398 void __iomem *addr)
1399{
1400 return readl(addr);
1401}
1402
1403void __iomem *
1404netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1405{
1406 ulong off = offset;
1407
1408 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1409 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1410 offset > NETXEN_CRB_PCIX_HOST)
1411 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1412 return NETXEN_CRB_NORMALIZE(adapter, offset);
1413 }
1414
1415 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1416 return (void __iomem *)off;
1417}
1418
1419static unsigned long
1420netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1421 unsigned long long addr)
1422{
1423 int window;
1424 u32 win_read;
1425
1426 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1427 /* DDR network side */
1428 window = MN_WIN(addr);
1429 adapter->ahw.ddr_mn_window = window;
1430 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1431 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
1432 if ((win_read << 17) != window) {
1433 printk(KERN_INFO "Written MNwin (0x%x) != "
1434 "Read MNwin (0x%x)\n", window, win_read);
1435 }
1436 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1437 } else if (ADDR_IN_RANGE(addr,
1438 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1439 if ((addr & 0x00ff800) == 0xff800) {
1440 printk("%s: QM access not handled.\n", __func__);
1441 addr = -1UL;
1442 }
1443
1444 window = OCM_WIN(addr);
1445 adapter->ahw.ddr_mn_window = window;
1446 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1447 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
1448 if ((win_read >> 7) != window) {
1449 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1450 "Read OCMwin (0x%x)\n",
1451 __func__, window, win_read);
1452 }
1453 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1454
1455 } else if (ADDR_IN_RANGE(addr,
1456 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1457 /* QDR network side */
1458 window = MS_WIN(addr);
1459 adapter->ahw.qdr_sn_window = window;
1460 NXWR32(adapter, adapter->ahw.ms_win_crb, window);
1461 win_read = NXRD32(adapter, adapter->ahw.ms_win_crb);
1462 if (win_read != window) {
1463 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1464 "Read MSwin (0x%x)\n",
1465 __func__, window, win_read);
1466 }
1467 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1468
1469 } else {
1470 /*
1471 * peg gdb frequently accesses memory that doesn't exist,
1472 * this limits the chit chat so debugging isn't slowed down.
1473 */
1474 if ((netxen_pci_set_window_warning_count++ < 8)
1475 || (netxen_pci_set_window_warning_count%64 == 0)) {
1476 printk("%s: Warning:%s Unknown address range!\n",
1477 __func__, netxen_nic_driver_name);
1478}
1479 addr = -1UL;
1480 }
1481 return addr;
1482}
1483
1484#define MAX_CTL_CHECK 1000
1485
1486static int
1487netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1488 u64 off, void *data, int size)
1489{
1490 unsigned long flags;
1491 int i, j, ret = 0, loop, sz[2], off0;
1492 uint32_t temp;
1493 uint64_t off8, tmpw, word[2] = {0, 0};
1494 void __iomem *mem_crb;
1495
1496 if (size != 8)
1497 return -EIO;
1498
1499 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1500 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1501 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1502 goto correct;
1503 }
1504
1505 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1506 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1507 goto correct;
1508 }
1509
1510 return -EIO;
1511
1512correct:
1513 off8 = off & 0xfffffff8;
1514 off0 = off & 0x7;
1515 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1516 sz[1] = size - sz[0];
1517 loop = ((off0 + size - 1) >> 3) + 1;
1518
1519 if ((size != 8) || (off0 != 0)) {
1520 for (i = 0; i < loop; i++) {
1521 if (adapter->pci_mem_read(adapter,
1522 off8 + (i << 3), &word[i], 8))
1523 return -1;
1524 }
1525 }
1526
1527 switch (size) {
1528 case 1:
1529 tmpw = *((uint8_t *)data);
1530 break;
1531 case 2:
1532 tmpw = *((uint16_t *)data);
1533 break;
1534 case 4:
1535 tmpw = *((uint32_t *)data);
1536 break;
1537 case 8:
1538 default:
1539 tmpw = *((uint64_t *)data);
1540 break;
1541 }
1542 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1543 word[0] |= tmpw << (off0 * 8);
1544
1545 if (loop == 2) {
1546 word[1] &= ~(~0ULL << (sz[1] * 8));
1547 word[1] |= tmpw >> (sz[0] * 8);
1548 }
1549
1550 write_lock_irqsave(&adapter->adapter_lock, flags);
1551 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1552
1553 for (i = 0; i < loop; i++) {
1554 writel((uint32_t)(off8 + (i << 3)),
1555 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1556 writel(0,
1557 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1558 writel(word[i] & 0xffffffff,
1559 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1560 writel((word[i] >> 32) & 0xffffffff,
1561 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1562 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1563 (mem_crb+MIU_TEST_AGT_CTRL));
1564 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1565 (mem_crb+MIU_TEST_AGT_CTRL));
1566
1567 for (j = 0; j < MAX_CTL_CHECK; j++) {
1568 temp = readl(
1569 (mem_crb+MIU_TEST_AGT_CTRL));
1570 if ((temp & MIU_TA_CTL_BUSY) == 0)
1571 break;
1572 }
1573
1574 if (j >= MAX_CTL_CHECK) {
1575 if (printk_ratelimit())
1576 dev_err(&adapter->pdev->dev,
1577 "failed to write through agent\n");
1578 ret = -1;
1579 break;
1580 }
1581 }
1582
1583 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1584 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1585 return ret;
1586}
1587
1588static int
1589netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1590 u64 off, void *data, int size)
1591{
1592 unsigned long flags;
1593 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1594 uint32_t temp;
1595 uint64_t off8, val, word[2] = {0, 0};
1596 void __iomem *mem_crb;
1597
1598 if (size != 8)
1599 return -EIO;
1600
1601 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1602 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1603 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1604 goto correct;
1605 }
1606
1607 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1608 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1609 goto correct;
1610 }
1611
1612 return -EIO;
1613
1614correct:
1615 off8 = off & 0xfffffff8;
1616 off0[0] = off & 0x7;
1617 off0[1] = 0;
1618 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1619 sz[1] = size - sz[0];
1620 loop = ((off0[0] + size - 1) >> 3) + 1;
1621
1622 write_lock_irqsave(&adapter->adapter_lock, flags);
1623 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1624
1625 for (i = 0; i < loop; i++) {
1626 writel((uint32_t)(off8 + (i << 3)),
1627 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1628 writel(0,
1629 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1630 writel(MIU_TA_CTL_ENABLE,
1631 (mem_crb+MIU_TEST_AGT_CTRL));
1632 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1633 (mem_crb+MIU_TEST_AGT_CTRL));
1634
1635 for (j = 0; j < MAX_CTL_CHECK; j++) {
1636 temp = readl(
1637 (mem_crb+MIU_TEST_AGT_CTRL));
1638 if ((temp & MIU_TA_CTL_BUSY) == 0)
1639 break;
1640 }
1641
1642 if (j >= MAX_CTL_CHECK) {
1643 if (printk_ratelimit())
1644 dev_err(&adapter->pdev->dev,
1645 "failed to read through agent\n");
1646 break;
1647 }
1648
1649 start = off0[i] >> 2;
1650 end = (off0[i] + sz[i] - 1) >> 2;
1651 for (k = start; k <= end; k++) {
1652 word[i] |= ((uint64_t) readl(
1653 (mem_crb +
1654 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1655 }
1656 }
1657
1658 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1659 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1660
1661 if (j >= MAX_CTL_CHECK)
1662 return -1;
1663
1664 if (sz[0] == 8) {
1665 val = word[0];
1666 } else {
1667 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1668 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1669 }
1670
1671 switch (size) {
1672 case 1:
1673 *(uint8_t *)data = val;
1674 break;
1675 case 2:
1676 *(uint16_t *)data = val;
1677 break;
1678 case 4:
1679 *(uint32_t *)data = val;
1680 break;
1681 case 8:
1682 *(uint64_t *)data = val;
1683 break;
1684 }
1685 return 0;
1686}
1687
1688static int
1689netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1690 u64 off, void *data, int size)
1691{
1692 int i, j, ret = 0, loop, sz[2], off0;
1693 uint32_t temp;
1694 uint64_t off8, tmpw, word[2] = {0, 0};
1695 void __iomem *mem_crb;
1696
1697 if (size != 8)
1698 return -EIO;
1699
1700 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1701 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1702 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1703 goto correct;
1704 }
1705
1706 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1707 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1708 goto correct;
1709 }
1710
1711 return -EIO;
1712
1713correct:
1714 off8 = off & 0xfffffff8;
1715 off0 = off & 0x7;
1716 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1717 sz[1] = size - sz[0];
1718 loop = ((off0 + size - 1) >> 3) + 1;
1719
1720 if ((size != 8) || (off0 != 0)) {
1721 for (i = 0; i < loop; i++) {
1722 if (adapter->pci_mem_read(adapter,
1723 off8 + (i << 3), &word[i], 8))
1724 return -1;
1725 }
1726 }
1727
1728 switch (size) {
1729 case 1:
1730 tmpw = *((uint8_t *)data);
1731 break;
1732 case 2:
1733 tmpw = *((uint16_t *)data);
1734 break;
1735 case 4:
1736 tmpw = *((uint32_t *)data);
1737 break;
1738 case 8:
1739 default:
1740 tmpw = *((uint64_t *)data);
1741 break;
1742 }
1743
1744 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1745 word[0] |= tmpw << (off0 * 8);
1746
1747 if (loop == 2) {
1748 word[1] &= ~(~0ULL << (sz[1] * 8));
1749 word[1] |= tmpw >> (sz[0] * 8);
1750 }
1751
1752 /*
1753 * don't lock here - write_wx gets the lock if each time
1754 * write_lock_irqsave(&adapter->adapter_lock, flags);
1755 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1756 */
1757
1758 for (i = 0; i < loop; i++) {
1759 writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO);
1760 writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI);
1761 writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO);
1762 writel((word[i] >> 32) & 0xffffffff,
1763 mem_crb+MIU_TEST_AGT_WRDATA_HI);
1764 writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE),
1765 mem_crb+MIU_TEST_AGT_CTRL);
1766 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE,
1767 mem_crb+MIU_TEST_AGT_CTRL);
1768
1769 for (j = 0; j < MAX_CTL_CHECK; j++) {
1770 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
1771 if ((temp & MIU_TA_CTL_BUSY) == 0)
1772 break;
1773 }
1774
1775 if (j >= MAX_CTL_CHECK) {
1776 if (printk_ratelimit())
1777 dev_err(&adapter->pdev->dev,
1778 "failed to write through agent\n");
1779 ret = -1;
1780 break;
1781 }
1782 }
1783
1784 /*
1785 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1786 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1787 */
1788 return ret;
1789}
1790
1791static int
1792netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1793 u64 off, void *data, int size)
1794{
1795 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1796 uint32_t temp;
1797 uint64_t off8, val, word[2] = {0, 0};
1798 void __iomem *mem_crb;
1799
1800 if (size != 8)
1801 return -EIO;
1802
1803 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1804 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1805 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1806 goto correct;
1807 }
1808
1809 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1810 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1811 goto correct;
1812 }
1813
1814 return -EIO;
1815
1816correct:
1817 off8 = off & 0xfffffff8;
1818 off0[0] = off & 0x7;
1819 off0[1] = 0;
1820 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1821 sz[1] = size - sz[0];
1822 loop = ((off0[0] + size - 1) >> 3) + 1;
1823
1824 /*
1825 * don't lock here - write_wx gets the lock if each time
1826 * write_lock_irqsave(&adapter->adapter_lock, flags);
1827 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1828 */
1829
1830 for (i = 0; i < loop; i++) {
1831 writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO);
1832 writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI);
1833 writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL);
1834 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE,
1835 mem_crb + MIU_TEST_AGT_CTRL);
1836
1837 for (j = 0; j < MAX_CTL_CHECK; j++) {
1838 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
1839 if ((temp & MIU_TA_CTL_BUSY) == 0)
1840 break;
1841 }
1842
1843 if (j >= MAX_CTL_CHECK) {
1844 if (printk_ratelimit())
1845 dev_err(&adapter->pdev->dev,
1846 "failed to read through agent\n");
1847 break;
1848 }
1849
1850 start = off0[i] >> 2;
1851 end = (off0[i] + sz[i] - 1) >> 2;
1852 for (k = start; k <= end; k++) {
1853 temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k));
1854 word[i] |= ((uint64_t)temp << (32 * k));
1855 }
1856 }
1857
1858 /*
1859 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1860 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1861 */
1862
1863 if (j >= MAX_CTL_CHECK)
1864 return -1;
1865
1866 if (sz[0] == 8) {
1867 val = word[0];
1868 } else {
1869 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1870 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1871 }
1872
1873 switch (size) {
1874 case 1:
1875 *(uint8_t *)data = val;
1876 break;
1877 case 2:
1878 *(uint16_t *)data = val;
1879 break;
1880 case 4:
1881 *(uint32_t *)data = val;
1882 break;
1883 case 8:
1884 *(uint64_t *)data = val;
1885 break;
1886 }
1887 return 0;
1888}
1889
1890void
1891netxen_setup_hwops(struct netxen_adapter *adapter)
1892{
1893 adapter->init_port = netxen_niu_xg_init_port;
1894 adapter->stop_port = netxen_niu_disable_xg_port;
1895
1896 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1897 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1898 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1899 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1900 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1901 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1902 adapter->io_read = netxen_nic_io_read_128M,
1903 adapter->io_write = netxen_nic_io_write_128M,
1904
1905 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1906 adapter->set_multi = netxen_p2_nic_set_multi;
1907 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1908 adapter->set_promisc = netxen_p2_nic_set_promisc;
1909
1910 } else {
1911 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1912 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1913 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1914 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1915 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1916 adapter->io_read = netxen_nic_io_read_2M,
1917 adapter->io_write = netxen_nic_io_write_2M,
1918
1919 adapter->set_mtu = nx_fw_cmd_set_mtu;
1920 adapter->set_promisc = netxen_p3_nic_set_promisc;
1921 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1922 adapter->set_multi = netxen_p3_nic_set_multi;
1923
1924 adapter->phy_read = nx_fw_cmd_query_phy;
1925 adapter->phy_write = nx_fw_cmd_set_phy;
1926 }
1927}
1928
1929int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1930{
1931 int offset, board_type, magic;
1932 struct pci_dev *pdev = adapter->pdev;
1933
1934 offset = NX_FW_MAGIC_OFFSET;
1935 if (netxen_rom_fast_read(adapter, offset, &magic))
1936 return -EIO;
1937
1938 if (magic != NETXEN_BDINFO_MAGIC) {
1939 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1940 magic);
1941 return -EIO;
1942 }
1943
1944 offset = NX_BRDTYPE_OFFSET;
1945 if (netxen_rom_fast_read(adapter, offset, &board_type))
1946 return -EIO;
1947
1948 adapter->ahw.board_type = board_type;
1949
1950 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1951 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1952 if ((gpio & 0x8000) == 0)
1953 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1954 }
1955
1956 switch (board_type) {
1957 case NETXEN_BRDTYPE_P2_SB35_4G:
1958 adapter->ahw.port_type = NETXEN_NIC_GBE;
1959 break;
1960 case NETXEN_BRDTYPE_P2_SB31_10G:
1961 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1962 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1963 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1964 case NETXEN_BRDTYPE_P3_HMEZ:
1965 case NETXEN_BRDTYPE_P3_XG_LOM:
1966 case NETXEN_BRDTYPE_P3_10G_CX4:
1967 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1968 case NETXEN_BRDTYPE_P3_IMEZ:
1969 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1970 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1971 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1972 case NETXEN_BRDTYPE_P3_10G_XFP:
1973 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1974 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1975 break;
1976 case NETXEN_BRDTYPE_P1_BD:
1977 case NETXEN_BRDTYPE_P1_SB:
1978 case NETXEN_BRDTYPE_P1_SMAX:
1979 case NETXEN_BRDTYPE_P1_SOCK:
1980 case NETXEN_BRDTYPE_P3_REF_QG:
1981 case NETXEN_BRDTYPE_P3_4_GB:
1982 case NETXEN_BRDTYPE_P3_4_GB_MM:
1983 adapter->ahw.port_type = NETXEN_NIC_GBE;
1984 break;
1985 case NETXEN_BRDTYPE_P3_10G_TP:
1986 adapter->ahw.port_type = (adapter->portnum < 2) ?
1987 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1988 break;
1989 default:
1990 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1991 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1992 break;
1993 }
1994
1995 return 0;
1996}
1997
1998/* NIU access sections */
1999
2000int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2001{
2002 new_mtu += MTU_FUDGE_FACTOR;
2003 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2004 new_mtu);
2005 return 0;
2006}
2007
2008int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2009{
2010 new_mtu += MTU_FUDGE_FACTOR;
2011 if (adapter->physical_port == 0)
2012 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2013 else
2014 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2015 return 0;
2016}
2017
2018void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2019{
2020 __u32 status;
2021 __u32 autoneg;
2022 __u32 port_mode;
2023
2024 if (!netif_carrier_ok(adapter->netdev)) {
2025 adapter->link_speed = 0;
2026 adapter->link_duplex = -1;
2027 adapter->link_autoneg = AUTONEG_ENABLE;
2028 return;
2029 }
2030
2031 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2032 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2033 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2034 adapter->link_speed = SPEED_1000;
2035 adapter->link_duplex = DUPLEX_FULL;
2036 adapter->link_autoneg = AUTONEG_DISABLE;
2037 return;
2038 }
2039
2040 if (adapter->phy_read
2041 && adapter->phy_read(adapter,
2042 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2043 &status) == 0) {
2044 if (netxen_get_phy_link(status)) {
2045 switch (netxen_get_phy_speed(status)) {
2046 case 0:
2047 adapter->link_speed = SPEED_10;
2048 break;
2049 case 1:
2050 adapter->link_speed = SPEED_100;
2051 break;
2052 case 2:
2053 adapter->link_speed = SPEED_1000;
2054 break;
2055 default:
2056 adapter->link_speed = 0;
2057 break;
2058 }
2059 switch (netxen_get_phy_duplex(status)) {
2060 case 0:
2061 adapter->link_duplex = DUPLEX_HALF;
2062 break;
2063 case 1:
2064 adapter->link_duplex = DUPLEX_FULL;
2065 break;
2066 default:
2067 adapter->link_duplex = -1;
2068 break;
2069 }
2070 if (adapter->phy_read
2071 && adapter->phy_read(adapter,
2072 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2073 &autoneg) != 0)
2074 adapter->link_autoneg = autoneg;
2075 } else
2076 goto link_down;
2077 } else {
2078 link_down:
2079 adapter->link_speed = 0;
2080 adapter->link_duplex = -1;
2081 }
2082 }
2083}
2084
2085int
2086netxen_nic_wol_supported(struct netxen_adapter *adapter)
2087{
2088 u32 wol_cfg;
2089
2090 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2091 return 0;
2092
2093 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2094 if (wol_cfg & (1UL << adapter->portnum)) {
2095 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2096 if (wol_cfg & (1 << adapter->portnum))
2097 return 1;
2098 }
2099
2100 return 0;
2101}