tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
14#include <asm/cpm.h>
15#include <sysdev/fsl_soc.h>
16
17/* CPM Command register.
18*/
19#define CPM_CR_RST ((uint)0x80000000)
20#define CPM_CR_PAGE ((uint)0x7c000000)
21#define CPM_CR_SBLOCK ((uint)0x03e00000)
22#define CPM_CR_FLG ((uint)0x00010000)
23#define CPM_CR_MCN ((uint)0x00003fc0)
24#define CPM_CR_OPCODE ((uint)0x0000000f)
25
26/* Device sub-block and page codes.
27*/
28#define CPM_CR_SCC1_SBLOCK (0x04)
29#define CPM_CR_SCC2_SBLOCK (0x05)
30#define CPM_CR_SCC3_SBLOCK (0x06)
31#define CPM_CR_SCC4_SBLOCK (0x07)
32#define CPM_CR_SMC1_SBLOCK (0x08)
33#define CPM_CR_SMC2_SBLOCK (0x09)
34#define CPM_CR_SPI_SBLOCK (0x0a)
35#define CPM_CR_I2C_SBLOCK (0x0b)
36#define CPM_CR_TIMER_SBLOCK (0x0f)
37#define CPM_CR_RAND_SBLOCK (0x0e)
38#define CPM_CR_FCC1_SBLOCK (0x10)
39#define CPM_CR_FCC2_SBLOCK (0x11)
40#define CPM_CR_FCC3_SBLOCK (0x12)
41#define CPM_CR_IDMA1_SBLOCK (0x14)
42#define CPM_CR_IDMA2_SBLOCK (0x15)
43#define CPM_CR_IDMA3_SBLOCK (0x16)
44#define CPM_CR_IDMA4_SBLOCK (0x17)
45#define CPM_CR_MCC1_SBLOCK (0x1c)
46
47#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
48
49#define CPM_CR_SCC1_PAGE (0x00)
50#define CPM_CR_SCC2_PAGE (0x01)
51#define CPM_CR_SCC3_PAGE (0x02)
52#define CPM_CR_SCC4_PAGE (0x03)
53#define CPM_CR_SMC1_PAGE (0x07)
54#define CPM_CR_SMC2_PAGE (0x08)
55#define CPM_CR_SPI_PAGE (0x09)
56#define CPM_CR_I2C_PAGE (0x0a)
57#define CPM_CR_TIMER_PAGE (0x0a)
58#define CPM_CR_RAND_PAGE (0x0a)
59#define CPM_CR_FCC1_PAGE (0x04)
60#define CPM_CR_FCC2_PAGE (0x05)
61#define CPM_CR_FCC3_PAGE (0x06)
62#define CPM_CR_IDMA1_PAGE (0x07)
63#define CPM_CR_IDMA2_PAGE (0x08)
64#define CPM_CR_IDMA3_PAGE (0x09)
65#define CPM_CR_IDMA4_PAGE (0x0a)
66#define CPM_CR_MCC1_PAGE (0x07)
67#define CPM_CR_MCC2_PAGE (0x08)
68
69#define CPM_CR_FCC_PAGE(x) (x + 0x04)
70
71/* CPM2-specific opcodes (see cpm.h for common opcodes)
72*/
73#define CPM_CR_START_IDMA ((ushort)0x0009)
74
75#define mk_cr_cmd(PG, SBC, MCN, OP) \
76 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
77
78/* The number of pages of host memory we allocate for CPM. This is
79 * done early in kernel initialization to get physically contiguous
80 * pages.
81 */
82#define NUM_CPM_HOST_PAGES 2
83
84/* Export the base address of the communication processor registers
85 * and dual port ram.
86 */
87extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
88
89#define cpm_dpalloc cpm_muram_alloc
90#define cpm_dpfree cpm_muram_free
91#define cpm_dpram_addr cpm_muram_addr
92
93extern void cpm2_reset(void);
94
95/* Baud rate generators.
96*/
97#define CPM_BRG_RST ((uint)0x00020000)
98#define CPM_BRG_EN ((uint)0x00010000)
99#define CPM_BRG_EXTC_INT ((uint)0x00000000)
100#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
101#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
102#define CPM_BRG_ATB ((uint)0x00002000)
103#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
104#define CPM_BRG_DIV16 ((uint)0x00000001)
105
106#define CPM2_BRG_INT_CLK (get_brgfreq())
107#define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16)
108
109extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
110
111/* This function is used by UARTS, or anything else that uses a 16x
112 * oversampled clock.
113 */
114static inline void cpm_setbrg(uint brg, uint rate)
115{
116 __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
117}
118
119/* This function is used to set high speed synchronous baud rate
120 * clocks.
121 */
122static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
123{
124 __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
125}
126
127/* Function code bits, usually generic to devices.
128*/
129#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
130#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
131#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
132#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
133#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
134
135/* Parameter RAM offsets from the base.
136*/
137#define PROFF_SCC1 ((uint)0x8000)
138#define PROFF_SCC2 ((uint)0x8100)
139#define PROFF_SCC3 ((uint)0x8200)
140#define PROFF_SCC4 ((uint)0x8300)
141#define PROFF_FCC1 ((uint)0x8400)
142#define PROFF_FCC2 ((uint)0x8500)
143#define PROFF_FCC3 ((uint)0x8600)
144#define PROFF_MCC1 ((uint)0x8700)
145#define PROFF_SMC1_BASE ((uint)0x87fc)
146#define PROFF_IDMA1_BASE ((uint)0x87fe)
147#define PROFF_MCC2 ((uint)0x8800)
148#define PROFF_SMC2_BASE ((uint)0x88fc)
149#define PROFF_IDMA2_BASE ((uint)0x88fe)
150#define PROFF_SPI_BASE ((uint)0x89fc)
151#define PROFF_IDMA3_BASE ((uint)0x89fe)
152#define PROFF_TIMERS ((uint)0x8ae0)
153#define PROFF_REVNUM ((uint)0x8af0)
154#define PROFF_RAND ((uint)0x8af8)
155#define PROFF_I2C_BASE ((uint)0x8afc)
156#define PROFF_IDMA4_BASE ((uint)0x8afe)
157
158#define PROFF_SCC_SIZE ((uint)0x100)
159#define PROFF_FCC_SIZE ((uint)0x100)
160#define PROFF_SMC_SIZE ((uint)64)
161
162/* The SMCs are relocated to any of the first eight DPRAM pages.
163 * We will fix these at the first locations of DPRAM, until we
164 * get some microcode patches :-).
165 * The parameter ram space for the SMCs is fifty-some bytes, and
166 * they are required to start on a 64 byte boundary.
167 */
168#define PROFF_SMC1 (0)
169#define PROFF_SMC2 (64)
170
171
172/* Define enough so I can at least use the serial port as a UART.
173 */
174typedef struct smc_uart {
175 ushort smc_rbase; /* Rx Buffer descriptor base address */
176 ushort smc_tbase; /* Tx Buffer descriptor base address */
177 u_char smc_rfcr; /* Rx function code */
178 u_char smc_tfcr; /* Tx function code */
179 ushort smc_mrblr; /* Max receive buffer length */
180 uint smc_rstate; /* Internal */
181 uint smc_idp; /* Internal */
182 ushort smc_rbptr; /* Internal */
183 ushort smc_ibc; /* Internal */
184 uint smc_rxtmp; /* Internal */
185 uint smc_tstate; /* Internal */
186 uint smc_tdp; /* Internal */
187 ushort smc_tbptr; /* Internal */
188 ushort smc_tbc; /* Internal */
189 uint smc_txtmp; /* Internal */
190 ushort smc_maxidl; /* Maximum idle characters */
191 ushort smc_tmpidl; /* Temporary idle counter */
192 ushort smc_brklen; /* Last received break length */
193 ushort smc_brkec; /* rcv'd break condition counter */
194 ushort smc_brkcr; /* xmt break count register */
195 ushort smc_rmask; /* Temporary bit mask */
196 uint smc_stmp; /* SDMA Temp */
197} smc_uart_t;
198
199/* SMC uart mode register (Internal memory map).
200*/
201#define SMCMR_REN ((ushort)0x0001)
202#define SMCMR_TEN ((ushort)0x0002)
203#define SMCMR_DM ((ushort)0x000c)
204#define SMCMR_SM_GCI ((ushort)0x0000)
205#define SMCMR_SM_UART ((ushort)0x0020)
206#define SMCMR_SM_TRANS ((ushort)0x0030)
207#define SMCMR_SM_MASK ((ushort)0x0030)
208#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
209#define SMCMR_REVD SMCMR_PM_EVEN
210#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
211#define SMCMR_BS SMCMR_PEN
212#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
213#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
214#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
215
216/* SMC Event and Mask register.
217*/
218#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
219#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
220#define SMCM_TXE ((unsigned char)0x10)
221#define SMCM_BSY ((unsigned char)0x04)
222#define SMCM_TX ((unsigned char)0x02)
223#define SMCM_RX ((unsigned char)0x01)
224
225/* SCCs.
226*/
227#define SCC_GSMRH_IRP ((uint)0x00040000)
228#define SCC_GSMRH_GDE ((uint)0x00010000)
229#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
230#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
231#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
232#define SCC_GSMRH_REVD ((uint)0x00002000)
233#define SCC_GSMRH_TRX ((uint)0x00001000)
234#define SCC_GSMRH_TTX ((uint)0x00000800)
235#define SCC_GSMRH_CDP ((uint)0x00000400)
236#define SCC_GSMRH_CTSP ((uint)0x00000200)
237#define SCC_GSMRH_CDS ((uint)0x00000100)
238#define SCC_GSMRH_CTSS ((uint)0x00000080)
239#define SCC_GSMRH_TFL ((uint)0x00000040)
240#define SCC_GSMRH_RFW ((uint)0x00000020)
241#define SCC_GSMRH_TXSY ((uint)0x00000010)
242#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
243#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
244#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
245#define SCC_GSMRH_RTSM ((uint)0x00000002)
246#define SCC_GSMRH_RSYN ((uint)0x00000001)
247
248#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
249#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
250#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
251#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
252#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
253#define SCC_GSMRL_TCI ((uint)0x10000000)
254#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
255#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
256#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
257#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
258#define SCC_GSMRL_RINV ((uint)0x02000000)
259#define SCC_GSMRL_TINV ((uint)0x01000000)
260#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
261#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
262#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
263#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
264#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
265#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
266#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
267#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
268#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
269#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
270#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
271#define SCC_GSMRL_TEND ((uint)0x00040000)
272#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
273#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
274#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
275#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
276#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
277#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
278#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
279#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
280#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
281#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
282#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
283#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
284#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
285#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
286#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
287#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
288#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
289#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
290#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
291#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
292#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
293#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
294#define SCC_GSMRL_ENR ((uint)0x00000020)
295#define SCC_GSMRL_ENT ((uint)0x00000010)
296#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
297#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
298#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
299#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
300#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
301#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
302#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
303#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
304#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
305#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
306
307#define SCC_TODR_TOD ((ushort)0x8000)
308
309/* SCC Event and Mask register.
310*/
311#define SCCM_TXE ((unsigned char)0x10)
312#define SCCM_BSY ((unsigned char)0x04)
313#define SCCM_TX ((unsigned char)0x02)
314#define SCCM_RX ((unsigned char)0x01)
315
316typedef struct scc_param {
317 ushort scc_rbase; /* Rx Buffer descriptor base address */
318 ushort scc_tbase; /* Tx Buffer descriptor base address */
319 u_char scc_rfcr; /* Rx function code */
320 u_char scc_tfcr; /* Tx function code */
321 ushort scc_mrblr; /* Max receive buffer length */
322 uint scc_rstate; /* Internal */
323 uint scc_idp; /* Internal */
324 ushort scc_rbptr; /* Internal */
325 ushort scc_ibc; /* Internal */
326 uint scc_rxtmp; /* Internal */
327 uint scc_tstate; /* Internal */
328 uint scc_tdp; /* Internal */
329 ushort scc_tbptr; /* Internal */
330 ushort scc_tbc; /* Internal */
331 uint scc_txtmp; /* Internal */
332 uint scc_rcrc; /* Internal */
333 uint scc_tcrc; /* Internal */
334} sccp_t;
335
336/* Function code bits.
337*/
338#define SCC_EB ((u_char) 0x10) /* Set big endian byte order */
339#define SCC_GBL ((u_char) 0x20) /* Snooping enabled */
340
341/* CPM Ethernet through SCC1.
342 */
343typedef struct scc_enet {
344 sccp_t sen_genscc;
345 uint sen_cpres; /* Preset CRC */
346 uint sen_cmask; /* Constant mask for CRC */
347 uint sen_crcec; /* CRC Error counter */
348 uint sen_alec; /* alignment error counter */
349 uint sen_disfc; /* discard frame counter */
350 ushort sen_pads; /* Tx short frame pad character */
351 ushort sen_retlim; /* Retry limit threshold */
352 ushort sen_retcnt; /* Retry limit counter */
353 ushort sen_maxflr; /* maximum frame length register */
354 ushort sen_minflr; /* minimum frame length register */
355 ushort sen_maxd1; /* maximum DMA1 length */
356 ushort sen_maxd2; /* maximum DMA2 length */
357 ushort sen_maxd; /* Rx max DMA */
358 ushort sen_dmacnt; /* Rx DMA counter */
359 ushort sen_maxb; /* Max BD byte count */
360 ushort sen_gaddr1; /* Group address filter */
361 ushort sen_gaddr2;
362 ushort sen_gaddr3;
363 ushort sen_gaddr4;
364 uint sen_tbuf0data0; /* Save area 0 - current frame */
365 uint sen_tbuf0data1; /* Save area 1 - current frame */
366 uint sen_tbuf0rba; /* Internal */
367 uint sen_tbuf0crc; /* Internal */
368 ushort sen_tbuf0bcnt; /* Internal */
369 ushort sen_paddrh; /* physical address (MSB) */
370 ushort sen_paddrm;
371 ushort sen_paddrl; /* physical address (LSB) */
372 ushort sen_pper; /* persistence */
373 ushort sen_rfbdptr; /* Rx first BD pointer */
374 ushort sen_tfbdptr; /* Tx first BD pointer */
375 ushort sen_tlbdptr; /* Tx last BD pointer */
376 uint sen_tbuf1data0; /* Save area 0 - current frame */
377 uint sen_tbuf1data1; /* Save area 1 - current frame */
378 uint sen_tbuf1rba; /* Internal */
379 uint sen_tbuf1crc; /* Internal */
380 ushort sen_tbuf1bcnt; /* Internal */
381 ushort sen_txlen; /* Tx Frame length counter */
382 ushort sen_iaddr1; /* Individual address filter */
383 ushort sen_iaddr2;
384 ushort sen_iaddr3;
385 ushort sen_iaddr4;
386 ushort sen_boffcnt; /* Backoff counter */
387
388 /* NOTE: Some versions of the manual have the following items
389 * incorrectly documented. Below is the proper order.
390 */
391 ushort sen_taddrh; /* temp address (MSB) */
392 ushort sen_taddrm;
393 ushort sen_taddrl; /* temp address (LSB) */
394} scc_enet_t;
395
396
397/* SCC Event register as used by Ethernet.
398*/
399#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
400#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
401#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
402#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
403#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
404#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
405
406/* SCC Mode Register (PSMR) as used by Ethernet.
407*/
408#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
409#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
410#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
411#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
412#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
413#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
414#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
415#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
416#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
417#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
418#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
419#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
420#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
421
422/* SCC as UART
423*/
424typedef struct scc_uart {
425 sccp_t scc_genscc;
426 uint scc_res1; /* Reserved */
427 uint scc_res2; /* Reserved */
428 ushort scc_maxidl; /* Maximum idle chars */
429 ushort scc_idlc; /* temp idle counter */
430 ushort scc_brkcr; /* Break count register */
431 ushort scc_parec; /* receive parity error counter */
432 ushort scc_frmec; /* receive framing error counter */
433 ushort scc_nosec; /* receive noise counter */
434 ushort scc_brkec; /* receive break condition counter */
435 ushort scc_brkln; /* last received break length */
436 ushort scc_uaddr1; /* UART address character 1 */
437 ushort scc_uaddr2; /* UART address character 2 */
438 ushort scc_rtemp; /* Temp storage */
439 ushort scc_toseq; /* Transmit out of sequence char */
440 ushort scc_char1; /* control character 1 */
441 ushort scc_char2; /* control character 2 */
442 ushort scc_char3; /* control character 3 */
443 ushort scc_char4; /* control character 4 */
444 ushort scc_char5; /* control character 5 */
445 ushort scc_char6; /* control character 6 */
446 ushort scc_char7; /* control character 7 */
447 ushort scc_char8; /* control character 8 */
448 ushort scc_rccm; /* receive control character mask */
449 ushort scc_rccr; /* receive control character register */
450 ushort scc_rlbc; /* receive last break character */
451} scc_uart_t;
452
453/* SCC Event and Mask registers when it is used as a UART.
454*/
455#define UART_SCCM_GLR ((ushort)0x1000)
456#define UART_SCCM_GLT ((ushort)0x0800)
457#define UART_SCCM_AB ((ushort)0x0200)
458#define UART_SCCM_IDL ((ushort)0x0100)
459#define UART_SCCM_GRA ((ushort)0x0080)
460#define UART_SCCM_BRKE ((ushort)0x0040)
461#define UART_SCCM_BRKS ((ushort)0x0020)
462#define UART_SCCM_CCR ((ushort)0x0008)
463#define UART_SCCM_BSY ((ushort)0x0004)
464#define UART_SCCM_TX ((ushort)0x0002)
465#define UART_SCCM_RX ((ushort)0x0001)
466
467/* The SCC PSMR when used as a UART.
468*/
469#define SCU_PSMR_FLC ((ushort)0x8000)
470#define SCU_PSMR_SL ((ushort)0x4000)
471#define SCU_PSMR_CL ((ushort)0x3000)
472#define SCU_PSMR_UM ((ushort)0x0c00)
473#define SCU_PSMR_FRZ ((ushort)0x0200)
474#define SCU_PSMR_RZS ((ushort)0x0100)
475#define SCU_PSMR_SYN ((ushort)0x0080)
476#define SCU_PSMR_DRT ((ushort)0x0040)
477#define SCU_PSMR_PEN ((ushort)0x0010)
478#define SCU_PSMR_RPM ((ushort)0x000c)
479#define SCU_PSMR_REVP ((ushort)0x0008)
480#define SCU_PSMR_TPM ((ushort)0x0003)
481#define SCU_PSMR_TEVP ((ushort)0x0002)
482
483/* CPM Transparent mode SCC.
484 */
485typedef struct scc_trans {
486 sccp_t st_genscc;
487 uint st_cpres; /* Preset CRC */
488 uint st_cmask; /* Constant mask for CRC */
489} scc_trans_t;
490
491/* How about some FCCs.....
492*/
493#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
494#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
495#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
496#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
497#define FCC_GFMR_TCI ((uint)0x20000000)
498#define FCC_GFMR_TRX ((uint)0x10000000)
499#define FCC_GFMR_TTX ((uint)0x08000000)
500#define FCC_GFMR_TTX ((uint)0x08000000)
501#define FCC_GFMR_CDP ((uint)0x04000000)
502#define FCC_GFMR_CTSP ((uint)0x02000000)
503#define FCC_GFMR_CDS ((uint)0x01000000)
504#define FCC_GFMR_CTSS ((uint)0x00800000)
505#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
506#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
507#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
508#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
509#define FCC_GFMR_RTSM ((uint)0x00002000)
510#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
511#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
512#define FCC_GFMR_REVD ((uint)0x00000400)
513#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
514#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
515#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
516#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
517#define FCC_GFMR_ENR ((uint)0x00000020)
518#define FCC_GFMR_ENT ((uint)0x00000010)
519#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
520#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
521#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
522
523/* Generic FCC parameter ram.
524*/
525typedef struct fcc_param {
526 ushort fcc_riptr; /* Rx Internal temp pointer */
527 ushort fcc_tiptr; /* Tx Internal temp pointer */
528 ushort fcc_res1;
529 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
530 uint fcc_rstate; /* Upper byte is Func code, must be set */
531 uint fcc_rbase; /* Receive BD base */
532 ushort fcc_rbdstat; /* RxBD status */
533 ushort fcc_rbdlen; /* RxBD down counter */
534 uint fcc_rdptr; /* RxBD internal data pointer */
535 uint fcc_tstate; /* Upper byte is Func code, must be set */
536 uint fcc_tbase; /* Transmit BD base */
537 ushort fcc_tbdstat; /* TxBD status */
538 ushort fcc_tbdlen; /* TxBD down counter */
539 uint fcc_tdptr; /* TxBD internal data pointer */
540 uint fcc_rbptr; /* Rx BD Internal buf pointer */
541 uint fcc_tbptr; /* Tx BD Internal buf pointer */
542 uint fcc_rcrc; /* Rx temp CRC */
543 uint fcc_res2;
544 uint fcc_tcrc; /* Tx temp CRC */
545} fccp_t;
546
547
548/* Ethernet controller through FCC.
549*/
550typedef struct fcc_enet {
551 fccp_t fen_genfcc;
552 uint fen_statbuf; /* Internal status buffer */
553 uint fen_camptr; /* CAM address */
554 uint fen_cmask; /* Constant mask for CRC */
555 uint fen_cpres; /* Preset CRC */
556 uint fen_crcec; /* CRC Error counter */
557 uint fen_alec; /* alignment error counter */
558 uint fen_disfc; /* discard frame counter */
559 ushort fen_retlim; /* Retry limit */
560 ushort fen_retcnt; /* Retry counter */
561 ushort fen_pper; /* Persistence */
562 ushort fen_boffcnt; /* backoff counter */
563 uint fen_gaddrh; /* Group address filter, high 32-bits */
564 uint fen_gaddrl; /* Group address filter, low 32-bits */
565 ushort fen_tfcstat; /* out of sequence TxBD */
566 ushort fen_tfclen;
567 uint fen_tfcptr;
568 ushort fen_mflr; /* Maximum frame length (1518) */
569 ushort fen_paddrh; /* MAC address */
570 ushort fen_paddrm;
571 ushort fen_paddrl;
572 ushort fen_ibdcount; /* Internal BD counter */
573 ushort fen_ibdstart; /* Internal BD start pointer */
574 ushort fen_ibdend; /* Internal BD end pointer */
575 ushort fen_txlen; /* Internal Tx frame length counter */
576 uint fen_ibdbase[8]; /* Internal use */
577 uint fen_iaddrh; /* Individual address filter */
578 uint fen_iaddrl;
579 ushort fen_minflr; /* Minimum frame length (64) */
580 ushort fen_taddrh; /* Filter transfer MAC address */
581 ushort fen_taddrm;
582 ushort fen_taddrl;
583 ushort fen_padptr; /* Pointer to pad byte buffer */
584 ushort fen_cftype; /* control frame type */
585 ushort fen_cfrange; /* control frame range */
586 ushort fen_maxb; /* maximum BD count */
587 ushort fen_maxd1; /* Max DMA1 length (1520) */
588 ushort fen_maxd2; /* Max DMA2 length (1520) */
589 ushort fen_maxd; /* internal max DMA count */
590 ushort fen_dmacnt; /* internal DMA counter */
591 uint fen_octc; /* Total octect counter */
592 uint fen_colc; /* Total collision counter */
593 uint fen_broc; /* Total broadcast packet counter */
594 uint fen_mulc; /* Total multicast packet count */
595 uint fen_uspc; /* Total packets < 64 bytes */
596 uint fen_frgc; /* Total packets < 64 bytes with errors */
597 uint fen_ospc; /* Total packets > 1518 */
598 uint fen_jbrc; /* Total packets > 1518 with errors */
599 uint fen_p64c; /* Total packets == 64 bytes */
600 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
601 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
602 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
603 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
604 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
605 uint fen_cambuf; /* Internal CAM buffer poiner */
606 ushort fen_rfthr; /* Received frames threshold */
607 ushort fen_rfcnt; /* Received frames count */
608} fcc_enet_t;
609
610/* FCC Event/Mask register as used by Ethernet.
611*/
612#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
613#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
614#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
615#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
616#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
617#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
618#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
619#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
620
621/* FCC Mode Register (FPSMR) as used by Ethernet.
622*/
623#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
624#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
625#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
626#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
627#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
628#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
629#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
630#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
631#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
632#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
633#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
634#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
635#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
636
637/* IIC parameter RAM.
638*/
639typedef struct iic {
640 ushort iic_rbase; /* Rx Buffer descriptor base address */
641 ushort iic_tbase; /* Tx Buffer descriptor base address */
642 u_char iic_rfcr; /* Rx function code */
643 u_char iic_tfcr; /* Tx function code */
644 ushort iic_mrblr; /* Max receive buffer length */
645 uint iic_rstate; /* Internal */
646 uint iic_rdp; /* Internal */
647 ushort iic_rbptr; /* Internal */
648 ushort iic_rbc; /* Internal */
649 uint iic_rxtmp; /* Internal */
650 uint iic_tstate; /* Internal */
651 uint iic_tdp; /* Internal */
652 ushort iic_tbptr; /* Internal */
653 ushort iic_tbc; /* Internal */
654 uint iic_txtmp; /* Internal */
655} iic_t;
656
657/* SPI parameter RAM.
658*/
659typedef struct spi {
660 ushort spi_rbase; /* Rx Buffer descriptor base address */
661 ushort spi_tbase; /* Tx Buffer descriptor base address */
662 u_char spi_rfcr; /* Rx function code */
663 u_char spi_tfcr; /* Tx function code */
664 ushort spi_mrblr; /* Max receive buffer length */
665 uint spi_rstate; /* Internal */
666 uint spi_rdp; /* Internal */
667 ushort spi_rbptr; /* Internal */
668 ushort spi_rbc; /* Internal */
669 uint spi_rxtmp; /* Internal */
670 uint spi_tstate; /* Internal */
671 uint spi_tdp; /* Internal */
672 ushort spi_tbptr; /* Internal */
673 ushort spi_tbc; /* Internal */
674 uint spi_txtmp; /* Internal */
675 uint spi_res; /* Tx temp. */
676 uint spi_res1[4]; /* SDMA temp. */
677} spi_t;
678
679/* SPI Mode register.
680*/
681#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
682#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
683#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
684#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
685#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
686#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
687#define SPMODE_EN ((ushort)0x0100) /* Enable */
688#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
689#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
690
691#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
692#define SPMODE_PM(x) ((x) &0xF)
693
694#define SPI_EB ((u_char)0x10) /* big endian byte order */
695
696/* IDMA parameter RAM
697*/
698typedef struct idma {
699 ushort ibase; /* IDMA buffer descriptor table base address */
700 ushort dcm; /* DMA channel mode */
701 ushort ibdptr; /* IDMA current buffer descriptor pointer */
702 ushort dpr_buf; /* IDMA transfer buffer base address */
703 ushort buf_inv; /* internal buffer inventory */
704 ushort ss_max; /* steady-state maximum transfer size */
705 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
706 ushort sts; /* source transfer size */
707 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
708 ushort seob; /* source end of burst */
709 ushort deob; /* destination end of burst */
710 ushort dts; /* destination transfer size */
711 ushort ret_add; /* return address when working in ERM=1 mode */
712 ushort res0; /* reserved */
713 uint bd_cnt; /* internal byte count */
714 uint s_ptr; /* source internal data pointer */
715 uint d_ptr; /* destination internal data pointer */
716 uint istate; /* internal state */
717 u_char res1[20]; /* pad to 64-byte length */
718} idma_t;
719
720/* DMA channel mode bit fields
721*/
722#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
723#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
724#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
725#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
726#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
727#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
728#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
729#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
730#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
731#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
732#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
733#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
734#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
735#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
736#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
737#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
738#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
739#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
740
741/* IDMA Buffer Descriptors
742*/
743typedef struct idma_bd {
744 uint flags;
745 uint len; /* data length */
746 uint src; /* source data buffer pointer */
747 uint dst; /* destination data buffer pointer */
748} idma_bd_t;
749
750/* IDMA buffer descriptor flag bit fields
751*/
752#define IDMA_BD_V ((uint)0x80000000) /* valid */
753#define IDMA_BD_W ((uint)0x20000000) /* wrap */
754#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
755#define IDMA_BD_L ((uint)0x08000000) /* last */
756#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
757#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
758#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
759#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
760#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
761#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
762#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
763#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
764#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
765#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
766#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
767
768/* per-channel IDMA registers
769*/
770typedef struct im_idma {
771 u_char idsr; /* IDMAn event status register */
772 u_char res0[3];
773 u_char idmr; /* IDMAn event mask register */
774 u_char res1[3];
775} im_idma_t;
776
777/* IDMA event register bit fields
778*/
779#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
780#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
781#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
782#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
783
784/* RISC Controller Configuration Register (RCCR) bit fields
785*/
786#define RCCR_TIME ((uint)0x80000000) /* timer enable */
787#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
788#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
789#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
790#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
791#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
792#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
793#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
794#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
795#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
796#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
797#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
798#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
799#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
800#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
801#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
802#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
803#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
804#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
805#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
806#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
807#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
808#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
809#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
810#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
811#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
812#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
813#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
814#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
815#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
816#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
817#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
818#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
819#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
820#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
821#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
822#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
823#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
824
825/*-----------------------------------------------------------------------
826 * CMXFCR - CMX FCC Clock Route Register
827 */
828#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
829#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
830#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
831#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
832#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
833#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
834#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
835#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
836#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
837
838#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
839#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
840#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
841#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
842#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
843#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
844#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
845#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
846
847#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
848#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
849#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
850#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
851#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
852#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
853#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
854#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
855
856#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
857#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
858#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
859#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
860#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
861#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
862#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
863#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
864
865#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
866#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
867#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
868#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
869#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
870#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
871#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
872#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
873
874#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
875#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
876#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
877#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
878#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
879#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
880#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
881#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
882
883#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
884#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
885#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
886#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
887#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
888#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
889#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
890#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
891
892/*-----------------------------------------------------------------------
893 * CMXSCR - CMX SCC Clock Route Register
894 */
895#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
896#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
897#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
898#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
899#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
900#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
901#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
902#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
903#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
904#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
905#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
906#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
907#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
908#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
909#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
910#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
911
912#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
913#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
914#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
915#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
916#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
917#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
918#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
919#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
920
921#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
922#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
923#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
924#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
925#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
926#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
927#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
928#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
929
930#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
931#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
932#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
933#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
934#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
935#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
936#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
937#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
938
939#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
940#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
941#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
942#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
943#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
944#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
945#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
946#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
947
948#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
949#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
950#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
951#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
952#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
953#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
954#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
955#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
956
957#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
958#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
959#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
960#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
961#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
962#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
963#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
964#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
965
966#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
967#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
968#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
969#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
970#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
971#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
972#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
973#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
974
975#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
976#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
977#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
978#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
979#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
980#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
981#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
982#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
983
984/*-----------------------------------------------------------------------
985 * SIUMCR - SIU Module Configuration Register 4-31
986 */
987#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
988#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
989#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
990#define SIUMCR_CDIS 0x10000000 /* Core Disable */
991#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
992#define SIUMCR_DPPC01 0x04000000 /* - " - */
993#define SIUMCR_DPPC10 0x08000000 /* - " - */
994#define SIUMCR_DPPC11 0x0c000000 /* - " - */
995#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
996#define SIUMCR_L2CPC01 0x01000000 /* - " - */
997#define SIUMCR_L2CPC10 0x02000000 /* - " - */
998#define SIUMCR_L2CPC11 0x03000000 /* - " - */
999#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1000#define SIUMCR_LBPC01 0x00400000 /* - " - */
1001#define SIUMCR_LBPC10 0x00800000 /* - " - */
1002#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1003#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1004#define SIUMCR_APPC01 0x00100000 /* - " - */
1005#define SIUMCR_APPC10 0x00200000 /* - " - */
1006#define SIUMCR_APPC11 0x00300000 /* - " - */
1007#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1008#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1009#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1010#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1011#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1012#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1013#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1014#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1015#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1016#define SIUMCR_MMR01 0x00004000 /* - " - */
1017#define SIUMCR_MMR10 0x00008000 /* - " - */
1018#define SIUMCR_MMR11 0x0000c000 /* - " - */
1019#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1020
1021/*-----------------------------------------------------------------------
1022 * SCCR - System Clock Control Register 9-8
1023*/
1024#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1025#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1026#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1027#define SCCR_PCIDF_SHIFT 3
1028
1029#ifndef CPM_IMMR_OFFSET
1030#define CPM_IMMR_OFFSET 0x101a8
1031#endif
1032
1033#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1034
1035/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1036 * in order to use clock-computing stuff below for the FCC x
1037 */
1038
1039/* Automatically generates register configurations */
1040#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1041
1042#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1043#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1044#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1045#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1046#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1047#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1048
1049#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1050#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1051#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1052#define CMX1_CLK_MASK ((uint)0xff000000)
1053
1054#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1055#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1056#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1057#define CMX2_CLK_MASK ((uint)0x00ff0000)
1058
1059#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1060#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1061#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1062#define CMX3_CLK_MASK ((uint)0x0000ff00)
1063
1064#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1065#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1066
1067#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1068
1069/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1070 * but there is little variation among the choices.
1071 */
1072#define PA1_COL 0x00000001U
1073#define PA1_CRS 0x00000002U
1074#define PA1_TXER 0x00000004U
1075#define PA1_TXEN 0x00000008U
1076#define PA1_RXDV 0x00000010U
1077#define PA1_RXER 0x00000020U
1078#define PA1_TXDAT 0x00003c00U
1079#define PA1_RXDAT 0x0003c000U
1080#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1081#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1082 PA1_RXDV | PA1_RXER)
1083#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1084#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1085
1086
1087/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1088 * but there is little variation among the choices.
1089 */
1090#define PB2_TXER 0x00000001U
1091#define PB2_RXDV 0x00000002U
1092#define PB2_TXEN 0x00000004U
1093#define PB2_RXER 0x00000008U
1094#define PB2_COL 0x00000010U
1095#define PB2_CRS 0x00000020U
1096#define PB2_TXDAT 0x000003c0U
1097#define PB2_RXDAT 0x00003c00U
1098#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1099 PB2_RXER | PB2_RXDV | PB2_TXER)
1100#define PB2_PSORB1 (PB2_TXEN)
1101#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1102#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1103
1104
1105/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1106 * but there is little variation among the choices.
1107 */
1108#define PB3_RXDV 0x00004000U
1109#define PB3_RXER 0x00008000U
1110#define PB3_TXER 0x00010000U
1111#define PB3_TXEN 0x00020000U
1112#define PB3_COL 0x00040000U
1113#define PB3_CRS 0x00080000U
1114#define PB3_TXDAT 0x0f000000U
1115#define PC3_TXDAT 0x00000010U
1116#define PB3_RXDAT 0x00f00000U
1117#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1118 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1119#define PB3_PSORB1 0
1120#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1121#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1122#define PC3_DIRC1 (PC3_TXDAT)
1123
1124/* Handy macro to specify mem for FCCs*/
1125#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1126#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1127#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1128#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1129
1130/* Clocks and GRG's */
1131
1132enum cpm_clk_dir {
1133 CPM_CLK_RX,
1134 CPM_CLK_TX,
1135 CPM_CLK_RTX
1136};
1137
1138enum cpm_clk_target {
1139 CPM_CLK_SCC1,
1140 CPM_CLK_SCC2,
1141 CPM_CLK_SCC3,
1142 CPM_CLK_SCC4,
1143 CPM_CLK_FCC1,
1144 CPM_CLK_FCC2,
1145 CPM_CLK_FCC3,
1146 CPM_CLK_SMC1,
1147 CPM_CLK_SMC2,
1148};
1149
1150enum cpm_clk {
1151 CPM_CLK_NONE = 0,
1152 CPM_BRG1, /* Baud Rate Generator 1 */
1153 CPM_BRG2, /* Baud Rate Generator 2 */
1154 CPM_BRG3, /* Baud Rate Generator 3 */
1155 CPM_BRG4, /* Baud Rate Generator 4 */
1156 CPM_BRG5, /* Baud Rate Generator 5 */
1157 CPM_BRG6, /* Baud Rate Generator 6 */
1158 CPM_BRG7, /* Baud Rate Generator 7 */
1159 CPM_BRG8, /* Baud Rate Generator 8 */
1160 CPM_CLK1, /* Clock 1 */
1161 CPM_CLK2, /* Clock 2 */
1162 CPM_CLK3, /* Clock 3 */
1163 CPM_CLK4, /* Clock 4 */
1164 CPM_CLK5, /* Clock 5 */
1165 CPM_CLK6, /* Clock 6 */
1166 CPM_CLK7, /* Clock 7 */
1167 CPM_CLK8, /* Clock 8 */
1168 CPM_CLK9, /* Clock 9 */
1169 CPM_CLK10, /* Clock 10 */
1170 CPM_CLK11, /* Clock 11 */
1171 CPM_CLK12, /* Clock 12 */
1172 CPM_CLK13, /* Clock 13 */
1173 CPM_CLK14, /* Clock 14 */
1174 CPM_CLK15, /* Clock 15 */
1175 CPM_CLK16, /* Clock 16 */
1176 CPM_CLK17, /* Clock 17 */
1177 CPM_CLK18, /* Clock 18 */
1178 CPM_CLK19, /* Clock 19 */
1179 CPM_CLK20, /* Clock 20 */
1180 CPM_CLK_DUMMY
1181};
1182
1183extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1184extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
1185
1186#define CPM_PIN_INPUT 0
1187#define CPM_PIN_OUTPUT 1
1188#define CPM_PIN_PRIMARY 0
1189#define CPM_PIN_SECONDARY 2
1190#define CPM_PIN_GPIO 4
1191#define CPM_PIN_OPENDRAIN 8
1192
1193void cpm2_set_pin(int port, int pin, int flags);
1194
1195#endif /* __CPM2__ */
1196#endif /* __KERNEL__ */