tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * MPC8548 CDS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23/*
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26*/
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 pci2 = &pci2;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 PowerPC,8548@0 {
39 device_type = "cpu";
40 reg = <0x0>;
41 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot
48 next-level-cache = <&L2>;
49 };
50 };
51
52 memory {
53 device_type = "memory";
54 reg = <0x0 0x8000000>; // 128M at 0x0
55 };
56
57 soc8548@e0000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 device_type = "soc";
61 compatible = "simple-bus";
62 ranges = <0x0 0xe0000000 0x100000>;
63 bus-frequency = <0>;
64
65 ecm-law@0 {
66 compatible = "fsl,ecm-law";
67 reg = <0x0 0x1000>;
68 fsl,num-laws = <10>;
69 };
70
71 ecm@1000 {
72 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
73 reg = <0x1000 0x1000>;
74 interrupts = <17 2>;
75 interrupt-parent = <&mpic>;
76 };
77
78 memory-controller@2000 {
79 compatible = "fsl,8548-memory-controller";
80 reg = <0x2000 0x1000>;
81 interrupt-parent = <&mpic>;
82 interrupts = <18 2>;
83 };
84
85 L2: l2-cache-controller@20000 {
86 compatible = "fsl,8548-l2-cache-controller";
87 reg = <0x20000 0x1000>;
88 cache-line-size = <32>; // 32 bytes
89 cache-size = <0x80000>; // L2, 512K
90 interrupt-parent = <&mpic>;
91 interrupts = <16 2>;
92 };
93
94 i2c@3000 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <0>;
98 compatible = "fsl-i2c";
99 reg = <0x3000 0x100>;
100 interrupts = <43 2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103
104 eeprom@50 {
105 compatible = "atmel,24c64";
106 reg = <0x50>;
107 };
108
109 eeprom@56 {
110 compatible = "atmel,24c64";
111 reg = <0x56>;
112 };
113
114 eeprom@57 {
115 compatible = "atmel,24c64";
116 reg = <0x57>;
117 };
118 };
119
120 i2c@3100 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 cell-index = <1>;
124 compatible = "fsl-i2c";
125 reg = <0x3100 0x100>;
126 interrupts = <43 2>;
127 interrupt-parent = <&mpic>;
128 dfsrr;
129
130 eeprom@50 {
131 compatible = "atmel,24c64";
132 reg = <0x50>;
133 };
134 };
135
136 dma@21300 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
140 reg = <0x21300 0x4>;
141 ranges = <0x0 0x21100 0x200>;
142 cell-index = <0>;
143 dma-channel@0 {
144 compatible = "fsl,mpc8548-dma-channel",
145 "fsl,eloplus-dma-channel";
146 reg = <0x0 0x80>;
147 cell-index = <0>;
148 interrupt-parent = <&mpic>;
149 interrupts = <20 2>;
150 };
151 dma-channel@80 {
152 compatible = "fsl,mpc8548-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x80 0x80>;
155 cell-index = <1>;
156 interrupt-parent = <&mpic>;
157 interrupts = <21 2>;
158 };
159 dma-channel@100 {
160 compatible = "fsl,mpc8548-dma-channel",
161 "fsl,eloplus-dma-channel";
162 reg = <0x100 0x80>;
163 cell-index = <2>;
164 interrupt-parent = <&mpic>;
165 interrupts = <22 2>;
166 };
167 dma-channel@180 {
168 compatible = "fsl,mpc8548-dma-channel",
169 "fsl,eloplus-dma-channel";
170 reg = <0x180 0x80>;
171 cell-index = <3>;
172 interrupt-parent = <&mpic>;
173 interrupts = <23 2>;
174 };
175 };
176
177 enet0: ethernet@24000 {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 cell-index = <0>;
181 device_type = "network";
182 model = "eTSEC";
183 compatible = "gianfar";
184 reg = <0x24000 0x1000>;
185 ranges = <0x0 0x24000 0x1000>;
186 local-mac-address = [ 00 00 00 00 00 00 ];
187 interrupts = <29 2 30 2 34 2>;
188 interrupt-parent = <&mpic>;
189 tbi-handle = <&tbi0>;
190 phy-handle = <&phy0>;
191
192 mdio@520 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,gianfar-mdio";
196 reg = <0x520 0x20>;
197
198 phy0: ethernet-phy@0 {
199 interrupt-parent = <&mpic>;
200 interrupts = <5 1>;
201 reg = <0x0>;
202 device_type = "ethernet-phy";
203 };
204 phy1: ethernet-phy@1 {
205 interrupt-parent = <&mpic>;
206 interrupts = <5 1>;
207 reg = <0x1>;
208 device_type = "ethernet-phy";
209 };
210 phy2: ethernet-phy@2 {
211 interrupt-parent = <&mpic>;
212 interrupts = <5 1>;
213 reg = <0x2>;
214 device_type = "ethernet-phy";
215 };
216 phy3: ethernet-phy@3 {
217 interrupt-parent = <&mpic>;
218 interrupts = <5 1>;
219 reg = <0x3>;
220 device_type = "ethernet-phy";
221 };
222 tbi0: tbi-phy@11 {
223 reg = <0x11>;
224 device_type = "tbi-phy";
225 };
226 };
227 };
228
229 enet1: ethernet@25000 {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 cell-index = <1>;
233 device_type = "network";
234 model = "eTSEC";
235 compatible = "gianfar";
236 reg = <0x25000 0x1000>;
237 ranges = <0x0 0x25000 0x1000>;
238 local-mac-address = [ 00 00 00 00 00 00 ];
239 interrupts = <35 2 36 2 40 2>;
240 interrupt-parent = <&mpic>;
241 tbi-handle = <&tbi1>;
242 phy-handle = <&phy1>;
243
244 mdio@520 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "fsl,gianfar-tbi";
248 reg = <0x520 0x20>;
249
250 tbi1: tbi-phy@11 {
251 reg = <0x11>;
252 device_type = "tbi-phy";
253 };
254 };
255 };
256
257/* eTSEC 3/4 are currently broken
258 enet2: ethernet@26000 {
259 #address-cells = <1>;
260 #size-cells = <1>;
261 cell-index = <2>;
262 device_type = "network";
263 model = "eTSEC";
264 compatible = "gianfar";
265 reg = <0x26000 0x1000>;
266 ranges = <0x0 0x26000 0x1000>;
267 local-mac-address = [ 00 00 00 00 00 00 ];
268 interrupts = <31 2 32 2 33 2>;
269 interrupt-parent = <&mpic>;
270 tbi-handle = <&tbi2>;
271 phy-handle = <&phy2>;
272
273 mdio@520 {
274 #address-cells = <1>;
275 #size-cells = <0>;
276 compatible = "fsl,gianfar-tbi";
277 reg = <0x520 0x20>;
278
279 tbi2: tbi-phy@11 {
280 reg = <0x11>;
281 device_type = "tbi-phy";
282 };
283 };
284 };
285
286 enet3: ethernet@27000 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 cell-index = <3>;
290 device_type = "network";
291 model = "eTSEC";
292 compatible = "gianfar";
293 reg = <0x27000 0x1000>;
294 ranges = <0x0 0x27000 0x1000>;
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 interrupts = <37 2 38 2 39 2>;
297 interrupt-parent = <&mpic>;
298 tbi-handle = <&tbi3>;
299 phy-handle = <&phy3>;
300
301 mdio@520 {
302 #address-cells = <1>;
303 #size-cells = <0>;
304 compatible = "fsl,gianfar-tbi";
305 reg = <0x520 0x20>;
306
307 tbi3: tbi-phy@11 {
308 reg = <0x11>;
309 device_type = "tbi-phy";
310 };
311 };
312 };
313 */
314
315 serial0: serial@4500 {
316 cell-index = <0>;
317 device_type = "serial";
318 compatible = "ns16550";
319 reg = <0x4500 0x100>; // reg base, size
320 clock-frequency = <0>; // should we fill in in uboot?
321 interrupts = <42 2>;
322 interrupt-parent = <&mpic>;
323 };
324
325 serial1: serial@4600 {
326 cell-index = <1>;
327 device_type = "serial";
328 compatible = "ns16550";
329 reg = <0x4600 0x100>; // reg base, size
330 clock-frequency = <0>; // should we fill in in uboot?
331 interrupts = <42 2>;
332 interrupt-parent = <&mpic>;
333 };
334
335 global-utilities@e0000 { //global utilities reg
336 compatible = "fsl,mpc8548-guts";
337 reg = <0xe0000 0x1000>;
338 fsl,has-rstcr;
339 };
340
341 crypto@30000 {
342 compatible = "fsl,sec2.1", "fsl,sec2.0";
343 reg = <0x30000 0x10000>;
344 interrupts = <45 2>;
345 interrupt-parent = <&mpic>;
346 fsl,num-channels = <4>;
347 fsl,channel-fifo-len = <24>;
348 fsl,exec-units-mask = <0xfe>;
349 fsl,descriptor-types-mask = <0x12b0ebf>;
350 };
351
352 mpic: pic@40000 {
353 interrupt-controller;
354 #address-cells = <0>;
355 #interrupt-cells = <2>;
356 reg = <0x40000 0x40000>;
357 compatible = "chrp,open-pic";
358 device_type = "open-pic";
359 };
360 };
361
362 pci0: pci@e0008000 {
363 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
364 interrupt-map = <
365 /* IDSEL 0x4 (PCIX Slot 2) */
366 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
367 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
368 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
369 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
370
371 /* IDSEL 0x5 (PCIX Slot 3) */
372 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
373 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
374 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
375 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
376
377 /* IDSEL 0x6 (PCIX Slot 4) */
378 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
379 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
380 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
381 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
382
383 /* IDSEL 0x8 (PCIX Slot 5) */
384 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
385 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
386 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
387 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
388
389 /* IDSEL 0xC (Tsi310 bridge) */
390 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
391 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
392 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
393 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
394
395 /* IDSEL 0x14 (Slot 2) */
396 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
397 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
398 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
399 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
400
401 /* IDSEL 0x15 (Slot 3) */
402 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
403 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
404 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
405 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
406
407 /* IDSEL 0x16 (Slot 4) */
408 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
409 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
410 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
411 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
412
413 /* IDSEL 0x18 (Slot 5) */
414 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
415 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
416 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
417 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
418
419 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
420 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
421 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
422 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
423 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
424
425 interrupt-parent = <&mpic>;
426 interrupts = <24 2>;
427 bus-range = <0 0>;
428 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
429 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
430 clock-frequency = <66666666>;
431 #interrupt-cells = <1>;
432 #size-cells = <2>;
433 #address-cells = <3>;
434 reg = <0xe0008000 0x1000>;
435 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
436 device_type = "pci";
437
438 pci_bridge@1c {
439 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
440 interrupt-map = <
441
442 /* IDSEL 0x00 (PrPMC Site) */
443 0000 0x0 0x0 0x1 &mpic 0x0 0x1
444 0000 0x0 0x0 0x2 &mpic 0x1 0x1
445 0000 0x0 0x0 0x3 &mpic 0x2 0x1
446 0000 0x0 0x0 0x4 &mpic 0x3 0x1
447
448 /* IDSEL 0x04 (VIA chip) */
449 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
450 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
451 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
452 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
453
454 /* IDSEL 0x05 (8139) */
455 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
456
457 /* IDSEL 0x06 (Slot 6) */
458 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
459 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
460 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
461 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
462
463 /* IDESL 0x07 (Slot 7) */
464 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
465 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
466 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
467 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
468
469 reg = <0xe000 0x0 0x0 0x0 0x0>;
470 #interrupt-cells = <1>;
471 #size-cells = <2>;
472 #address-cells = <3>;
473 ranges = <0x2000000 0x0 0x80000000
474 0x2000000 0x0 0x80000000
475 0x0 0x20000000
476 0x1000000 0x0 0x0
477 0x1000000 0x0 0x0
478 0x0 0x80000>;
479 clock-frequency = <33333333>;
480
481 isa@4 {
482 device_type = "isa";
483 #interrupt-cells = <2>;
484 #size-cells = <1>;
485 #address-cells = <2>;
486 reg = <0x2000 0x0 0x0 0x0 0x0>;
487 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
488 interrupt-parent = <&i8259>;
489
490 i8259: interrupt-controller@20 {
491 interrupt-controller;
492 device_type = "interrupt-controller";
493 reg = <0x1 0x20 0x2
494 0x1 0xa0 0x2
495 0x1 0x4d0 0x2>;
496 #address-cells = <0>;
497 #interrupt-cells = <2>;
498 compatible = "chrp,iic";
499 interrupts = <0 1>;
500 interrupt-parent = <&mpic>;
501 };
502
503 rtc@70 {
504 compatible = "pnpPNP,b00";
505 reg = <0x1 0x70 0x2>;
506 };
507 };
508 };
509 };
510
511 pci1: pci@e0009000 {
512 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
513 interrupt-map = <
514
515 /* IDSEL 0x15 */
516 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
517 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
518 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
519 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
520
521 interrupt-parent = <&mpic>;
522 interrupts = <25 2>;
523 bus-range = <0 0>;
524 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
525 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
526 clock-frequency = <66666666>;
527 #interrupt-cells = <1>;
528 #size-cells = <2>;
529 #address-cells = <3>;
530 reg = <0xe0009000 0x1000>;
531 compatible = "fsl,mpc8540-pci";
532 device_type = "pci";
533 };
534
535 pci2: pcie@e000a000 {
536 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
537 interrupt-map = <
538
539 /* IDSEL 0x0 (PEX) */
540 00000 0x0 0x0 0x1 &mpic 0x0 0x1
541 00000 0x0 0x0 0x2 &mpic 0x1 0x1
542 00000 0x0 0x0 0x3 &mpic 0x2 0x1
543 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
544
545 interrupt-parent = <&mpic>;
546 interrupts = <26 2>;
547 bus-range = <0 255>;
548 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
549 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
550 clock-frequency = <33333333>;
551 #interrupt-cells = <1>;
552 #size-cells = <2>;
553 #address-cells = <3>;
554 reg = <0xe000a000 0x1000>;
555 compatible = "fsl,mpc8548-pcie";
556 device_type = "pci";
557 pcie@0 {
558 reg = <0x0 0x0 0x0 0x0 0x0>;
559 #size-cells = <2>;
560 #address-cells = <3>;
561 device_type = "pci";
562 ranges = <0x2000000 0x0 0xa0000000
563 0x2000000 0x0 0xa0000000
564 0x0 0x20000000
565
566 0x1000000 0x0 0x0
567 0x1000000 0x0 0x0
568 0x0 0x100000>;
569 };
570 };
571};