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1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
23
24#include <linux/device.h>
25#include <linux/uio.h>
26#include <linux/dma-mapping.h>
27
28/**
29 * typedef dma_cookie_t - an opaque DMA cookie
30 *
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
32 */
33typedef s32 dma_cookie_t;
34
35#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
36
37/**
38 * enum dma_status - DMA transaction status
39 * @DMA_SUCCESS: transaction completed successfully
40 * @DMA_IN_PROGRESS: transaction not yet processed
41 * @DMA_ERROR: transaction failed
42 */
43enum dma_status {
44 DMA_SUCCESS,
45 DMA_IN_PROGRESS,
46 DMA_ERROR,
47};
48
49/**
50 * enum dma_transaction_type - DMA transaction types/indexes
51 */
52enum dma_transaction_type {
53 DMA_MEMCPY,
54 DMA_XOR,
55 DMA_PQ_XOR,
56 DMA_DUAL_XOR,
57 DMA_PQ_UPDATE,
58 DMA_ZERO_SUM,
59 DMA_PQ_ZERO_SUM,
60 DMA_MEMSET,
61 DMA_MEMCPY_CRC32C,
62 DMA_INTERRUPT,
63 DMA_PRIVATE,
64 DMA_SLAVE,
65};
66
67/* last transaction type for creation of the capabilities mask */
68#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
69
70
71/**
72 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
73 * control completion, and communicate status.
74 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
75 * this transaction
76 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
77 * acknowledges receipt, i.e. has has a chance to establish any
78 * dependency chains
79 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
80 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
81 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
82 * (if not set, do the source dma-unmapping as page)
83 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
84 * (if not set, do the destination dma-unmapping as page)
85 */
86enum dma_ctrl_flags {
87 DMA_PREP_INTERRUPT = (1 << 0),
88 DMA_CTRL_ACK = (1 << 1),
89 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
90 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
91 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
92 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
93};
94
95/**
96 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
97 * See linux/cpumask.h
98 */
99typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
100
101/**
102 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
103 * @memcpy_count: transaction counter
104 * @bytes_transferred: byte counter
105 */
106
107struct dma_chan_percpu {
108 /* stats */
109 unsigned long memcpy_count;
110 unsigned long bytes_transferred;
111};
112
113/**
114 * struct dma_chan - devices supply DMA channels, clients use them
115 * @device: ptr to the dma device who supplies this channel, always !%NULL
116 * @cookie: last cookie value returned to client
117 * @chan_id: channel ID for sysfs
118 * @dev: class device for sysfs
119 * @device_node: used to add this to the device chan list
120 * @local: per-cpu pointer to a struct dma_chan_percpu
121 * @client-count: how many clients are using this channel
122 * @table_count: number of appearances in the mem-to-mem allocation table
123 * @private: private data for certain client-channel associations
124 */
125struct dma_chan {
126 struct dma_device *device;
127 dma_cookie_t cookie;
128
129 /* sysfs */
130 int chan_id;
131 struct dma_chan_dev *dev;
132
133 struct list_head device_node;
134 struct dma_chan_percpu *local;
135 int client_count;
136 int table_count;
137 void *private;
138};
139
140/**
141 * struct dma_chan_dev - relate sysfs device node to backing channel device
142 * @chan - driver channel device
143 * @device - sysfs device
144 * @dev_id - parent dma_device dev_id
145 * @idr_ref - reference count to gate release of dma_device dev_id
146 */
147struct dma_chan_dev {
148 struct dma_chan *chan;
149 struct device device;
150 int dev_id;
151 atomic_t *idr_ref;
152};
153
154static inline const char *dma_chan_name(struct dma_chan *chan)
155{
156 return dev_name(&chan->dev->device);
157}
158
159void dma_chan_cleanup(struct kref *kref);
160
161/**
162 * typedef dma_filter_fn - callback filter for dma_request_channel
163 * @chan: channel to be reviewed
164 * @filter_param: opaque parameter passed through dma_request_channel
165 *
166 * When this optional parameter is specified in a call to dma_request_channel a
167 * suitable channel is passed to this routine for further dispositioning before
168 * being returned. Where 'suitable' indicates a non-busy channel that
169 * satisfies the given capability mask. It returns 'true' to indicate that the
170 * channel is suitable.
171 */
172typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
173
174typedef void (*dma_async_tx_callback)(void *dma_async_param);
175/**
176 * struct dma_async_tx_descriptor - async transaction descriptor
177 * ---dma generic offload fields---
178 * @cookie: tracking cookie for this transaction, set to -EBUSY if
179 * this tx is sitting on a dependency list
180 * @flags: flags to augment operation preparation, control completion, and
181 * communicate status
182 * @phys: physical address of the descriptor
183 * @tx_list: driver common field for operations that require multiple
184 * descriptors
185 * @chan: target channel for this operation
186 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
187 * @callback: routine to call after this operation is complete
188 * @callback_param: general parameter to pass to the callback routine
189 * ---async_tx api specific fields---
190 * @next: at completion submit this descriptor
191 * @parent: pointer to the next level up in the dependency chain
192 * @lock: protect the parent and next pointers
193 */
194struct dma_async_tx_descriptor {
195 dma_cookie_t cookie;
196 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
197 dma_addr_t phys;
198 struct list_head tx_list;
199 struct dma_chan *chan;
200 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
201 dma_async_tx_callback callback;
202 void *callback_param;
203 struct dma_async_tx_descriptor *next;
204 struct dma_async_tx_descriptor *parent;
205 spinlock_t lock;
206};
207
208/**
209 * struct dma_device - info on the entity supplying DMA services
210 * @chancnt: how many DMA channels are supported
211 * @privatecnt: how many DMA channels are requested by dma_request_channel
212 * @channels: the list of struct dma_chan
213 * @global_node: list_head for global dma_device_list
214 * @cap_mask: one or more dma_capability flags
215 * @max_xor: maximum number of xor sources, 0 if no capability
216 * @dev_id: unique device ID
217 * @dev: struct device reference for dma mapping api
218 * @device_alloc_chan_resources: allocate resources and return the
219 * number of allocated descriptors
220 * @device_free_chan_resources: release DMA channel's resources
221 * @device_prep_dma_memcpy: prepares a memcpy operation
222 * @device_prep_dma_xor: prepares a xor operation
223 * @device_prep_dma_zero_sum: prepares a zero_sum operation
224 * @device_prep_dma_memset: prepares a memset operation
225 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
226 * @device_prep_slave_sg: prepares a slave dma operation
227 * @device_terminate_all: terminate all pending operations
228 * @device_is_tx_complete: poll for transaction completion
229 * @device_issue_pending: push pending transactions to hardware
230 */
231struct dma_device {
232
233 unsigned int chancnt;
234 unsigned int privatecnt;
235 struct list_head channels;
236 struct list_head global_node;
237 dma_cap_mask_t cap_mask;
238 int max_xor;
239
240 int dev_id;
241 struct device *dev;
242
243 int (*device_alloc_chan_resources)(struct dma_chan *chan);
244 void (*device_free_chan_resources)(struct dma_chan *chan);
245
246 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
247 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
248 size_t len, unsigned long flags);
249 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
250 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
251 unsigned int src_cnt, size_t len, unsigned long flags);
252 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
253 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
254 size_t len, u32 *result, unsigned long flags);
255 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
256 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
257 unsigned long flags);
258 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
259 struct dma_chan *chan, unsigned long flags);
260
261 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
262 struct dma_chan *chan, struct scatterlist *sgl,
263 unsigned int sg_len, enum dma_data_direction direction,
264 unsigned long flags);
265 void (*device_terminate_all)(struct dma_chan *chan);
266
267 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
268 dma_cookie_t cookie, dma_cookie_t *last,
269 dma_cookie_t *used);
270 void (*device_issue_pending)(struct dma_chan *chan);
271};
272
273/* --- public DMA engine API --- */
274
275#ifdef CONFIG_DMA_ENGINE
276void dmaengine_get(void);
277void dmaengine_put(void);
278#else
279static inline void dmaengine_get(void)
280{
281}
282static inline void dmaengine_put(void)
283{
284}
285#endif
286
287#ifdef CONFIG_NET_DMA
288#define net_dmaengine_get() dmaengine_get()
289#define net_dmaengine_put() dmaengine_put()
290#else
291static inline void net_dmaengine_get(void)
292{
293}
294static inline void net_dmaengine_put(void)
295{
296}
297#endif
298
299#ifdef CONFIG_ASYNC_TX_DMA
300#define async_dmaengine_get() dmaengine_get()
301#define async_dmaengine_put() dmaengine_put()
302#define async_dma_find_channel(type) dma_find_channel(type)
303#else
304static inline void async_dmaengine_get(void)
305{
306}
307static inline void async_dmaengine_put(void)
308{
309}
310static inline struct dma_chan *
311async_dma_find_channel(enum dma_transaction_type type)
312{
313 return NULL;
314}
315#endif
316
317dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
318 void *dest, void *src, size_t len);
319dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
320 struct page *page, unsigned int offset, void *kdata, size_t len);
321dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
322 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
323 unsigned int src_off, size_t len);
324void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
325 struct dma_chan *chan);
326
327static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
328{
329 tx->flags |= DMA_CTRL_ACK;
330}
331
332static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
333{
334 tx->flags &= ~DMA_CTRL_ACK;
335}
336
337static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
338{
339 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
340}
341
342#define first_dma_cap(mask) __first_dma_cap(&(mask))
343static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
344{
345 return min_t(int, DMA_TX_TYPE_END,
346 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
347}
348
349#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
350static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
351{
352 return min_t(int, DMA_TX_TYPE_END,
353 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
354}
355
356#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
357static inline void
358__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
359{
360 set_bit(tx_type, dstp->bits);
361}
362
363#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
364static inline void
365__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
366{
367 clear_bit(tx_type, dstp->bits);
368}
369
370#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
371static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
372{
373 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
374}
375
376#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
377static inline int
378__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
379{
380 return test_bit(tx_type, srcp->bits);
381}
382
383#define for_each_dma_cap_mask(cap, mask) \
384 for ((cap) = first_dma_cap(mask); \
385 (cap) < DMA_TX_TYPE_END; \
386 (cap) = next_dma_cap((cap), (mask)))
387
388/**
389 * dma_async_issue_pending - flush pending transactions to HW
390 * @chan: target DMA channel
391 *
392 * This allows drivers to push copies to HW in batches,
393 * reducing MMIO writes where possible.
394 */
395static inline void dma_async_issue_pending(struct dma_chan *chan)
396{
397 chan->device->device_issue_pending(chan);
398}
399
400#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
401
402/**
403 * dma_async_is_tx_complete - poll for transaction completion
404 * @chan: DMA channel
405 * @cookie: transaction identifier to check status of
406 * @last: returns last completed cookie, can be NULL
407 * @used: returns last issued cookie, can be NULL
408 *
409 * If @last and @used are passed in, upon return they reflect the driver
410 * internal state and can be used with dma_async_is_complete() to check
411 * the status of multiple cookies without re-checking hardware state.
412 */
413static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
414 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
415{
416 return chan->device->device_is_tx_complete(chan, cookie, last, used);
417}
418
419#define dma_async_memcpy_complete(chan, cookie, last, used)\
420 dma_async_is_tx_complete(chan, cookie, last, used)
421
422/**
423 * dma_async_is_complete - test a cookie against chan state
424 * @cookie: transaction identifier to test status of
425 * @last_complete: last know completed transaction
426 * @last_used: last cookie value handed out
427 *
428 * dma_async_is_complete() is used in dma_async_memcpy_complete()
429 * the test logic is separated for lightweight testing of multiple cookies
430 */
431static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
432 dma_cookie_t last_complete, dma_cookie_t last_used)
433{
434 if (last_complete <= last_used) {
435 if ((cookie <= last_complete) || (cookie > last_used))
436 return DMA_SUCCESS;
437 } else {
438 if ((cookie <= last_complete) && (cookie > last_used))
439 return DMA_SUCCESS;
440 }
441 return DMA_IN_PROGRESS;
442}
443
444enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
445#ifdef CONFIG_DMA_ENGINE
446enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
447void dma_issue_pending_all(void);
448#else
449static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
450{
451 return DMA_SUCCESS;
452}
453static inline void dma_issue_pending_all(void)
454{
455 do { } while (0);
456}
457#endif
458
459/* --- DMA device --- */
460
461int dma_async_device_register(struct dma_device *device);
462void dma_async_device_unregister(struct dma_device *device);
463void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
464struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
465#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
466struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
467void dma_release_channel(struct dma_chan *chan);
468
469/* --- Helper iov-locking functions --- */
470
471struct dma_page_list {
472 char __user *base_address;
473 int nr_pages;
474 struct page **pages;
475};
476
477struct dma_pinned_list {
478 int nr_iovecs;
479 struct dma_page_list page_list[0];
480};
481
482struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
483void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
484
485dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
486 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
487dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
488 struct dma_pinned_list *pinned_list, struct page *page,
489 unsigned int offset, size_t len);
490
491#endif /* DMAENGINE_H */