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1/* 2 * linux/arch/powerpc/platforms/cell/qpace_setup.c 3 * 4 * Copyright (C) 1995 Linus Torvalds 5 * Adapted from 'alpha' version by Gary Thomas 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * Modified by PPC64 Team, IBM Corp 8 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH 9 * Modified by Benjamin Krill <ben@codiert.org>, IBM Corp. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17#include <linux/sched.h> 18#include <linux/kernel.h> 19#include <linux/init.h> 20#include <linux/delay.h> 21#include <linux/irq.h> 22#include <linux/console.h> 23#include <linux/of_platform.h> 24 25#include <asm/mmu.h> 26#include <asm/processor.h> 27#include <asm/io.h> 28#include <asm/kexec.h> 29#include <asm/pgtable.h> 30#include <asm/prom.h> 31#include <asm/rtas.h> 32#include <asm/dma.h> 33#include <asm/machdep.h> 34#include <asm/time.h> 35#include <asm/cputable.h> 36#include <asm/irq.h> 37#include <asm/spu.h> 38#include <asm/spu_priv1.h> 39#include <asm/udbg.h> 40#include <asm/cell-regs.h> 41 42#include "interrupt.h" 43#include "pervasive.h" 44#include "ras.h" 45#include "io-workarounds.h" 46 47static void qpace_show_cpuinfo(struct seq_file *m) 48{ 49 struct device_node *root; 50 const char *model = ""; 51 52 root = of_find_node_by_path("/"); 53 if (root) 54 model = of_get_property(root, "model", NULL); 55 seq_printf(m, "machine\t\t: CHRP %s\n", model); 56 of_node_put(root); 57} 58 59static void qpace_progress(char *s, unsigned short hex) 60{ 61 printk("*** %04x : %s\n", hex, s ? s : ""); 62} 63 64static int __init qpace_publish_devices(void) 65{ 66 int node; 67 68 /* Publish OF platform devices for southbridge IOs */ 69 of_platform_bus_probe(NULL, NULL, NULL); 70 71 /* There is no device for the MIC memory controller, thus we create 72 * a platform device for it to attach the EDAC driver to. 73 */ 74 for_each_online_node(node) { 75 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL) 76 continue; 77 platform_device_register_simple("cbe-mic", node, NULL, 0); 78 } 79 80 return 0; 81} 82machine_subsys_initcall(qpace, qpace_publish_devices); 83 84static void __init qpace_setup_arch(void) 85{ 86#ifdef CONFIG_SPU_BASE 87 spu_priv1_ops = &spu_priv1_mmio_ops; 88 spu_management_ops = &spu_management_of_ops; 89#endif 90 91 cbe_regs_init(); 92 93#ifdef CONFIG_CBE_RAS 94 cbe_ras_init(); 95#endif 96 97#ifdef CONFIG_SMP 98 smp_init_cell(); 99#endif 100 101 /* init to some ~sane value until calibrate_delay() runs */ 102 loops_per_jiffy = 50000000; 103 104 cbe_pervasive_init(); 105#ifdef CONFIG_DUMMY_CONSOLE 106 conswitchp = &dummy_con; 107#endif 108} 109 110static int __init qpace_probe(void) 111{ 112 unsigned long root = of_get_flat_dt_root(); 113 114 if (!of_flat_dt_is_compatible(root, "IBM,QPACE")) 115 return 0; 116 117 hpte_init_native(); 118 119 return 1; 120} 121 122define_machine(qpace) { 123 .name = "QPACE", 124 .probe = qpace_probe, 125 .setup_arch = qpace_setup_arch, 126 .show_cpuinfo = qpace_show_cpuinfo, 127 .restart = rtas_restart, 128 .power_off = rtas_power_off, 129 .halt = rtas_halt, 130 .get_boot_time = rtas_get_boot_time, 131 .get_rtc_time = rtas_get_rtc_time, 132 .set_rtc_time = rtas_set_rtc_time, 133 .calibrate_decr = generic_calibrate_decr, 134 .progress = qpace_progress, 135 .init_IRQ = iic_init_IRQ, 136#ifdef CONFIG_KEXEC 137 .machine_kexec = default_machine_kexec, 138 .machine_kexec_prepare = default_machine_kexec_prepare, 139 .machine_crash_shutdown = default_machine_crash_shutdown, 140#endif 141};