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1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <linux/spinlock.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <asm/cpm.h>
23#include <asm/immap_qe.h>
24
25#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
26#define QE_NUM_OF_BRGS 16
27#define QE_NUM_OF_PORTS 1024
28
29/* Memory partitions
30*/
31#define MEM_PART_SYSTEM 0
32#define MEM_PART_SECONDARY 1
33#define MEM_PART_MURAM 2
34
35/* Clocks and BRGs */
36enum qe_clock {
37 QE_CLK_NONE = 0,
38 QE_BRG1, /* Baud Rate Generator 1 */
39 QE_BRG2, /* Baud Rate Generator 2 */
40 QE_BRG3, /* Baud Rate Generator 3 */
41 QE_BRG4, /* Baud Rate Generator 4 */
42 QE_BRG5, /* Baud Rate Generator 5 */
43 QE_BRG6, /* Baud Rate Generator 6 */
44 QE_BRG7, /* Baud Rate Generator 7 */
45 QE_BRG8, /* Baud Rate Generator 8 */
46 QE_BRG9, /* Baud Rate Generator 9 */
47 QE_BRG10, /* Baud Rate Generator 10 */
48 QE_BRG11, /* Baud Rate Generator 11 */
49 QE_BRG12, /* Baud Rate Generator 12 */
50 QE_BRG13, /* Baud Rate Generator 13 */
51 QE_BRG14, /* Baud Rate Generator 14 */
52 QE_BRG15, /* Baud Rate Generator 15 */
53 QE_BRG16, /* Baud Rate Generator 16 */
54 QE_CLK1, /* Clock 1 */
55 QE_CLK2, /* Clock 2 */
56 QE_CLK3, /* Clock 3 */
57 QE_CLK4, /* Clock 4 */
58 QE_CLK5, /* Clock 5 */
59 QE_CLK6, /* Clock 6 */
60 QE_CLK7, /* Clock 7 */
61 QE_CLK8, /* Clock 8 */
62 QE_CLK9, /* Clock 9 */
63 QE_CLK10, /* Clock 10 */
64 QE_CLK11, /* Clock 11 */
65 QE_CLK12, /* Clock 12 */
66 QE_CLK13, /* Clock 13 */
67 QE_CLK14, /* Clock 14 */
68 QE_CLK15, /* Clock 15 */
69 QE_CLK16, /* Clock 16 */
70 QE_CLK17, /* Clock 17 */
71 QE_CLK18, /* Clock 18 */
72 QE_CLK19, /* Clock 19 */
73 QE_CLK20, /* Clock 20 */
74 QE_CLK21, /* Clock 21 */
75 QE_CLK22, /* Clock 22 */
76 QE_CLK23, /* Clock 23 */
77 QE_CLK24, /* Clock 24 */
78 QE_CLK_DUMMY
79};
80
81static inline bool qe_clock_is_brg(enum qe_clock clk)
82{
83 return clk >= QE_BRG1 && clk <= QE_BRG16;
84}
85
86extern spinlock_t cmxgcr_lock;
87
88/* Export QE common operations */
89#ifdef CONFIG_QUICC_ENGINE
90extern void __init qe_reset(void);
91#else
92static inline void qe_reset(void) {}
93#endif
94
95/* QE PIO */
96#define QE_PIO_PINS 32
97
98struct qe_pio_regs {
99 __be32 cpodr; /* Open drain register */
100 __be32 cpdata; /* Data register */
101 __be32 cpdir1; /* Direction register */
102 __be32 cpdir2; /* Direction register */
103 __be32 cppar1; /* Pin assignment register */
104 __be32 cppar2; /* Pin assignment register */
105#ifdef CONFIG_PPC_85xx
106 u8 pad[8];
107#endif
108};
109
110#define QE_PIO_DIR_IN 2
111#define QE_PIO_DIR_OUT 1
112extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
113 int dir, int open_drain, int assignment,
114 int has_irq);
115#ifdef CONFIG_QUICC_ENGINE
116extern int par_io_init(struct device_node *np);
117extern int par_io_of_config(struct device_node *np);
118extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
119 int assignment, int has_irq);
120extern int par_io_data_set(u8 port, u8 pin, u8 val);
121#else
122static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
123static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
124static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
125 int assignment, int has_irq) { return -ENOSYS; }
126static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
127#endif /* CONFIG_QUICC_ENGINE */
128
129/*
130 * Pin multiplexing functions.
131 */
132struct qe_pin;
133#ifdef CONFIG_QE_GPIO
134extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
135extern void qe_pin_free(struct qe_pin *qe_pin);
136extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
137extern void qe_pin_set_dedicated(struct qe_pin *pin);
138#else
139static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
140{
141 return ERR_PTR(-ENOSYS);
142}
143static inline void qe_pin_free(struct qe_pin *qe_pin) {}
144static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
145static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
146#endif /* CONFIG_QE_GPIO */
147
148/* QE internal API */
149int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
150enum qe_clock qe_clock_source(const char *source);
151unsigned int qe_get_brg_clk(void);
152int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
153int qe_get_snum(void);
154void qe_put_snum(u8 snum);
155unsigned int qe_get_num_of_risc(void);
156unsigned int qe_get_num_of_snums(void);
157
158/* we actually use cpm_muram implementation, define this for convenience */
159#define qe_muram_init cpm_muram_init
160#define qe_muram_alloc cpm_muram_alloc
161#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
162#define qe_muram_free cpm_muram_free
163#define qe_muram_addr cpm_muram_addr
164#define qe_muram_offset cpm_muram_offset
165
166/* Structure that defines QE firmware binary files.
167 *
168 * See Documentation/powerpc/qe-firmware.txt for a description of these
169 * fields.
170 */
171struct qe_firmware {
172 struct qe_header {
173 __be32 length; /* Length of the entire structure, in bytes */
174 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
175 u8 version; /* Version of this layout. First ver is '1' */
176 } header;
177 u8 id[62]; /* Null-terminated identifier string */
178 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
179 u8 count; /* Number of microcode[] structures */
180 struct {
181 __be16 model; /* The SOC model */
182 u8 major; /* The SOC revision major */
183 u8 minor; /* The SOC revision minor */
184 } __attribute__ ((packed)) soc;
185 u8 padding[4]; /* Reserved, for alignment */
186 __be64 extended_modes; /* Extended modes */
187 __be32 vtraps[8]; /* Virtual trap addresses */
188 u8 reserved[4]; /* Reserved, for future expansion */
189 struct qe_microcode {
190 u8 id[32]; /* Null-terminated identifier */
191 __be32 traps[16]; /* Trap addresses, 0 == ignore */
192 __be32 eccr; /* The value for the ECCR register */
193 __be32 iram_offset; /* Offset into I-RAM for the code */
194 __be32 count; /* Number of 32-bit words of the code */
195 __be32 code_offset; /* Offset of the actual microcode */
196 u8 major; /* The microcode version major */
197 u8 minor; /* The microcode version minor */
198 u8 revision; /* The microcode version revision */
199 u8 padding; /* Reserved, for alignment */
200 u8 reserved[4]; /* Reserved, for future expansion */
201 } __attribute__ ((packed)) microcode[1];
202 /* All microcode binaries should be located here */
203 /* CRC32 should be located here, after the microcode binaries */
204} __attribute__ ((packed));
205
206struct qe_firmware_info {
207 char id[64]; /* Firmware name */
208 u32 vtraps[8]; /* Virtual trap addresses */
209 u64 extended_modes; /* Extended modes */
210};
211
212/* Upload a firmware to the QE */
213int qe_upload_firmware(const struct qe_firmware *firmware);
214
215/* Obtain information on the uploaded firmware */
216struct qe_firmware_info *qe_get_firmware_info(void);
217
218/* QE USB */
219int qe_usb_clock_set(enum qe_clock clk, int rate);
220
221/* Buffer descriptors */
222struct qe_bd {
223 __be16 status;
224 __be16 length;
225 __be32 buf;
226} __attribute__ ((packed));
227
228#define BD_STATUS_MASK 0xffff0000
229#define BD_LENGTH_MASK 0x0000ffff
230
231/* Alignment */
232#define QE_INTR_TABLE_ALIGN 16 /* ??? */
233#define QE_ALIGNMENT_OF_BD 8
234#define QE_ALIGNMENT_OF_PRAM 64
235
236/* RISC allocation */
237#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
238#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
239#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
240#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
241#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
242 QE_RISC_ALLOCATION_RISC2)
243#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
244 QE_RISC_ALLOCATION_RISC2 | \
245 QE_RISC_ALLOCATION_RISC3 | \
246 QE_RISC_ALLOCATION_RISC4)
247
248/* QE extended filtering Table Lookup Key Size */
249enum qe_fltr_tbl_lookup_key_size {
250 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
251 = 0x3f, /* LookupKey parsed by the Generate LookupKey
252 CMD is truncated to 8 bytes */
253 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
254 = 0x5f, /* LookupKey parsed by the Generate LookupKey
255 CMD is truncated to 16 bytes */
256};
257
258/* QE FLTR extended filtering Largest External Table Lookup Key Size */
259enum qe_fltr_largest_external_tbl_lookup_key_size {
260 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
261 = 0x0,/* not used */
262 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
263 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
264 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
265 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
266};
267
268/* structure representing QE parameter RAM */
269struct qe_timer_tables {
270 u16 tm_base; /* QE timer table base adr */
271 u16 tm_ptr; /* QE timer table pointer */
272 u16 r_tmr; /* QE timer mode register */
273 u16 r_tmv; /* QE timer valid register */
274 u32 tm_cmd; /* QE timer cmd register */
275 u32 tm_cnt; /* QE timer internal cnt */
276} __attribute__ ((packed));
277
278#define QE_FLTR_TAD_SIZE 8
279
280/* QE extended filtering Termination Action Descriptor (TAD) */
281struct qe_fltr_tad {
282 u8 serialized[QE_FLTR_TAD_SIZE];
283} __attribute__ ((packed));
284
285/* Communication Direction */
286enum comm_dir {
287 COMM_DIR_NONE = 0,
288 COMM_DIR_RX = 1,
289 COMM_DIR_TX = 2,
290 COMM_DIR_RX_AND_TX = 3
291};
292
293/* QE CMXUCR Registers.
294 * There are two UCCs represented in each of the four CMXUCR registers.
295 * These values are for the UCC in the LSBs
296 */
297#define QE_CMXUCR_MII_ENET_MNG 0x00007000
298#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
299#define QE_CMXUCR_GRANT 0x00008000
300#define QE_CMXUCR_TSA 0x00004000
301#define QE_CMXUCR_BKPT 0x00000100
302#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
303
304/* QE CMXGCR Registers.
305*/
306#define QE_CMXGCR_MII_ENET_MNG 0x00007000
307#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
308#define QE_CMXGCR_USBCS 0x0000000f
309#define QE_CMXGCR_USBCS_CLK3 0x1
310#define QE_CMXGCR_USBCS_CLK5 0x2
311#define QE_CMXGCR_USBCS_CLK7 0x3
312#define QE_CMXGCR_USBCS_CLK9 0x4
313#define QE_CMXGCR_USBCS_CLK13 0x5
314#define QE_CMXGCR_USBCS_CLK17 0x6
315#define QE_CMXGCR_USBCS_CLK19 0x7
316#define QE_CMXGCR_USBCS_CLK21 0x8
317#define QE_CMXGCR_USBCS_BRG9 0x9
318#define QE_CMXGCR_USBCS_BRG10 0xa
319
320/* QE CECR Commands.
321*/
322#define QE_CR_FLG 0x00010000
323#define QE_RESET 0x80000000
324#define QE_INIT_TX_RX 0x00000000
325#define QE_INIT_RX 0x00000001
326#define QE_INIT_TX 0x00000002
327#define QE_ENTER_HUNT_MODE 0x00000003
328#define QE_STOP_TX 0x00000004
329#define QE_GRACEFUL_STOP_TX 0x00000005
330#define QE_RESTART_TX 0x00000006
331#define QE_CLOSE_RX_BD 0x00000007
332#define QE_SWITCH_COMMAND 0x00000007
333#define QE_SET_GROUP_ADDRESS 0x00000008
334#define QE_START_IDMA 0x00000009
335#define QE_MCC_STOP_RX 0x00000009
336#define QE_ATM_TRANSMIT 0x0000000a
337#define QE_HPAC_CLEAR_ALL 0x0000000b
338#define QE_GRACEFUL_STOP_RX 0x0000001a
339#define QE_RESTART_RX 0x0000001b
340#define QE_HPAC_SET_PRIORITY 0x0000010b
341#define QE_HPAC_STOP_TX 0x0000020b
342#define QE_HPAC_STOP_RX 0x0000030b
343#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
344#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
345#define QE_HPAC_START_TX 0x0000060b
346#define QE_HPAC_START_RX 0x0000070b
347#define QE_USB_STOP_TX 0x0000000a
348#define QE_USB_RESTART_TX 0x0000000c
349#define QE_QMC_STOP_TX 0x0000000c
350#define QE_QMC_STOP_RX 0x0000000d
351#define QE_SS7_SU_FIL_RESET 0x0000000e
352/* jonathbr added from here down for 83xx */
353#define QE_RESET_BCS 0x0000000a
354#define QE_MCC_INIT_TX_RX_16 0x00000003
355#define QE_MCC_STOP_TX 0x00000004
356#define QE_MCC_INIT_TX_1 0x00000005
357#define QE_MCC_INIT_RX_1 0x00000006
358#define QE_MCC_RESET 0x00000007
359#define QE_SET_TIMER 0x00000008
360#define QE_RANDOM_NUMBER 0x0000000c
361#define QE_ATM_MULTI_THREAD_INIT 0x00000011
362#define QE_ASSIGN_PAGE 0x00000012
363#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
364#define QE_START_FLOW_CONTROL 0x00000014
365#define QE_STOP_FLOW_CONTROL 0x00000015
366#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
367
368#define QE_ASSIGN_RISC 0x00000010
369#define QE_CR_MCN_NORMAL_SHIFT 6
370#define QE_CR_MCN_USB_SHIFT 4
371#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
372#define QE_CR_SNUM_SHIFT 17
373
374/* QE CECR Sub Block - sub block of QE command.
375*/
376#define QE_CR_SUBBLOCK_INVALID 0x00000000
377#define QE_CR_SUBBLOCK_USB 0x03200000
378#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
379#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
380#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
381#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
382#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
383#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
384#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
385#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
386#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
387#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
388#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
389#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
390#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
391#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
392#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
393#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
394#define QE_CR_SUBBLOCK_MCC1 0x03800000
395#define QE_CR_SUBBLOCK_MCC2 0x03a00000
396#define QE_CR_SUBBLOCK_MCC3 0x03000000
397#define QE_CR_SUBBLOCK_IDMA1 0x02800000
398#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
399#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
400#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
401#define QE_CR_SUBBLOCK_HPAC 0x01e00000
402#define QE_CR_SUBBLOCK_SPI1 0x01400000
403#define QE_CR_SUBBLOCK_SPI2 0x01600000
404#define QE_CR_SUBBLOCK_RAND 0x01c00000
405#define QE_CR_SUBBLOCK_TIMER 0x01e00000
406#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
407
408/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
409#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
410#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
411#define QE_CR_PROTOCOL_QMC 0x02
412#define QE_CR_PROTOCOL_UART 0x04
413#define QE_CR_PROTOCOL_ATM_POS 0x0A
414#define QE_CR_PROTOCOL_ETHERNET 0x0C
415#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
416
417/* BRG configuration register */
418#define QE_BRGC_ENABLE 0x00010000
419#define QE_BRGC_DIVISOR_SHIFT 1
420#define QE_BRGC_DIVISOR_MAX 0xFFF
421#define QE_BRGC_DIV16 1
422
423/* QE Timers registers */
424#define QE_GTCFR1_PCAS 0x80
425#define QE_GTCFR1_STP2 0x20
426#define QE_GTCFR1_RST2 0x10
427#define QE_GTCFR1_GM2 0x08
428#define QE_GTCFR1_GM1 0x04
429#define QE_GTCFR1_STP1 0x02
430#define QE_GTCFR1_RST1 0x01
431
432/* SDMA registers */
433#define QE_SDSR_BER1 0x02000000
434#define QE_SDSR_BER2 0x01000000
435
436#define QE_SDMR_GLB_1_MSK 0x80000000
437#define QE_SDMR_ADR_SEL 0x20000000
438#define QE_SDMR_BER1_MSK 0x02000000
439#define QE_SDMR_BER2_MSK 0x01000000
440#define QE_SDMR_EB1_MSK 0x00800000
441#define QE_SDMR_ER1_MSK 0x00080000
442#define QE_SDMR_ER2_MSK 0x00040000
443#define QE_SDMR_CEN_MASK 0x0000E000
444#define QE_SDMR_SBER_1 0x00000200
445#define QE_SDMR_SBER_2 0x00000200
446#define QE_SDMR_EB1_PR_MASK 0x000000C0
447#define QE_SDMR_ER1_PR 0x00000008
448
449#define QE_SDMR_CEN_SHIFT 13
450#define QE_SDMR_EB1_PR_SHIFT 6
451
452#define QE_SDTM_MSNUM_SHIFT 24
453
454#define QE_SDEBCR_BA_MASK 0x01FFFFFF
455
456/* Communication Processor */
457#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
458#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
459#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
460
461/* I-RAM */
462#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
463#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
464
465/* UPC */
466#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
467#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
468#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
469#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
470#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
471
472/* UCC GUEMR register */
473#define UCC_GUEMR_MODE_MASK_RX 0x02
474#define UCC_GUEMR_MODE_FAST_RX 0x02
475#define UCC_GUEMR_MODE_SLOW_RX 0x00
476#define UCC_GUEMR_MODE_MASK_TX 0x01
477#define UCC_GUEMR_MODE_FAST_TX 0x01
478#define UCC_GUEMR_MODE_SLOW_TX 0x00
479#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
480#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
481 must be set 1 */
482
483/* structure representing UCC SLOW parameter RAM */
484struct ucc_slow_pram {
485 __be16 rbase; /* RX BD base address */
486 __be16 tbase; /* TX BD base address */
487 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
488 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
489 __be16 mrblr; /* Rx buffer length */
490 __be32 rstate; /* Rx internal state */
491 __be32 rptr; /* Rx internal data pointer */
492 __be16 rbptr; /* rb BD Pointer */
493 __be16 rcount; /* Rx internal byte count */
494 __be32 rtemp; /* Rx temp */
495 __be32 tstate; /* Tx internal state */
496 __be32 tptr; /* Tx internal data pointer */
497 __be16 tbptr; /* Tx BD pointer */
498 __be16 tcount; /* Tx byte count */
499 __be32 ttemp; /* Tx temp */
500 __be32 rcrc; /* temp receive CRC */
501 __be32 tcrc; /* temp transmit CRC */
502} __attribute__ ((packed));
503
504/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
505#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
506#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
507#define UCC_SLOW_GUMR_H_REVD 0x00002000
508#define UCC_SLOW_GUMR_H_TRX 0x00001000
509#define UCC_SLOW_GUMR_H_TTX 0x00000800
510#define UCC_SLOW_GUMR_H_CDP 0x00000400
511#define UCC_SLOW_GUMR_H_CTSP 0x00000200
512#define UCC_SLOW_GUMR_H_CDS 0x00000100
513#define UCC_SLOW_GUMR_H_CTSS 0x00000080
514#define UCC_SLOW_GUMR_H_TFL 0x00000040
515#define UCC_SLOW_GUMR_H_RFW 0x00000020
516#define UCC_SLOW_GUMR_H_TXSY 0x00000010
517#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
518#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
519#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
520#define UCC_SLOW_GUMR_H_RTSM 0x00000002
521#define UCC_SLOW_GUMR_H_RSYN 0x00000001
522
523#define UCC_SLOW_GUMR_L_TCI 0x10000000
524#define UCC_SLOW_GUMR_L_RINV 0x02000000
525#define UCC_SLOW_GUMR_L_TINV 0x01000000
526#define UCC_SLOW_GUMR_L_TEND 0x00040000
527#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
528#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
529#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
530#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
531#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
532#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
533#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
534#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
535#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
536#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
537#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
538#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
539#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
540#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
541#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
542#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
543#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
544#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
545#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
546#define UCC_SLOW_GUMR_L_ENR 0x00000020
547#define UCC_SLOW_GUMR_L_ENT 0x00000010
548#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
549#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
550#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
551#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
552#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
553
554/* General UCC FAST Mode Register */
555#define UCC_FAST_GUMR_TCI 0x20000000
556#define UCC_FAST_GUMR_TRX 0x10000000
557#define UCC_FAST_GUMR_TTX 0x08000000
558#define UCC_FAST_GUMR_CDP 0x04000000
559#define UCC_FAST_GUMR_CTSP 0x02000000
560#define UCC_FAST_GUMR_CDS 0x01000000
561#define UCC_FAST_GUMR_CTSS 0x00800000
562#define UCC_FAST_GUMR_TXSY 0x00020000
563#define UCC_FAST_GUMR_RSYN 0x00010000
564#define UCC_FAST_GUMR_RTSM 0x00002000
565#define UCC_FAST_GUMR_REVD 0x00000400
566#define UCC_FAST_GUMR_ENR 0x00000020
567#define UCC_FAST_GUMR_ENT 0x00000010
568
569/* UART Slow UCC Event Register (UCCE) */
570#define UCC_UART_UCCE_AB 0x0200
571#define UCC_UART_UCCE_IDLE 0x0100
572#define UCC_UART_UCCE_GRA 0x0080
573#define UCC_UART_UCCE_BRKE 0x0040
574#define UCC_UART_UCCE_BRKS 0x0020
575#define UCC_UART_UCCE_CCR 0x0008
576#define UCC_UART_UCCE_BSY 0x0004
577#define UCC_UART_UCCE_TX 0x0002
578#define UCC_UART_UCCE_RX 0x0001
579
580/* HDLC Slow UCC Event Register (UCCE) */
581#define UCC_HDLC_UCCE_GLR 0x1000
582#define UCC_HDLC_UCCE_GLT 0x0800
583#define UCC_HDLC_UCCE_IDLE 0x0100
584#define UCC_HDLC_UCCE_BRKE 0x0040
585#define UCC_HDLC_UCCE_BRKS 0x0020
586#define UCC_HDLC_UCCE_TXE 0x0010
587#define UCC_HDLC_UCCE_RXF 0x0008
588#define UCC_HDLC_UCCE_BSY 0x0004
589#define UCC_HDLC_UCCE_TXB 0x0002
590#define UCC_HDLC_UCCE_RXB 0x0001
591
592/* BISYNC Slow UCC Event Register (UCCE) */
593#define UCC_BISYNC_UCCE_GRA 0x0080
594#define UCC_BISYNC_UCCE_TXE 0x0010
595#define UCC_BISYNC_UCCE_RCH 0x0008
596#define UCC_BISYNC_UCCE_BSY 0x0004
597#define UCC_BISYNC_UCCE_TXB 0x0002
598#define UCC_BISYNC_UCCE_RXB 0x0001
599
600/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
601#define UCC_GETH_UCCE_MPD 0x80000000
602#define UCC_GETH_UCCE_SCAR 0x40000000
603#define UCC_GETH_UCCE_GRA 0x20000000
604#define UCC_GETH_UCCE_CBPR 0x10000000
605#define UCC_GETH_UCCE_BSY 0x08000000
606#define UCC_GETH_UCCE_RXC 0x04000000
607#define UCC_GETH_UCCE_TXC 0x02000000
608#define UCC_GETH_UCCE_TXE 0x01000000
609#define UCC_GETH_UCCE_TXB7 0x00800000
610#define UCC_GETH_UCCE_TXB6 0x00400000
611#define UCC_GETH_UCCE_TXB5 0x00200000
612#define UCC_GETH_UCCE_TXB4 0x00100000
613#define UCC_GETH_UCCE_TXB3 0x00080000
614#define UCC_GETH_UCCE_TXB2 0x00040000
615#define UCC_GETH_UCCE_TXB1 0x00020000
616#define UCC_GETH_UCCE_TXB0 0x00010000
617#define UCC_GETH_UCCE_RXB7 0x00008000
618#define UCC_GETH_UCCE_RXB6 0x00004000
619#define UCC_GETH_UCCE_RXB5 0x00002000
620#define UCC_GETH_UCCE_RXB4 0x00001000
621#define UCC_GETH_UCCE_RXB3 0x00000800
622#define UCC_GETH_UCCE_RXB2 0x00000400
623#define UCC_GETH_UCCE_RXB1 0x00000200
624#define UCC_GETH_UCCE_RXB0 0x00000100
625#define UCC_GETH_UCCE_RXF7 0x00000080
626#define UCC_GETH_UCCE_RXF6 0x00000040
627#define UCC_GETH_UCCE_RXF5 0x00000020
628#define UCC_GETH_UCCE_RXF4 0x00000010
629#define UCC_GETH_UCCE_RXF3 0x00000008
630#define UCC_GETH_UCCE_RXF2 0x00000004
631#define UCC_GETH_UCCE_RXF1 0x00000002
632#define UCC_GETH_UCCE_RXF0 0x00000001
633
634/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
635#define UCC_UART_UPSMR_FLC 0x8000
636#define UCC_UART_UPSMR_SL 0x4000
637#define UCC_UART_UPSMR_CL_MASK 0x3000
638#define UCC_UART_UPSMR_CL_8 0x3000
639#define UCC_UART_UPSMR_CL_7 0x2000
640#define UCC_UART_UPSMR_CL_6 0x1000
641#define UCC_UART_UPSMR_CL_5 0x0000
642#define UCC_UART_UPSMR_UM_MASK 0x0c00
643#define UCC_UART_UPSMR_UM_NORMAL 0x0000
644#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
645#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
646#define UCC_UART_UPSMR_FRZ 0x0200
647#define UCC_UART_UPSMR_RZS 0x0100
648#define UCC_UART_UPSMR_SYN 0x0080
649#define UCC_UART_UPSMR_DRT 0x0040
650#define UCC_UART_UPSMR_PEN 0x0010
651#define UCC_UART_UPSMR_RPM_MASK 0x000c
652#define UCC_UART_UPSMR_RPM_ODD 0x0000
653#define UCC_UART_UPSMR_RPM_LOW 0x0004
654#define UCC_UART_UPSMR_RPM_EVEN 0x0008
655#define UCC_UART_UPSMR_RPM_HIGH 0x000C
656#define UCC_UART_UPSMR_TPM_MASK 0x0003
657#define UCC_UART_UPSMR_TPM_ODD 0x0000
658#define UCC_UART_UPSMR_TPM_LOW 0x0001
659#define UCC_UART_UPSMR_TPM_EVEN 0x0002
660#define UCC_UART_UPSMR_TPM_HIGH 0x0003
661
662/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
663#define UCC_GETH_UPSMR_FTFE 0x80000000
664#define UCC_GETH_UPSMR_PTPE 0x40000000
665#define UCC_GETH_UPSMR_ECM 0x04000000
666#define UCC_GETH_UPSMR_HSE 0x02000000
667#define UCC_GETH_UPSMR_PRO 0x00400000
668#define UCC_GETH_UPSMR_CAP 0x00200000
669#define UCC_GETH_UPSMR_RSH 0x00100000
670#define UCC_GETH_UPSMR_RPM 0x00080000
671#define UCC_GETH_UPSMR_R10M 0x00040000
672#define UCC_GETH_UPSMR_RLPB 0x00020000
673#define UCC_GETH_UPSMR_TBIM 0x00010000
674#define UCC_GETH_UPSMR_RES1 0x00002000
675#define UCC_GETH_UPSMR_RMM 0x00001000
676#define UCC_GETH_UPSMR_CAM 0x00000400
677#define UCC_GETH_UPSMR_BRO 0x00000200
678#define UCC_GETH_UPSMR_SMM 0x00000080
679#define UCC_GETH_UPSMR_SGMM 0x00000020
680
681/* UCC Transmit On Demand Register (UTODR) */
682#define UCC_SLOW_TOD 0x8000
683#define UCC_FAST_TOD 0x8000
684
685/* UCC Bus Mode Register masks */
686/* Not to be confused with the Bundle Mode Register */
687#define UCC_BMR_GBL 0x20
688#define UCC_BMR_BO_BE 0x10
689#define UCC_BMR_CETM 0x04
690#define UCC_BMR_DTB 0x02
691#define UCC_BMR_BDB 0x01
692
693/* Function code masks */
694#define FC_GBL 0x20
695#define FC_DTB_LCL 0x02
696#define UCC_FAST_FUNCTION_CODE_GBL 0x20
697#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
698#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
699
700#endif /* __KERNEL__ */
701#endif /* _ASM_POWERPC_QE_H */