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Linux kernel mirror (for testing)
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1/*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33#include "ixgb_hw.h"
34#include "ixgb_ids.h"
35
36/* Local function prototypes */
37
38static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
39
40static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
41
42static void ixgb_get_bus_info(struct ixgb_hw *hw);
43
44static bool ixgb_link_reset(struct ixgb_hw *hw);
45
46static void ixgb_optics_reset(struct ixgb_hw *hw);
47
48static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
49
50static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
51
52static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
53
54static void ixgb_clear_vfta(struct ixgb_hw *hw);
55
56static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
57
58static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
59 u32 reg_address,
60 u32 phy_address,
61 u32 device_type);
62
63static bool ixgb_setup_fc(struct ixgb_hw *hw);
64
65static bool mac_addr_valid(u8 *mac_addr);
66
67static u32 ixgb_mac_reset(struct ixgb_hw *hw)
68{
69 u32 ctrl_reg;
70
71 ctrl_reg = IXGB_CTRL0_RST |
72 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
73 IXGB_CTRL0_SDP2_DIR |
74 IXGB_CTRL0_SDP1_DIR |
75 IXGB_CTRL0_SDP0_DIR |
76 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
77 IXGB_CTRL0_SDP2 |
78 IXGB_CTRL0_SDP0;
79
80#ifdef HP_ZX1
81 /* Workaround for 82597EX reset errata */
82 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
83#else
84 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
85#endif
86
87 /* Delay a few ms just to allow the reset to complete */
88 msleep(IXGB_DELAY_AFTER_RESET);
89 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
90#ifdef DBG
91 /* Make sure the self-clearing global reset bit did self clear */
92 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
93#endif
94
95 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
96 ctrl_reg = /* Enable interrupt from XFP and SerDes */
97 IXGB_CTRL1_GPI0_EN |
98 IXGB_CTRL1_SDP6_DIR |
99 IXGB_CTRL1_SDP7_DIR |
100 IXGB_CTRL1_SDP6 |
101 IXGB_CTRL1_SDP7;
102 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
103 ixgb_optics_reset_bcm(hw);
104 }
105
106 if (hw->phy_type == ixgb_phy_type_txn17401)
107 ixgb_optics_reset(hw);
108
109 return ctrl_reg;
110}
111
112/******************************************************************************
113 * Reset the transmit and receive units; mask and clear all interrupts.
114 *
115 * hw - Struct containing variables accessed by shared code
116 *****************************************************************************/
117bool
118ixgb_adapter_stop(struct ixgb_hw *hw)
119{
120 u32 ctrl_reg;
121 u32 icr_reg;
122
123 DEBUGFUNC("ixgb_adapter_stop");
124
125 /* If we are stopped or resetting exit gracefully and wait to be
126 * started again before accessing the hardware.
127 */
128 if (hw->adapter_stopped) {
129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
130 return false;
131 }
132
133 /* Set the Adapter Stopped flag so other driver functions stop
134 * touching the Hardware.
135 */
136 hw->adapter_stopped = true;
137
138 /* Clear interrupt mask to stop board from generating interrupts */
139 DEBUGOUT("Masking off all interrupts\n");
140 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
141
142 /* Disable the Transmit and Receive units. Then delay to allow
143 * any pending transactions to complete before we hit the MAC with
144 * the global reset.
145 */
146 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
147 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
148 msleep(IXGB_DELAY_BEFORE_RESET);
149
150 /* Issue a global reset to the MAC. This will reset the chip's
151 * transmit, receive, DMA, and link units. It will not effect
152 * the current PCI configuration. The global reset bit is self-
153 * clearing, and should clear within a microsecond.
154 */
155 DEBUGOUT("Issuing a global reset to MAC\n");
156
157 ctrl_reg = ixgb_mac_reset(hw);
158
159 /* Clear interrupt mask to stop board from generating interrupts */
160 DEBUGOUT("Masking off all interrupts\n");
161 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
162
163 /* Clear any pending interrupt events. */
164 icr_reg = IXGB_READ_REG(hw, ICR);
165
166 return (ctrl_reg & IXGB_CTRL0_RST);
167}
168
169
170/******************************************************************************
171 * Identifies the vendor of the optics module on the adapter. The SR adapters
172 * support two different types of XPAK optics, so it is necessary to determine
173 * which optics are present before applying any optics-specific workarounds.
174 *
175 * hw - Struct containing variables accessed by shared code.
176 *
177 * Returns: the vendor of the XPAK optics module.
178 *****************************************************************************/
179static ixgb_xpak_vendor
180ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
181{
182 u32 i;
183 u16 vendor_name[5];
184 ixgb_xpak_vendor xpak_vendor;
185
186 DEBUGFUNC("ixgb_identify_xpak_vendor");
187
188 /* Read the first few bytes of the vendor string from the XPAK NVR
189 * registers. These are standard XENPAK/XPAK registers, so all XPAK
190 * devices should implement them. */
191 for (i = 0; i < 5; i++) {
192 vendor_name[i] = ixgb_read_phy_reg(hw,
193 MDIO_PMA_PMD_XPAK_VENDOR_NAME
194 + i, IXGB_PHY_ADDRESS,
195 MDIO_MMD_PMAPMD);
196 }
197
198 /* Determine the actual vendor */
199 if (vendor_name[0] == 'I' &&
200 vendor_name[1] == 'N' &&
201 vendor_name[2] == 'T' &&
202 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
203 xpak_vendor = ixgb_xpak_vendor_intel;
204 } else {
205 xpak_vendor = ixgb_xpak_vendor_infineon;
206 }
207
208 return (xpak_vendor);
209}
210
211/******************************************************************************
212 * Determine the physical layer module on the adapter.
213 *
214 * hw - Struct containing variables accessed by shared code. The device_id
215 * field must be (correctly) populated before calling this routine.
216 *
217 * Returns: the phy type of the adapter.
218 *****************************************************************************/
219static ixgb_phy_type
220ixgb_identify_phy(struct ixgb_hw *hw)
221{
222 ixgb_phy_type phy_type;
223 ixgb_xpak_vendor xpak_vendor;
224
225 DEBUGFUNC("ixgb_identify_phy");
226
227 /* Infer the transceiver/phy type from the device id */
228 switch (hw->device_id) {
229 case IXGB_DEVICE_ID_82597EX:
230 DEBUGOUT("Identified TXN17401 optics\n");
231 phy_type = ixgb_phy_type_txn17401;
232 break;
233
234 case IXGB_DEVICE_ID_82597EX_SR:
235 /* The SR adapters carry two different types of XPAK optics
236 * modules; read the vendor identifier to determine the exact
237 * type of optics. */
238 xpak_vendor = ixgb_identify_xpak_vendor(hw);
239 if (xpak_vendor == ixgb_xpak_vendor_intel) {
240 DEBUGOUT("Identified TXN17201 optics\n");
241 phy_type = ixgb_phy_type_txn17201;
242 } else {
243 DEBUGOUT("Identified G6005 optics\n");
244 phy_type = ixgb_phy_type_g6005;
245 }
246 break;
247 case IXGB_DEVICE_ID_82597EX_LR:
248 DEBUGOUT("Identified G6104 optics\n");
249 phy_type = ixgb_phy_type_g6104;
250 break;
251 case IXGB_DEVICE_ID_82597EX_CX4:
252 DEBUGOUT("Identified CX4\n");
253 xpak_vendor = ixgb_identify_xpak_vendor(hw);
254 if (xpak_vendor == ixgb_xpak_vendor_intel) {
255 DEBUGOUT("Identified TXN17201 optics\n");
256 phy_type = ixgb_phy_type_txn17201;
257 } else {
258 DEBUGOUT("Identified G6005 optics\n");
259 phy_type = ixgb_phy_type_g6005;
260 }
261 break;
262 default:
263 DEBUGOUT("Unknown physical layer module\n");
264 phy_type = ixgb_phy_type_unknown;
265 break;
266 }
267
268 /* update phy type for sun specific board */
269 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
270 phy_type = ixgb_phy_type_bcm;
271
272 return (phy_type);
273}
274
275/******************************************************************************
276 * Performs basic configuration of the adapter.
277 *
278 * hw - Struct containing variables accessed by shared code
279 *
280 * Resets the controller.
281 * Reads and validates the EEPROM.
282 * Initializes the receive address registers.
283 * Initializes the multicast table.
284 * Clears all on-chip counters.
285 * Calls routine to setup flow control settings.
286 * Leaves the transmit and receive units disabled and uninitialized.
287 *
288 * Returns:
289 * true if successful,
290 * false if unrecoverable problems were encountered.
291 *****************************************************************************/
292bool
293ixgb_init_hw(struct ixgb_hw *hw)
294{
295 u32 i;
296 u32 ctrl_reg;
297 bool status;
298
299 DEBUGFUNC("ixgb_init_hw");
300
301 /* Issue a global reset to the MAC. This will reset the chip's
302 * transmit, receive, DMA, and link units. It will not effect
303 * the current PCI configuration. The global reset bit is self-
304 * clearing, and should clear within a microsecond.
305 */
306 DEBUGOUT("Issuing a global reset to MAC\n");
307
308 ctrl_reg = ixgb_mac_reset(hw);
309
310 DEBUGOUT("Issuing an EE reset to MAC\n");
311#ifdef HP_ZX1
312 /* Workaround for 82597EX reset errata */
313 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
314#else
315 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
316#endif
317
318 /* Delay a few ms just to allow the reset to complete */
319 msleep(IXGB_DELAY_AFTER_EE_RESET);
320
321 if (!ixgb_get_eeprom_data(hw))
322 return false;
323
324 /* Use the device id to determine the type of phy/transceiver. */
325 hw->device_id = ixgb_get_ee_device_id(hw);
326 hw->phy_type = ixgb_identify_phy(hw);
327
328 /* Setup the receive addresses.
329 * Receive Address Registers (RARs 0 - 15).
330 */
331 ixgb_init_rx_addrs(hw);
332
333 /*
334 * Check that a valid MAC address has been set.
335 * If it is not valid, we fail hardware init.
336 */
337 if (!mac_addr_valid(hw->curr_mac_addr)) {
338 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
339 return(false);
340 }
341
342 /* tell the routines in this file they can access hardware again */
343 hw->adapter_stopped = false;
344
345 /* Fill in the bus_info structure */
346 ixgb_get_bus_info(hw);
347
348 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n");
350 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
351 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
352
353 /* Zero out the VLAN Filter Table Array */
354 ixgb_clear_vfta(hw);
355
356 /* Zero all of the hardware counters */
357 ixgb_clear_hw_cntrs(hw);
358
359 /* Call a subroutine to setup flow control. */
360 status = ixgb_setup_fc(hw);
361
362 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
363 ixgb_check_for_link(hw);
364
365 return (status);
366}
367
368/******************************************************************************
369 * Initializes receive address filters.
370 *
371 * hw - Struct containing variables accessed by shared code
372 *
373 * Places the MAC address in receive address register 0 and clears the rest
374 * of the receive address registers. Clears the multicast table. Assumes
375 * the receiver is in reset when the routine is called.
376 *****************************************************************************/
377static void
378ixgb_init_rx_addrs(struct ixgb_hw *hw)
379{
380 u32 i;
381
382 DEBUGFUNC("ixgb_init_rx_addrs");
383
384 /*
385 * If the current mac address is valid, assume it is a software override
386 * to the permanent address.
387 * Otherwise, use the permanent address from the eeprom.
388 */
389 if (!mac_addr_valid(hw->curr_mac_addr)) {
390
391 /* Get the MAC address from the eeprom for later reference */
392 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
393
394 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
395 hw->curr_mac_addr[0],
396 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
397 DEBUGOUT3("%.2X %.2X %.2X\n",
398 hw->curr_mac_addr[3],
399 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
400 } else {
401
402 /* Setup the receive address. */
403 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
404 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
405 hw->curr_mac_addr[0],
406 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
407 DEBUGOUT3("%.2X %.2X %.2X\n",
408 hw->curr_mac_addr[3],
409 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
410
411 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
412 }
413
414 /* Zero out the other 15 receive addresses. */
415 DEBUGOUT("Clearing RAR[1-15]\n");
416 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
417 /* Write high reg first to disable the AV bit first */
418 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
419 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
420 }
421
422 return;
423}
424
425/******************************************************************************
426 * Updates the MAC's list of multicast addresses.
427 *
428 * hw - Struct containing variables accessed by shared code
429 * mc_addr_list - the list of new multicast addresses
430 * mc_addr_count - number of addresses
431 * pad - number of bytes between addresses in the list
432 *
433 * The given list replaces any existing list. Clears the last 15 receive
434 * address registers and the multicast table. Uses receive address registers
435 * for the first 15 multicast addresses, and hashes the rest into the
436 * multicast table.
437 *****************************************************************************/
438void
439ixgb_mc_addr_list_update(struct ixgb_hw *hw,
440 u8 *mc_addr_list,
441 u32 mc_addr_count,
442 u32 pad)
443{
444 u32 hash_value;
445 u32 i;
446 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
447
448 DEBUGFUNC("ixgb_mc_addr_list_update");
449
450 /* Set the new number of MC addresses that we are being requested to use. */
451 hw->num_mc_addrs = mc_addr_count;
452
453 /* Clear RAR[1-15] */
454 DEBUGOUT(" Clearing RAR[1-15]\n");
455 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
456 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
457 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
458 }
459
460 /* Clear the MTA */
461 DEBUGOUT(" Clearing MTA\n");
462 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
463 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
464
465 /* Add the new addresses */
466 for (i = 0; i < mc_addr_count; i++) {
467 DEBUGOUT(" Adding the multicast addresses:\n");
468 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
469 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
470 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
471 1],
472 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
473 2],
474 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
475 3],
476 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
477 4],
478 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
479 5]);
480
481 /* Place this multicast address in the RAR if there is room, *
482 * else put it in the MTA
483 */
484 if (rar_used_count < IXGB_RAR_ENTRIES) {
485 ixgb_rar_set(hw,
486 mc_addr_list +
487 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
488 rar_used_count);
489 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
490 rar_used_count++;
491 } else {
492 hash_value = ixgb_hash_mc_addr(hw,
493 mc_addr_list +
494 (i *
495 (IXGB_ETH_LENGTH_OF_ADDRESS
496 + pad)));
497
498 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
499
500 ixgb_mta_set(hw, hash_value);
501 }
502 }
503
504 DEBUGOUT("MC Update Complete\n");
505 return;
506}
507
508/******************************************************************************
509 * Hashes an address to determine its location in the multicast table
510 *
511 * hw - Struct containing variables accessed by shared code
512 * mc_addr - the multicast address to hash
513 *
514 * Returns:
515 * The hash value
516 *****************************************************************************/
517static u32
518ixgb_hash_mc_addr(struct ixgb_hw *hw,
519 u8 *mc_addr)
520{
521 u32 hash_value = 0;
522
523 DEBUGFUNC("ixgb_hash_mc_addr");
524
525 /* The portion of the address that is used for the hash table is
526 * determined by the mc_filter_type setting.
527 */
528 switch (hw->mc_filter_type) {
529 /* [0] [1] [2] [3] [4] [5]
530 * 01 AA 00 12 34 56
531 * LSB MSB - According to H/W docs */
532 case 0:
533 /* [47:36] i.e. 0x563 for above example address */
534 hash_value =
535 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
536 break;
537 case 1: /* [46:35] i.e. 0xAC6 for above example address */
538 hash_value =
539 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
540 break;
541 case 2: /* [45:34] i.e. 0x5D8 for above example address */
542 hash_value =
543 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
544 break;
545 case 3: /* [43:32] i.e. 0x634 for above example address */
546 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
547 break;
548 default:
549 /* Invalid mc_filter_type, what should we do? */
550 DEBUGOUT("MC filter type param set incorrectly\n");
551 ASSERT(0);
552 break;
553 }
554
555 hash_value &= 0xFFF;
556 return (hash_value);
557}
558
559/******************************************************************************
560 * Sets the bit in the multicast table corresponding to the hash value.
561 *
562 * hw - Struct containing variables accessed by shared code
563 * hash_value - Multicast address hash value
564 *****************************************************************************/
565static void
566ixgb_mta_set(struct ixgb_hw *hw,
567 u32 hash_value)
568{
569 u32 hash_bit, hash_reg;
570 u32 mta_reg;
571
572 /* The MTA is a register array of 128 32-bit registers.
573 * It is treated like an array of 4096 bits. We want to set
574 * bit BitArray[hash_value]. So we figure out what register
575 * the bit is in, read it, OR in the new bit, then write
576 * back the new value. The register is determined by the
577 * upper 7 bits of the hash value and the bit within that
578 * register are determined by the lower 5 bits of the value.
579 */
580 hash_reg = (hash_value >> 5) & 0x7F;
581 hash_bit = hash_value & 0x1F;
582
583 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
584
585 mta_reg |= (1 << hash_bit);
586
587 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
588
589 return;
590}
591
592/******************************************************************************
593 * Puts an ethernet address into a receive address register.
594 *
595 * hw - Struct containing variables accessed by shared code
596 * addr - Address to put into receive address register
597 * index - Receive address register to write
598 *****************************************************************************/
599void
600ixgb_rar_set(struct ixgb_hw *hw,
601 u8 *addr,
602 u32 index)
603{
604 u32 rar_low, rar_high;
605
606 DEBUGFUNC("ixgb_rar_set");
607
608 /* HW expects these in little endian so we reverse the byte order
609 * from network order (big endian) to little endian
610 */
611 rar_low = ((u32) addr[0] |
612 ((u32)addr[1] << 8) |
613 ((u32)addr[2] << 16) |
614 ((u32)addr[3] << 24));
615
616 rar_high = ((u32) addr[4] |
617 ((u32)addr[5] << 8) |
618 IXGB_RAH_AV);
619
620 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
621 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
622 return;
623}
624
625/******************************************************************************
626 * Writes a value to the specified offset in the VLAN filter table.
627 *
628 * hw - Struct containing variables accessed by shared code
629 * offset - Offset in VLAN filer table to write
630 * value - Value to write into VLAN filter table
631 *****************************************************************************/
632void
633ixgb_write_vfta(struct ixgb_hw *hw,
634 u32 offset,
635 u32 value)
636{
637 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
638 return;
639}
640
641/******************************************************************************
642 * Clears the VLAN filer table
643 *
644 * hw - Struct containing variables accessed by shared code
645 *****************************************************************************/
646static void
647ixgb_clear_vfta(struct ixgb_hw *hw)
648{
649 u32 offset;
650
651 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
652 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
653 return;
654}
655
656/******************************************************************************
657 * Configures the flow control settings based on SW configuration.
658 *
659 * hw - Struct containing variables accessed by shared code
660 *****************************************************************************/
661
662static bool
663ixgb_setup_fc(struct ixgb_hw *hw)
664{
665 u32 ctrl_reg;
666 u32 pap_reg = 0; /* by default, assume no pause time */
667 bool status = true;
668
669 DEBUGFUNC("ixgb_setup_fc");
670
671 /* Get the current control reg 0 settings */
672 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
673
674 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
675 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
676
677 /* The possible values of the "flow_control" parameter are:
678 * 0: Flow control is completely disabled
679 * 1: Rx flow control is enabled (we can receive pause frames
680 * but not send pause frames).
681 * 2: Tx flow control is enabled (we can send pause frames
682 * but we do not support receiving pause frames).
683 * 3: Both Rx and TX flow control (symmetric) are enabled.
684 * other: Invalid.
685 */
686 switch (hw->fc.type) {
687 case ixgb_fc_none: /* 0 */
688 /* Set CMDC bit to disable Rx Flow control */
689 ctrl_reg |= (IXGB_CTRL0_CMDC);
690 break;
691 case ixgb_fc_rx_pause: /* 1 */
692 /* RX Flow control is enabled, and TX Flow control is
693 * disabled.
694 */
695 ctrl_reg |= (IXGB_CTRL0_RPE);
696 break;
697 case ixgb_fc_tx_pause: /* 2 */
698 /* TX Flow control is enabled, and RX Flow control is
699 * disabled, by a software over-ride.
700 */
701 ctrl_reg |= (IXGB_CTRL0_TPE);
702 pap_reg = hw->fc.pause_time;
703 break;
704 case ixgb_fc_full: /* 3 */
705 /* Flow control (both RX and TX) is enabled by a software
706 * over-ride.
707 */
708 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
709 pap_reg = hw->fc.pause_time;
710 break;
711 default:
712 /* We should never get here. The value should be 0-3. */
713 DEBUGOUT("Flow control param set incorrectly\n");
714 ASSERT(0);
715 break;
716 }
717
718 /* Write the new settings */
719 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
720
721 if (pap_reg != 0)
722 IXGB_WRITE_REG(hw, PAP, pap_reg);
723
724 /* Set the flow control receive threshold registers. Normally,
725 * these registers will be set to a default threshold that may be
726 * adjusted later by the driver's runtime code. However, if the
727 * ability to transmit pause frames in not enabled, then these
728 * registers will be set to 0.
729 */
730 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
731 IXGB_WRITE_REG(hw, FCRTL, 0);
732 IXGB_WRITE_REG(hw, FCRTH, 0);
733 } else {
734 /* We need to set up the Receive Threshold high and low water
735 * marks as well as (optionally) enabling the transmission of XON
736 * frames. */
737 if (hw->fc.send_xon) {
738 IXGB_WRITE_REG(hw, FCRTL,
739 (hw->fc.low_water | IXGB_FCRTL_XONE));
740 } else {
741 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
742 }
743 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
744 }
745 return (status);
746}
747
748/******************************************************************************
749 * Reads a word from a device over the Management Data Interface (MDI) bus.
750 * This interface is used to manage Physical layer devices.
751 *
752 * hw - Struct containing variables accessed by hw code
753 * reg_address - Offset of device register being read.
754 * phy_address - Address of device on MDI.
755 *
756 * Returns: Data word (16 bits) from MDI device.
757 *
758 * The 82597EX has support for several MDI access methods. This routine
759 * uses the new protocol MDI Single Command and Address Operation.
760 * This requires that first an address cycle command is sent, followed by a
761 * read command.
762 *****************************************************************************/
763static u16
764ixgb_read_phy_reg(struct ixgb_hw *hw,
765 u32 reg_address,
766 u32 phy_address,
767 u32 device_type)
768{
769 u32 i;
770 u32 data;
771 u32 command = 0;
772
773 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
774 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
775 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
776
777 /* Setup and write the address cycle command */
778 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
779 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
780 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
781 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
782
783 IXGB_WRITE_REG(hw, MSCA, command);
784
785 /**************************************************************
786 ** Check every 10 usec to see if the address cycle completed
787 ** The COMMAND bit will clear when the operation is complete.
788 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
789 ** from the CPU Write to the Ready bit assertion.
790 **************************************************************/
791
792 for (i = 0; i < 10; i++)
793 {
794 udelay(10);
795
796 command = IXGB_READ_REG(hw, MSCA);
797
798 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
799 break;
800 }
801
802 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
803
804 /* Address cycle complete, setup and write the read command */
805 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
806 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
807 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
808 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
809
810 IXGB_WRITE_REG(hw, MSCA, command);
811
812 /**************************************************************
813 ** Check every 10 usec to see if the read command completed
814 ** The COMMAND bit will clear when the operation is complete.
815 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
816 ** from the CPU Write to the Ready bit assertion.
817 **************************************************************/
818
819 for (i = 0; i < 10; i++)
820 {
821 udelay(10);
822
823 command = IXGB_READ_REG(hw, MSCA);
824
825 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
826 break;
827 }
828
829 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
830
831 /* Operation is complete, get the data from the MDIO Read/Write Data
832 * register and return.
833 */
834 data = IXGB_READ_REG(hw, MSRWD);
835 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
836 return((u16) data);
837}
838
839/******************************************************************************
840 * Writes a word to a device over the Management Data Interface (MDI) bus.
841 * This interface is used to manage Physical layer devices.
842 *
843 * hw - Struct containing variables accessed by hw code
844 * reg_address - Offset of device register being read.
845 * phy_address - Address of device on MDI.
846 * device_type - Also known as the Device ID or DID.
847 * data - 16-bit value to be written
848 *
849 * Returns: void.
850 *
851 * The 82597EX has support for several MDI access methods. This routine
852 * uses the new protocol MDI Single Command and Address Operation.
853 * This requires that first an address cycle command is sent, followed by a
854 * write command.
855 *****************************************************************************/
856static void
857ixgb_write_phy_reg(struct ixgb_hw *hw,
858 u32 reg_address,
859 u32 phy_address,
860 u32 device_type,
861 u16 data)
862{
863 u32 i;
864 u32 command = 0;
865
866 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
867 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
868 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
869
870 /* Put the data in the MDIO Read/Write Data register */
871 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
872
873 /* Setup and write the address cycle command */
874 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
875 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
876 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
877 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
878
879 IXGB_WRITE_REG(hw, MSCA, command);
880
881 /**************************************************************
882 ** Check every 10 usec to see if the address cycle completed
883 ** The COMMAND bit will clear when the operation is complete.
884 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
885 ** from the CPU Write to the Ready bit assertion.
886 **************************************************************/
887
888 for (i = 0; i < 10; i++)
889 {
890 udelay(10);
891
892 command = IXGB_READ_REG(hw, MSCA);
893
894 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
895 break;
896 }
897
898 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
899
900 /* Address cycle complete, setup and write the write command */
901 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
902 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
903 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
904 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
905
906 IXGB_WRITE_REG(hw, MSCA, command);
907
908 /**************************************************************
909 ** Check every 10 usec to see if the read command completed
910 ** The COMMAND bit will clear when the operation is complete.
911 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
912 ** from the CPU Write to the Ready bit assertion.
913 **************************************************************/
914
915 for (i = 0; i < 10; i++)
916 {
917 udelay(10);
918
919 command = IXGB_READ_REG(hw, MSCA);
920
921 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
922 break;
923 }
924
925 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
926
927 /* Operation is complete, return. */
928}
929
930/******************************************************************************
931 * Checks to see if the link status of the hardware has changed.
932 *
933 * hw - Struct containing variables accessed by hw code
934 *
935 * Called by any function that needs to check the link status of the adapter.
936 *****************************************************************************/
937void
938ixgb_check_for_link(struct ixgb_hw *hw)
939{
940 u32 status_reg;
941 u32 xpcss_reg;
942
943 DEBUGFUNC("ixgb_check_for_link");
944
945 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
946 status_reg = IXGB_READ_REG(hw, STATUS);
947
948 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
949 (status_reg & IXGB_STATUS_LU)) {
950 hw->link_up = true;
951 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
952 (status_reg & IXGB_STATUS_LU)) {
953 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
954 hw->link_up = ixgb_link_reset(hw);
955 } else {
956 /*
957 * 82597EX errata. Since the lane deskew problem may prevent
958 * link, reset the link before reporting link down.
959 */
960 hw->link_up = ixgb_link_reset(hw);
961 }
962 /* Anything else for 10 Gig?? */
963}
964
965/******************************************************************************
966 * Check for a bad link condition that may have occurred.
967 * The indication is that the RFC / LFC registers may be incrementing
968 * continually. A full adapter reset is required to recover.
969 *
970 * hw - Struct containing variables accessed by hw code
971 *
972 * Called by any function that needs to check the link status of the adapter.
973 *****************************************************************************/
974bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
975{
976 u32 newLFC, newRFC;
977 bool bad_link_returncode = false;
978
979 if (hw->phy_type == ixgb_phy_type_txn17401) {
980 newLFC = IXGB_READ_REG(hw, LFC);
981 newRFC = IXGB_READ_REG(hw, RFC);
982 if ((hw->lastLFC + 250 < newLFC)
983 || (hw->lastRFC + 250 < newRFC)) {
984 DEBUGOUT
985 ("BAD LINK! too many LFC/RFC since last check\n");
986 bad_link_returncode = true;
987 }
988 hw->lastLFC = newLFC;
989 hw->lastRFC = newRFC;
990 }
991
992 return bad_link_returncode;
993}
994
995/******************************************************************************
996 * Clears all hardware statistics counters.
997 *
998 * hw - Struct containing variables accessed by shared code
999 *****************************************************************************/
1000static void
1001ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
1002{
1003 volatile u32 temp_reg;
1004
1005 DEBUGFUNC("ixgb_clear_hw_cntrs");
1006
1007 /* if we are stopped or resetting exit gracefully */
1008 if (hw->adapter_stopped) {
1009 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
1010 return;
1011 }
1012
1013 temp_reg = IXGB_READ_REG(hw, TPRL);
1014 temp_reg = IXGB_READ_REG(hw, TPRH);
1015 temp_reg = IXGB_READ_REG(hw, GPRCL);
1016 temp_reg = IXGB_READ_REG(hw, GPRCH);
1017 temp_reg = IXGB_READ_REG(hw, BPRCL);
1018 temp_reg = IXGB_READ_REG(hw, BPRCH);
1019 temp_reg = IXGB_READ_REG(hw, MPRCL);
1020 temp_reg = IXGB_READ_REG(hw, MPRCH);
1021 temp_reg = IXGB_READ_REG(hw, UPRCL);
1022 temp_reg = IXGB_READ_REG(hw, UPRCH);
1023 temp_reg = IXGB_READ_REG(hw, VPRCL);
1024 temp_reg = IXGB_READ_REG(hw, VPRCH);
1025 temp_reg = IXGB_READ_REG(hw, JPRCL);
1026 temp_reg = IXGB_READ_REG(hw, JPRCH);
1027 temp_reg = IXGB_READ_REG(hw, GORCL);
1028 temp_reg = IXGB_READ_REG(hw, GORCH);
1029 temp_reg = IXGB_READ_REG(hw, TORL);
1030 temp_reg = IXGB_READ_REG(hw, TORH);
1031 temp_reg = IXGB_READ_REG(hw, RNBC);
1032 temp_reg = IXGB_READ_REG(hw, RUC);
1033 temp_reg = IXGB_READ_REG(hw, ROC);
1034 temp_reg = IXGB_READ_REG(hw, RLEC);
1035 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1036 temp_reg = IXGB_READ_REG(hw, ICBC);
1037 temp_reg = IXGB_READ_REG(hw, ECBC);
1038 temp_reg = IXGB_READ_REG(hw, MPC);
1039 temp_reg = IXGB_READ_REG(hw, TPTL);
1040 temp_reg = IXGB_READ_REG(hw, TPTH);
1041 temp_reg = IXGB_READ_REG(hw, GPTCL);
1042 temp_reg = IXGB_READ_REG(hw, GPTCH);
1043 temp_reg = IXGB_READ_REG(hw, BPTCL);
1044 temp_reg = IXGB_READ_REG(hw, BPTCH);
1045 temp_reg = IXGB_READ_REG(hw, MPTCL);
1046 temp_reg = IXGB_READ_REG(hw, MPTCH);
1047 temp_reg = IXGB_READ_REG(hw, UPTCL);
1048 temp_reg = IXGB_READ_REG(hw, UPTCH);
1049 temp_reg = IXGB_READ_REG(hw, VPTCL);
1050 temp_reg = IXGB_READ_REG(hw, VPTCH);
1051 temp_reg = IXGB_READ_REG(hw, JPTCL);
1052 temp_reg = IXGB_READ_REG(hw, JPTCH);
1053 temp_reg = IXGB_READ_REG(hw, GOTCL);
1054 temp_reg = IXGB_READ_REG(hw, GOTCH);
1055 temp_reg = IXGB_READ_REG(hw, TOTL);
1056 temp_reg = IXGB_READ_REG(hw, TOTH);
1057 temp_reg = IXGB_READ_REG(hw, DC);
1058 temp_reg = IXGB_READ_REG(hw, PLT64C);
1059 temp_reg = IXGB_READ_REG(hw, TSCTC);
1060 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1061 temp_reg = IXGB_READ_REG(hw, IBIC);
1062 temp_reg = IXGB_READ_REG(hw, RFC);
1063 temp_reg = IXGB_READ_REG(hw, LFC);
1064 temp_reg = IXGB_READ_REG(hw, PFRC);
1065 temp_reg = IXGB_READ_REG(hw, PFTC);
1066 temp_reg = IXGB_READ_REG(hw, MCFRC);
1067 temp_reg = IXGB_READ_REG(hw, MCFTC);
1068 temp_reg = IXGB_READ_REG(hw, XONRXC);
1069 temp_reg = IXGB_READ_REG(hw, XONTXC);
1070 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1071 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1072 temp_reg = IXGB_READ_REG(hw, RJC);
1073 return;
1074}
1075
1076/******************************************************************************
1077 * Turns on the software controllable LED
1078 *
1079 * hw - Struct containing variables accessed by shared code
1080 *****************************************************************************/
1081void
1082ixgb_led_on(struct ixgb_hw *hw)
1083{
1084 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1085
1086 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1087 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1088 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1089 return;
1090}
1091
1092/******************************************************************************
1093 * Turns off the software controllable LED
1094 *
1095 * hw - Struct containing variables accessed by shared code
1096 *****************************************************************************/
1097void
1098ixgb_led_off(struct ixgb_hw *hw)
1099{
1100 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1101
1102 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1103 ctrl0_reg |= IXGB_CTRL0_SDP0;
1104 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1105 return;
1106}
1107
1108/******************************************************************************
1109 * Gets the current PCI bus type, speed, and width of the hardware
1110 *
1111 * hw - Struct containing variables accessed by shared code
1112 *****************************************************************************/
1113static void
1114ixgb_get_bus_info(struct ixgb_hw *hw)
1115{
1116 u32 status_reg;
1117
1118 status_reg = IXGB_READ_REG(hw, STATUS);
1119
1120 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1121 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1122
1123 if (hw->bus.type == ixgb_bus_type_pci) {
1124 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1125 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1126 } else {
1127 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1128 case IXGB_STATUS_PCIX_SPD_66:
1129 hw->bus.speed = ixgb_bus_speed_66;
1130 break;
1131 case IXGB_STATUS_PCIX_SPD_100:
1132 hw->bus.speed = ixgb_bus_speed_100;
1133 break;
1134 case IXGB_STATUS_PCIX_SPD_133:
1135 hw->bus.speed = ixgb_bus_speed_133;
1136 break;
1137 default:
1138 hw->bus.speed = ixgb_bus_speed_reserved;
1139 break;
1140 }
1141 }
1142
1143 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1144 ixgb_bus_width_64 : ixgb_bus_width_32;
1145
1146 return;
1147}
1148
1149/******************************************************************************
1150 * Tests a MAC address to ensure it is a valid Individual Address
1151 *
1152 * mac_addr - pointer to MAC address.
1153 *
1154 *****************************************************************************/
1155static bool
1156mac_addr_valid(u8 *mac_addr)
1157{
1158 bool is_valid = true;
1159 DEBUGFUNC("mac_addr_valid");
1160
1161 /* Make sure it is not a multicast address */
1162 if (IS_MULTICAST(mac_addr)) {
1163 DEBUGOUT("MAC address is multicast\n");
1164 is_valid = false;
1165 }
1166 /* Not a broadcast address */
1167 else if (IS_BROADCAST(mac_addr)) {
1168 DEBUGOUT("MAC address is broadcast\n");
1169 is_valid = false;
1170 }
1171 /* Reject the zero address */
1172 else if (mac_addr[0] == 0 &&
1173 mac_addr[1] == 0 &&
1174 mac_addr[2] == 0 &&
1175 mac_addr[3] == 0 &&
1176 mac_addr[4] == 0 &&
1177 mac_addr[5] == 0) {
1178 DEBUGOUT("MAC address is all zeros\n");
1179 is_valid = false;
1180 }
1181 return (is_valid);
1182}
1183
1184/******************************************************************************
1185 * Resets the 10GbE link. Waits the settle time and returns the state of
1186 * the link.
1187 *
1188 * hw - Struct containing variables accessed by shared code
1189 *****************************************************************************/
1190static bool
1191ixgb_link_reset(struct ixgb_hw *hw)
1192{
1193 bool link_status = false;
1194 u8 wait_retries = MAX_RESET_ITERATIONS;
1195 u8 lrst_retries = MAX_RESET_ITERATIONS;
1196
1197 do {
1198 /* Reset the link */
1199 IXGB_WRITE_REG(hw, CTRL0,
1200 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1201
1202 /* Wait for link-up and lane re-alignment */
1203 do {
1204 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1205 link_status =
1206 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1207 && (IXGB_READ_REG(hw, XPCSS) &
1208 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1209 } while (!link_status && --wait_retries);
1210
1211 } while (!link_status && --lrst_retries);
1212
1213 return link_status;
1214}
1215
1216/******************************************************************************
1217 * Resets the 10GbE optics module.
1218 *
1219 * hw - Struct containing variables accessed by shared code
1220 *****************************************************************************/
1221static void
1222ixgb_optics_reset(struct ixgb_hw *hw)
1223{
1224 if (hw->phy_type == ixgb_phy_type_txn17401) {
1225 u16 mdio_reg;
1226
1227 ixgb_write_phy_reg(hw,
1228 MDIO_CTRL1,
1229 IXGB_PHY_ADDRESS,
1230 MDIO_MMD_PMAPMD,
1231 MDIO_CTRL1_RESET);
1232
1233 mdio_reg = ixgb_read_phy_reg(hw,
1234 MDIO_CTRL1,
1235 IXGB_PHY_ADDRESS,
1236 MDIO_MMD_PMAPMD);
1237 }
1238
1239 return;
1240}
1241
1242/******************************************************************************
1243 * Resets the 10GbE optics module for Sun variant NIC.
1244 *
1245 * hw - Struct containing variables accessed by shared code
1246 *****************************************************************************/
1247
1248#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1249#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1250#define IXGB_BCM8704_USER_CTRL_REG 0xC800
1251#define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1252#define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1253#define IXGB_SUN_PHY_ADDRESS 0x0000
1254#define IXGB_SUN_PHY_RESET_DELAY 305
1255
1256static void
1257ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1258{
1259 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1260 ctrl &= ~IXGB_CTRL0_SDP2;
1261 ctrl |= IXGB_CTRL0_SDP3;
1262 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1263
1264 /* SerDes needs extra delay */
1265 msleep(IXGB_SUN_PHY_RESET_DELAY);
1266
1267 /* Broadcom 7408L configuration */
1268 /* Reference clock config */
1269 ixgb_write_phy_reg(hw,
1270 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1271 IXGB_SUN_PHY_ADDRESS,
1272 IXGB_BCM8704_USER_DEV3_ADDR,
1273 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1274 /* we must read the registers twice */
1275 ixgb_read_phy_reg(hw,
1276 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1277 IXGB_SUN_PHY_ADDRESS,
1278 IXGB_BCM8704_USER_DEV3_ADDR);
1279 ixgb_read_phy_reg(hw,
1280 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1281 IXGB_SUN_PHY_ADDRESS,
1282 IXGB_BCM8704_USER_DEV3_ADDR);
1283
1284 ixgb_write_phy_reg(hw,
1285 IXGB_BCM8704_USER_CTRL_REG,
1286 IXGB_SUN_PHY_ADDRESS,
1287 IXGB_BCM8704_USER_DEV3_ADDR,
1288 IXGB_BCM8704_USER_CTRL_REG_VAL);
1289 ixgb_read_phy_reg(hw,
1290 IXGB_BCM8704_USER_CTRL_REG,
1291 IXGB_SUN_PHY_ADDRESS,
1292 IXGB_BCM8704_USER_DEV3_ADDR);
1293 ixgb_read_phy_reg(hw,
1294 IXGB_BCM8704_USER_CTRL_REG,
1295 IXGB_SUN_PHY_ADDRESS,
1296 IXGB_BCM8704_USER_DEV3_ADDR);
1297
1298 /* SerDes needs extra delay */
1299 msleep(IXGB_SUN_PHY_RESET_DELAY);
1300
1301 return;
1302}