tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#include <linux/serial_core.h>
2#include <asm/io.h>
3#include <linux/gpio.h>
4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
24# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
34# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
35# define PORT_PTCR 0xA405011EUL
36# define PORT_PVCR 0xA4050122UL
37# define SCIF_ORER 0x0200 /* overrun error bit */
38#elif defined(CONFIG_SH_RTS7751R2D)
39# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751R)
49# define SCSPTR1 0xffe0001c /* 8 bit SCI */
50# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51# define SCIF_ORER 0x0001 /* overrun error bit */
52# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
53 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
54 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
55#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
56# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
57# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
58# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
59# define SCIF_ORER 0x0001 /* overrun error bit */
60# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
61#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
62# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
63# define SCIF_ORER 0x0001 /* overrun error bit */
64# define PACR 0xa4050100
65# define PBCR 0xa4050102
66# define SCSCR_INIT(port) 0x3B
67#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
68# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
69# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
70# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
71# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
72# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
73#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
74# define PADR 0xA4050120
75# define PSDR 0xA405013e
76# define PWDR 0xA4050166
77# define PSCR 0xA405011E
78# define SCIF_ORER 0x0001 /* overrun error bit */
79# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
80#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
81# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
82# define SCSPTR0 SCPDR0
83# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
86# define SCSPTR0 0xa4050160
87# define SCSPTR1 0xa405013e
88# define SCSPTR2 0xa4050160
89# define SCSPTR3 0xa405013e
90# define SCSPTR4 0xa4050128
91# define SCSPTR5 0xa4050128
92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
97#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
98# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
99# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
102# define SCIF_BASE_ADDR 0x01030000
103# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
104# define SCIF_PTR2_OFFS 0x0000020
105# define SCIF_LSR2_OFFS 0x0000024
106# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
107# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
108# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
109#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
110# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
111# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
112#elif defined(CONFIG_H8S2678)
113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
115#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
116# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
117# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
118# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
119# define SCIF_ORER 0x0001 /* overrun error bit */
120# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
121#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
122# define SCSPTR0 0xff923020 /* 16 bit SCIF */
123# define SCSPTR1 0xff924020 /* 16 bit SCIF */
124# define SCSPTR2 0xff925020 /* 16 bit SCIF */
125# define SCIF_ORER 0x0001 /* overrun error bit */
126# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
127#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
128# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
129# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
130# define SCIF_ORER 0x0001 /* Overrun error bit */
131# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
132#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
133 defined(CONFIG_CPU_SUBTYPE_SH7786)
134# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
135# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
136# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
137# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
138# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
139# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
140# define SCIF_ORER 0x0001 /* Overrun error bit */
141# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
143 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
144 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
145 defined(CONFIG_CPU_SUBTYPE_SH7263)
146# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
147# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
148# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
149# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
150# if defined(CONFIG_CPU_SUBTYPE_SH7201)
151# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
152# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
153# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
154# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
155# endif
156# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
157#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
158# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
159# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
160# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
161# define SCIF_ORER 0x0001 /* overrun error bit */
162# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
163#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
164# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
165# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
166# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
167# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
168# define SCIF_ORER 0x0001 /* Overrun error bit */
169# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
170#else
171# error CPU subtype not defined
172#endif
173
174/* SCSCR */
175#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
176#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
177#define SCI_CTRL_FLAGS_TE 0x20 /* all */
178#define SCI_CTRL_FLAGS_RE 0x10 /* all */
179#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
190 defined(CONFIG_CPU_SUBTYPE_SHX3)
191#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
192#else
193#define SCI_CTRL_FLAGS_REIE 0
194#endif
195/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
196/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
198/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
199
200/* SCxSR SCI */
201#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209
210#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
211
212/* SCxSR SCIF */
213#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221
222#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
223 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
224 defined(CONFIG_CPU_SUBTYPE_SH7721)
225# define SCIF_ORER 0x0200
226# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
227# define SCIF_RFDC_MASK 0x007f
228# define SCIF_TXROOM_MAX 64
229#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
230# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
231# define SCIF_RFDC_MASK 0x007f
232# define SCIF_TXROOM_MAX 64
233/* SH7763 SCIF2 support */
234# define SCIF2_RFDC_MASK 0x001f
235# define SCIF2_TXROOM_MAX 16
236#else
237# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
238# define SCIF_RFDC_MASK 0x001f
239# define SCIF_TXROOM_MAX 16
240#endif
241
242#ifndef SCIF_ORER
243#define SCIF_ORER 0x0000
244#endif
245
246#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
247#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
248#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
249#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
250#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
251#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
252#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
253#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
254
255#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
256 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7721)
258# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
259# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
260# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
261# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
262#else
263# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
264# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
265# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
266# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
267#endif
268
269/* SCFCR */
270#define SCFCR_RFRST 0x0002
271#define SCFCR_TFRST 0x0004
272#define SCFCR_TCRST 0x4000
273#define SCFCR_MCE 0x0008
274
275#define SCI_MAJOR 204
276#define SCI_MINOR_START 8
277
278/* Generic serial flags */
279#define SCI_RX_THROTTLE 0x0000001
280
281#define SCI_MAGIC 0xbabeface
282
283/*
284 * Events are used to schedule things to happen at timer-interrupt
285 * time, instead of at rs interrupt time.
286 */
287#define SCI_EVENT_WRITE_WAKEUP 0
288
289#define SCI_IN(size, offset) \
290 if ((size) == 8) { \
291 return ioread8(port->membase + (offset)); \
292 } else { \
293 return ioread16(port->membase + (offset)); \
294 }
295#define SCI_OUT(size, offset, value) \
296 if ((size) == 8) { \
297 iowrite8(value, port->membase + (offset)); \
298 } else if ((size) == 16) { \
299 iowrite16(value, port->membase + (offset)); \
300 }
301
302#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
303 static inline unsigned int sci_##name##_in(struct uart_port *port) \
304 { \
305 if (port->type == PORT_SCIF) { \
306 SCI_IN(scif_size, scif_offset) \
307 } else { /* PORT_SCI or PORT_SCIFA */ \
308 SCI_IN(sci_size, sci_offset); \
309 } \
310 } \
311 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
312 { \
313 if (port->type == PORT_SCIF) { \
314 SCI_OUT(scif_size, scif_offset, value) \
315 } else { /* PORT_SCI or PORT_SCIFA */ \
316 SCI_OUT(sci_size, sci_offset, value); \
317 } \
318 }
319
320#ifdef CONFIG_H8300
321/* h8300 don't have SCIF */
322#define CPU_SCIF_FNS(name) \
323 static inline unsigned int sci_##name##_in(struct uart_port *port) \
324 { \
325 return 0; \
326 } \
327 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
328 { \
329 }
330#else
331#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
332 static inline unsigned int sci_##name##_in(struct uart_port *port) \
333 { \
334 SCI_IN(scif_size, scif_offset); \
335 } \
336 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
337 { \
338 SCI_OUT(scif_size, scif_offset, value); \
339 }
340#endif
341
342#define CPU_SCI_FNS(name, sci_offset, sci_size) \
343 static inline unsigned int sci_##name##_in(struct uart_port* port) \
344 { \
345 SCI_IN(sci_size, sci_offset); \
346 } \
347 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
348 { \
349 SCI_OUT(sci_size, sci_offset, value); \
350 }
351
352#ifdef CONFIG_CPU_SH3
353#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
354#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
355 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
356 h8_sci_offset, h8_sci_size) \
357 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
358#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
359 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
360#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
361 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
362 defined(CONFIG_CPU_SUBTYPE_SH7721)
363#define SCIF_FNS(name, scif_offset, scif_size) \
364 CPU_SCIF_FNS(name, scif_offset, scif_size)
365#else
366#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
367 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
368 h8_sci_offset, h8_sci_size) \
369 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
370#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
371 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
372#endif
373#elif defined(__H8300H__) || defined(__H8300S__)
374#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
375 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
376 h8_sci_offset, h8_sci_size) \
377 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
378#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
379 CPU_SCIF_FNS(name)
380#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
381 defined(CONFIG_CPU_SUBTYPE_SH7724)
382 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
383 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
384 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
385 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
386#else
387#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
388 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
389 h8_sci_offset, h8_sci_size) \
390 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
391#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
392 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
393#endif
394
395#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
396 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
397 defined(CONFIG_CPU_SUBTYPE_SH7721)
398
399SCIF_FNS(SCSMR, 0x00, 16)
400SCIF_FNS(SCBRR, 0x04, 8)
401SCIF_FNS(SCSCR, 0x08, 16)
402SCIF_FNS(SCTDSR, 0x0c, 8)
403SCIF_FNS(SCFER, 0x10, 16)
404SCIF_FNS(SCxSR, 0x14, 16)
405SCIF_FNS(SCFCR, 0x18, 16)
406SCIF_FNS(SCFDR, 0x1c, 16)
407SCIF_FNS(SCxTDR, 0x20, 8)
408SCIF_FNS(SCxRDR, 0x24, 8)
409SCIF_FNS(SCLSR, 0x24, 16)
410#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
411 defined(CONFIG_CPU_SUBTYPE_SH7724)
412SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
413SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
414SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
415SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
416SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
417SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
418SCIx_FNS(SCSPTR, 0, 0, 0, 0)
419SCIF_FNS(SCTDSR, 0x0c, 8)
420SCIF_FNS(SCFER, 0x10, 16)
421SCIF_FNS(SCFCR, 0x18, 16)
422SCIF_FNS(SCFDR, 0x1c, 16)
423SCIF_FNS(SCLSR, 0x24, 16)
424#else
425/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
426/* name off sz off sz off sz off sz off sz*/
427SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
428SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
429SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
430SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
431SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
432SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
433SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
434#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
435 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
436 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
437 defined(CONFIG_CPU_SUBTYPE_SH7786)
438SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
439SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
440SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
441SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
442SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
443#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
444SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
445SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
446SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
447SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
448SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
449SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
450SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
451#else
452SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
453#if defined(CONFIG_CPU_SUBTYPE_SH7722)
454SCIF_FNS(SCSPTR, 0, 0, 0, 0)
455#else
456SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
457#endif
458SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
459#endif
460#endif
461#define sci_in(port, reg) sci_##reg##_in(port)
462#define sci_out(port, reg, value) sci_##reg##_out(port, value)
463
464/* H8/300 series SCI pins assignment */
465#if defined(__H8300H__) || defined(__H8300S__)
466static const struct __attribute__((packed)) {
467 int port; /* GPIO port no */
468 unsigned short rx,tx; /* GPIO bit no */
469} h8300_sci_pins[] = {
470#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
471 { /* SCI0 */
472 .port = H8300_GPIO_P9,
473 .rx = H8300_GPIO_B2,
474 .tx = H8300_GPIO_B0,
475 },
476 { /* SCI1 */
477 .port = H8300_GPIO_P9,
478 .rx = H8300_GPIO_B3,
479 .tx = H8300_GPIO_B1,
480 },
481 { /* SCI2 */
482 .port = H8300_GPIO_PB,
483 .rx = H8300_GPIO_B7,
484 .tx = H8300_GPIO_B6,
485 }
486#elif defined(CONFIG_H8S2678)
487 { /* SCI0 */
488 .port = H8300_GPIO_P3,
489 .rx = H8300_GPIO_B2,
490 .tx = H8300_GPIO_B0,
491 },
492 { /* SCI1 */
493 .port = H8300_GPIO_P3,
494 .rx = H8300_GPIO_B3,
495 .tx = H8300_GPIO_B1,
496 },
497 { /* SCI2 */
498 .port = H8300_GPIO_P5,
499 .rx = H8300_GPIO_B1,
500 .tx = H8300_GPIO_B0,
501 }
502#endif
503};
504#endif
505
506#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
507 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
508 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
509 defined(CONFIG_CPU_SUBTYPE_SH7709)
510static inline int sci_rxd_in(struct uart_port *port)
511{
512 if (port->mapbase == 0xfffffe80)
513 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
514 if (port->mapbase == 0xa4000150)
515 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
516 if (port->mapbase == 0xa4000140)
517 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
518 return 1;
519}
520#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
521static inline int sci_rxd_in(struct uart_port *port)
522{
523 if (port->mapbase == SCIF0)
524 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
525 if (port->mapbase == SCIF2)
526 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
527 return 1;
528}
529#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
530static inline int sci_rxd_in(struct uart_port *port)
531{
532 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
533}
534#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
535 defined(CONFIG_CPU_SUBTYPE_SH7721)
536static inline int sci_rxd_in(struct uart_port *port)
537{
538 if (port->mapbase == 0xa4430000)
539 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
540 else if (port->mapbase == 0xa4438000)
541 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
542 return 1;
543}
544#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
545 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
546 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
547 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
548 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
549 defined(CONFIG_CPU_SUBTYPE_SH7091)
550static inline int sci_rxd_in(struct uart_port *port)
551{
552 if (port->mapbase == 0xffe00000)
553 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
554 if (port->mapbase == 0xffe80000)
555 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
556 return 1;
557}
558#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
559static inline int sci_rxd_in(struct uart_port *port)
560{
561 if (port->mapbase == 0xffe80000)
562 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
563 return 1;
564}
565#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
566static inline int sci_rxd_in(struct uart_port *port)
567{
568 if (port->mapbase == 0xfe600000)
569 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
570 if (port->mapbase == 0xfe610000)
571 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
572 if (port->mapbase == 0xfe620000)
573 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
574 return 1;
575}
576#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
577static inline int sci_rxd_in(struct uart_port *port)
578{
579 if (port->mapbase == 0xffe00000)
580 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
581 if (port->mapbase == 0xffe10000)
582 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
583 if (port->mapbase == 0xffe20000)
584 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
585 if (port->mapbase == 0xffe30000)
586 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
587 return 1;
588}
589#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
590static inline int sci_rxd_in(struct uart_port *port)
591{
592 if (port->mapbase == 0xffe00000)
593 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
594 return 1;
595}
596#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
597static inline int sci_rxd_in(struct uart_port *port)
598{
599 if (port->mapbase == 0xffe00000)
600 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
601 if (port->mapbase == 0xffe10000)
602 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
603 if (port->mapbase == 0xffe20000)
604 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
605
606 return 1;
607}
608#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
609static inline int sci_rxd_in(struct uart_port *port)
610{
611 if (port->mapbase == 0xffe00000)
612 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
613 if (port->mapbase == 0xffe10000)
614 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
615 if (port->mapbase == 0xffe20000)
616 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
617 if (port->mapbase == 0xa4e30000)
618 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
619 if (port->mapbase == 0xa4e40000)
620 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
621 if (port->mapbase == 0xa4e50000)
622 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
623 return 1;
624}
625#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
626# define SCFSR 0x0010
627# define SCASSR 0x0014
628static inline int sci_rxd_in(struct uart_port *port)
629{
630 if (port->type == PORT_SCIF)
631 return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
632 if (port->type == PORT_SCIFA)
633 return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
634 return 1;
635}
636#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
637static inline int sci_rxd_in(struct uart_port *port)
638{
639 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
640}
641#elif defined(__H8300H__) || defined(__H8300S__)
642static inline int sci_rxd_in(struct uart_port *port)
643{
644 int ch = (port->mapbase - SMR0) >> 3;
645 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
646}
647#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
648static inline int sci_rxd_in(struct uart_port *port)
649{
650 if (port->mapbase == 0xffe00000)
651 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xffe08000)
653 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
654 if (port->mapbase == 0xffe10000)
655 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
656
657 return 1;
658}
659#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
660static inline int sci_rxd_in(struct uart_port *port)
661{
662 if (port->mapbase == 0xff923000)
663 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
664 if (port->mapbase == 0xff924000)
665 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
666 if (port->mapbase == 0xff925000)
667 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
668 return 1;
669}
670#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
671static inline int sci_rxd_in(struct uart_port *port)
672{
673 if (port->mapbase == 0xffe00000)
674 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
675 if (port->mapbase == 0xffe10000)
676 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
677 return 1;
678}
679#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
680 defined(CONFIG_CPU_SUBTYPE_SH7786)
681static inline int sci_rxd_in(struct uart_port *port)
682{
683 if (port->mapbase == 0xffea0000)
684 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
685 if (port->mapbase == 0xffeb0000)
686 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
687 if (port->mapbase == 0xffec0000)
688 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
689 if (port->mapbase == 0xffed0000)
690 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
691 if (port->mapbase == 0xffee0000)
692 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
693 if (port->mapbase == 0xffef0000)
694 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
695 return 1;
696}
697#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
698 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
699 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
700 defined(CONFIG_CPU_SUBTYPE_SH7263)
701static inline int sci_rxd_in(struct uart_port *port)
702{
703 if (port->mapbase == 0xfffe8000)
704 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
705 if (port->mapbase == 0xfffe8800)
706 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
707 if (port->mapbase == 0xfffe9000)
708 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
709 if (port->mapbase == 0xfffe9800)
710 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
711#if defined(CONFIG_CPU_SUBTYPE_SH7201)
712 if (port->mapbase == 0xfffeA000)
713 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
714 if (port->mapbase == 0xfffeA800)
715 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
716 if (port->mapbase == 0xfffeB000)
717 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
718 if (port->mapbase == 0xfffeB800)
719 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
720#endif
721 return 1;
722}
723#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
724static inline int sci_rxd_in(struct uart_port *port)
725{
726 if (port->mapbase == 0xf8400000)
727 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
728 if (port->mapbase == 0xf8410000)
729 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
730 if (port->mapbase == 0xf8420000)
731 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
732 return 1;
733}
734#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
735static inline int sci_rxd_in(struct uart_port *port)
736{
737 if (port->mapbase == 0xffc30000)
738 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
739 if (port->mapbase == 0xffc40000)
740 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
741 if (port->mapbase == 0xffc50000)
742 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
743 if (port->mapbase == 0xffc60000)
744 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
745 return 1;
746}
747#endif
748
749/*
750 * Values for the BitRate Register (SCBRR)
751 *
752 * The values are actually divisors for a frequency which can
753 * be internal to the SH3 (14.7456MHz) or derived from an external
754 * clock source. This driver assumes the internal clock is used;
755 * to support using an external clock source, config options or
756 * possibly command-line options would need to be added.
757 *
758 * Also, to support speeds below 2400 (why?) the lower 2 bits of
759 * the SCSMR register would also need to be set to non-zero values.
760 *
761 * -- Greg Banks 27Feb2000
762 *
763 * Answer: The SCBRR register is only eight bits, and the value in
764 * it gets larger with lower baud rates. At around 2400 (depending on
765 * the peripherial module clock) you run out of bits. However the
766 * lower two bits of SCSMR allow the module clock to be divided down,
767 * scaling the value which is needed in SCBRR.
768 *
769 * -- Stuart Menefy - 23 May 2000
770 *
771 * I meant, why would anyone bother with bitrates below 2400.
772 *
773 * -- Greg Banks - 7Jul2000
774 *
775 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
776 * tape reader as a console!
777 *
778 * -- Mitch Davis - 15 Jul 2000
779 */
780
781#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
782 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
783 defined(CONFIG_CPU_SUBTYPE_SH7786)
784#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
785#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
786 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
787 defined(CONFIG_CPU_SUBTYPE_SH7721)
788#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
789#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
790 defined(CONFIG_CPU_SUBTYPE_SH7724)
791static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
792{
793 if (port->type == PORT_SCIF)
794 return (clk+16*bps)/(32*bps)-1;
795 else
796 return ((clk*2)+16*bps)/(16*bps)-1;
797}
798#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
799#elif defined(__H8300H__) || defined(__H8300S__)
800#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
801#else /* Generic SH */
802#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
803#endif