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1/*
2 * include/asm-ppc/mpc52xx_psc.h
3 *
4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5 * PSCs. Theses are shared between multiple drivers since a PSC can be
6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7 *
8 *
9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10 *
11 * Based/Extracted from some header of the 2.4 originally written by
12 * Dale Farnsworth <dfarnsworth@mvista.com>
13 *
14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright (C) 2003 MontaVista, Software, Inc.
16 *
17 * This file is licensed under the terms of the GNU General Public License
18 * version 2. This program is licensed "as is" without any warranty of any
19 * kind, whether express or implied.
20 */
21
22#ifndef __ASM_MPC52xx_PSC_H__
23#define __ASM_MPC52xx_PSC_H__
24
25#include <asm/types.h>
26
27/* Max number of PSCs */
28#define MPC52xx_PSC_MAXNUM 6
29
30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_UNEX_RX 0x0001
32#define MPC52xx_PSC_SR_DATA_VAL 0x0002
33#define MPC52xx_PSC_SR_DATA_OVR 0x0004
34#define MPC52xx_PSC_SR_CMDSEND 0x0008
35#define MPC52xx_PSC_SR_CDE 0x0080
36#define MPC52xx_PSC_SR_RXRDY 0x0100
37#define MPC52xx_PSC_SR_RXFULL 0x0200
38#define MPC52xx_PSC_SR_TXRDY 0x0400
39#define MPC52xx_PSC_SR_TXEMP 0x0800
40#define MPC52xx_PSC_SR_OE 0x1000
41#define MPC52xx_PSC_SR_PE 0x2000
42#define MPC52xx_PSC_SR_FE 0x4000
43#define MPC52xx_PSC_SR_RB 0x8000
44
45/* PSC Command values */
46#define MPC52xx_PSC_RX_ENABLE 0x0001
47#define MPC52xx_PSC_RX_DISABLE 0x0002
48#define MPC52xx_PSC_TX_ENABLE 0x0004
49#define MPC52xx_PSC_TX_DISABLE 0x0008
50#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
51#define MPC52xx_PSC_RST_RX 0x0020
52#define MPC52xx_PSC_RST_TX 0x0030
53#define MPC52xx_PSC_RST_ERR_STAT 0x0040
54#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
55#define MPC52xx_PSC_START_BRK 0x0060
56#define MPC52xx_PSC_STOP_BRK 0x0070
57
58/* PSC TxRx FIFO status bits */
59#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
60#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
61#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
62#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
63#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
64#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
65#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
66
67/* PSC interrupt status/mask bits */
68#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
69#define MPC52xx_PSC_IMR_DATA_VALID 0x0002
70#define MPC52xx_PSC_IMR_DATA_OVR 0x0004
71#define MPC52xx_PSC_IMR_CMD_SEND 0x0008
72#define MPC52xx_PSC_IMR_ERROR 0x0040
73#define MPC52xx_PSC_IMR_DEOF 0x0080
74#define MPC52xx_PSC_IMR_TXRDY 0x0100
75#define MPC52xx_PSC_IMR_RXRDY 0x0200
76#define MPC52xx_PSC_IMR_DB 0x0400
77#define MPC52xx_PSC_IMR_TXEMP 0x0800
78#define MPC52xx_PSC_IMR_ORERR 0x1000
79#define MPC52xx_PSC_IMR_IPC 0x8000
80
81/* PSC input port change bits */
82#define MPC52xx_PSC_CTS 0x01
83#define MPC52xx_PSC_DCD 0x02
84#define MPC52xx_PSC_D_CTS 0x10
85#define MPC52xx_PSC_D_DCD 0x20
86
87/* PSC acr bits */
88#define MPC52xx_PSC_IEC_CTS 0x01
89#define MPC52xx_PSC_IEC_DCD 0x02
90
91/* PSC output port bits */
92#define MPC52xx_PSC_OP_RTS 0x01
93#define MPC52xx_PSC_OP_RES 0x02
94
95/* PSC mode fields */
96#define MPC52xx_PSC_MODE_5_BITS 0x00
97#define MPC52xx_PSC_MODE_6_BITS 0x01
98#define MPC52xx_PSC_MODE_7_BITS 0x02
99#define MPC52xx_PSC_MODE_8_BITS 0x03
100#define MPC52xx_PSC_MODE_BITS_MASK 0x03
101#define MPC52xx_PSC_MODE_PAREVEN 0x00
102#define MPC52xx_PSC_MODE_PARODD 0x04
103#define MPC52xx_PSC_MODE_PARFORCE 0x08
104#define MPC52xx_PSC_MODE_PARNONE 0x10
105#define MPC52xx_PSC_MODE_ERR 0x20
106#define MPC52xx_PSC_MODE_FFULL 0x40
107#define MPC52xx_PSC_MODE_RXRTS 0x80
108
109#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
110#define MPC52xx_PSC_MODE_ONE_STOP 0x07
111#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
112#define MPC52xx_PSC_MODE_TXCTS 0x10
113
114#define MPC52xx_PSC_RFNUM_MASK 0x01ff
115
116#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
117#define MPC52xx_PSC_SICR_SHDR (1 << 28)
118#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
119#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
120#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
121#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
122#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
123#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
124#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
125#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
126#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
127#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
128#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
129#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
130#define MPC52xx_PSC_SICR_AWR (1 << 30)
131#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
132#define MPC52xx_PSC_SICR_I2S (1 << 22)
133#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
134#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
135#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
136#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
137#define MPC52xx_PSC_SICR_ESAI (1 << 17)
138#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
139#define MPC52xx_PSC_SICR_SPI (1 << 15)
140#define MPC52xx_PSC_SICR_MSTR (1 << 14)
141#define MPC52xx_PSC_SICR_CPOL (1 << 13)
142#define MPC52xx_PSC_SICR_CPHA (1 << 12)
143#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
144#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
145
146/* Structure of the hardware registers */
147struct mpc52xx_psc {
148 u8 mode; /* PSC + 0x00 */
149 u8 reserved0[3];
150 union { /* PSC + 0x04 */
151 u16 status;
152 u16 clock_select;
153 } sr_csr;
154#define mpc52xx_psc_status sr_csr.status
155#define mpc52xx_psc_clock_select sr_csr.clock_select
156 u16 reserved1;
157 u8 command; /* PSC + 0x08 */
158 u8 reserved2[3];
159 union { /* PSC + 0x0c */
160 u8 buffer_8;
161 u16 buffer_16;
162 u32 buffer_32;
163 } buffer;
164#define mpc52xx_psc_buffer_8 buffer.buffer_8
165#define mpc52xx_psc_buffer_16 buffer.buffer_16
166#define mpc52xx_psc_buffer_32 buffer.buffer_32
167 union { /* PSC + 0x10 */
168 u8 ipcr;
169 u8 acr;
170 } ipcr_acr;
171#define mpc52xx_psc_ipcr ipcr_acr.ipcr
172#define mpc52xx_psc_acr ipcr_acr.acr
173 u8 reserved3[3];
174 union { /* PSC + 0x14 */
175 u16 isr;
176 u16 imr;
177 } isr_imr;
178#define mpc52xx_psc_isr isr_imr.isr
179#define mpc52xx_psc_imr isr_imr.imr
180 u16 reserved4;
181 u8 ctur; /* PSC + 0x18 */
182 u8 reserved5[3];
183 u8 ctlr; /* PSC + 0x1c */
184 u8 reserved6[3];
185 /* BitClkDiv field of CCR is byte swapped in
186 * the hardware for mpc5200/b compatibility */
187 u32 ccr; /* PSC + 0x20 */
188 u32 ac97_slots; /* PSC + 0x24 */
189 u32 ac97_cmd; /* PSC + 0x28 */
190 u32 ac97_data; /* PSC + 0x2c */
191 u8 ivr; /* PSC + 0x30 */
192 u8 reserved8[3];
193 u8 ip; /* PSC + 0x34 */
194 u8 reserved9[3];
195 u8 op1; /* PSC + 0x38 */
196 u8 reserved10[3];
197 u8 op0; /* PSC + 0x3c */
198 u8 reserved11[3];
199 u32 sicr; /* PSC + 0x40 */
200 u8 ircr1; /* PSC + 0x44 */
201 u8 reserved13[3];
202 u8 ircr2; /* PSC + 0x44 */
203 u8 reserved14[3];
204 u8 irsdr; /* PSC + 0x4c */
205 u8 reserved15[3];
206 u8 irmdr; /* PSC + 0x50 */
207 u8 reserved16[3];
208 u8 irfdr; /* PSC + 0x54 */
209 u8 reserved17[3];
210};
211
212struct mpc52xx_psc_fifo {
213 u16 rfnum; /* PSC + 0x58 */
214 u16 reserved18;
215 u16 tfnum; /* PSC + 0x5c */
216 u16 reserved19;
217 u32 rfdata; /* PSC + 0x60 */
218 u16 rfstat; /* PSC + 0x64 */
219 u16 reserved20;
220 u8 rfcntl; /* PSC + 0x68 */
221 u8 reserved21[5];
222 u16 rfalarm; /* PSC + 0x6e */
223 u16 reserved22;
224 u16 rfrptr; /* PSC + 0x72 */
225 u16 reserved23;
226 u16 rfwptr; /* PSC + 0x76 */
227 u16 reserved24;
228 u16 rflrfptr; /* PSC + 0x7a */
229 u16 reserved25;
230 u16 rflwfptr; /* PSC + 0x7e */
231 u32 tfdata; /* PSC + 0x80 */
232 u16 tfstat; /* PSC + 0x84 */
233 u16 reserved26;
234 u8 tfcntl; /* PSC + 0x88 */
235 u8 reserved27[5];
236 u16 tfalarm; /* PSC + 0x8e */
237 u16 reserved28;
238 u16 tfrptr; /* PSC + 0x92 */
239 u16 reserved29;
240 u16 tfwptr; /* PSC + 0x96 */
241 u16 reserved30;
242 u16 tflrfptr; /* PSC + 0x9a */
243 u16 reserved31;
244 u16 tflwfptr; /* PSC + 0x9e */
245};
246
247#define MPC512x_PSC_FIFO_RESET_SLICE 0x80
248#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
249#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
250
251#define MPC512x_PSC_FIFO_EMPTY 0x1
252#define MPC512x_PSC_FIFO_FULL 0x2
253#define MPC512x_PSC_FIFO_ALARM 0x4
254#define MPC512x_PSC_FIFO_URERR 0x8
255#define MPC512x_PSC_FIFO_ORERR 0x01
256#define MPC512x_PSC_FIFO_MEMERROR 0x02
257
258struct mpc512x_psc_fifo {
259 u32 reserved1[10];
260 u32 txcmd; /* PSC + 0x80 */
261 u32 txalarm; /* PSC + 0x84 */
262 u32 txsr; /* PSC + 0x88 */
263 u32 txisr; /* PSC + 0x8c */
264 u32 tximr; /* PSC + 0x90 */
265 u32 txcnt; /* PSC + 0x94 */
266 u32 txptr; /* PSC + 0x98 */
267 u32 txsz; /* PSC + 0x9c */
268 u32 reserved2[7];
269 union {
270 u8 txdata_8;
271 u16 txdata_16;
272 u32 txdata_32;
273 } txdata; /* PSC + 0xbc */
274#define txdata_8 txdata.txdata_8
275#define txdata_16 txdata.txdata_16
276#define txdata_32 txdata.txdata_32
277 u32 rxcmd; /* PSC + 0xc0 */
278 u32 rxalarm; /* PSC + 0xc4 */
279 u32 rxsr; /* PSC + 0xc8 */
280 u32 rxisr; /* PSC + 0xcc */
281 u32 rximr; /* PSC + 0xd0 */
282 u32 rxcnt; /* PSC + 0xd4 */
283 u32 rxptr; /* PSC + 0xd8 */
284 u32 rxsz; /* PSC + 0xdc */
285 u32 reserved3[7];
286 union {
287 u8 rxdata_8;
288 u16 rxdata_16;
289 u32 rxdata_32;
290 } rxdata; /* PSC + 0xfc */
291#define rxdata_8 rxdata.rxdata_8
292#define rxdata_16 rxdata.rxdata_16
293#define rxdata_32 rxdata.rxdata_32
294};
295
296#endif /* __ASM_MPC52xx_PSC_H__ */