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1/* 2 * drivers/serial/sh-sci.c 3 * 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 5 * 6 * Copyright (C) 2002 - 2008 Paul Mundt 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 * 18 * This file is subject to the terms and conditions of the GNU General Public 19 * License. See the file "COPYING" in the main directory of this archive 20 * for more details. 21 */ 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 23#define SUPPORT_SYSRQ 24#endif 25 26#undef DEBUG 27 28#include <linux/module.h> 29#include <linux/errno.h> 30#include <linux/timer.h> 31#include <linux/interrupt.h> 32#include <linux/tty.h> 33#include <linux/tty_flip.h> 34#include <linux/serial.h> 35#include <linux/major.h> 36#include <linux/string.h> 37#include <linux/sysrq.h> 38#include <linux/ioport.h> 39#include <linux/mm.h> 40#include <linux/init.h> 41#include <linux/delay.h> 42#include <linux/console.h> 43#include <linux/platform_device.h> 44#include <linux/serial_sci.h> 45#include <linux/notifier.h> 46#include <linux/cpufreq.h> 47#include <linux/clk.h> 48#include <linux/ctype.h> 49#include <linux/err.h> 50#include <linux/list.h> 51 52#ifdef CONFIG_SUPERH 53#include <asm/clock.h> 54#include <asm/sh_bios.h> 55#endif 56 57#ifdef CONFIG_H8300 58#include <asm/gpio.h> 59#endif 60 61#include "sh-sci.h" 62 63struct sci_port { 64 struct uart_port port; 65 66 /* Port type */ 67 unsigned int type; 68 69 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ 70 unsigned int irqs[SCIx_NR_IRQS]; 71 72 /* Port enable callback */ 73 void (*enable)(struct uart_port *port); 74 75 /* Port disable callback */ 76 void (*disable)(struct uart_port *port); 77 78 /* Break timer */ 79 struct timer_list break_timer; 80 int break_flag; 81 82#ifdef CONFIG_HAVE_CLK 83 /* Interface clock */ 84 struct clk *iclk; 85 /* Data clock */ 86 struct clk *dclk; 87#endif 88 struct list_head node; 89}; 90 91struct sh_sci_priv { 92 spinlock_t lock; 93 struct list_head ports; 94 95#ifdef CONFIG_HAVE_CLK 96 struct notifier_block clk_nb; 97#endif 98}; 99 100/* Function prototypes */ 101static void sci_stop_tx(struct uart_port *port); 102 103#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 104 105static struct sci_port sci_ports[SCI_NPORTS]; 106static struct uart_driver sci_uart_driver; 107 108static inline struct sci_port * 109to_sci_port(struct uart_port *uart) 110{ 111 return container_of(uart, struct sci_port, port); 112} 113 114#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 115 116#ifdef CONFIG_CONSOLE_POLL 117static inline void handle_error(struct uart_port *port) 118{ 119 /* Clear error flags */ 120 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 121} 122 123static int sci_poll_get_char(struct uart_port *port) 124{ 125 unsigned short status; 126 int c; 127 128 do { 129 status = sci_in(port, SCxSR); 130 if (status & SCxSR_ERRORS(port)) { 131 handle_error(port); 132 continue; 133 } 134 } while (!(status & SCxSR_RDxF(port))); 135 136 c = sci_in(port, SCxRDR); 137 138 /* Dummy read */ 139 sci_in(port, SCxSR); 140 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 141 142 return c; 143} 144#endif 145 146static void sci_poll_put_char(struct uart_port *port, unsigned char c) 147{ 148 unsigned short status; 149 150 do { 151 status = sci_in(port, SCxSR); 152 } while (!(status & SCxSR_TDxE(port))); 153 154 sci_out(port, SCxTDR, c); 155 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 156} 157#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 158 159#if defined(__H8300S__) 160enum { sci_disable, sci_enable }; 161 162static void h8300_sci_config(struct uart_port *port, unsigned int ctrl) 163{ 164 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL; 165 int ch = (port->mapbase - SMR0) >> 3; 166 unsigned char mask = 1 << (ch+1); 167 168 if (ctrl == sci_disable) 169 *mstpcrl |= mask; 170 else 171 *mstpcrl &= ~mask; 172} 173 174static void h8300_sci_enable(struct uart_port *port) 175{ 176 h8300_sci_config(port, sci_enable); 177} 178 179static void h8300_sci_disable(struct uart_port *port) 180{ 181 h8300_sci_config(port, sci_disable); 182} 183#endif 184 185#if defined(__H8300H__) || defined(__H8300S__) 186static void sci_init_pins(struct uart_port *port, unsigned int cflag) 187{ 188 int ch = (port->mapbase - SMR0) >> 3; 189 190 /* set DDR regs */ 191 H8300_GPIO_DDR(h8300_sci_pins[ch].port, 192 h8300_sci_pins[ch].rx, 193 H8300_GPIO_INPUT); 194 H8300_GPIO_DDR(h8300_sci_pins[ch].port, 195 h8300_sci_pins[ch].tx, 196 H8300_GPIO_OUTPUT); 197 198 /* tx mark output*/ 199 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; 200} 201#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 202static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 203{ 204 if (port->mapbase == 0xA4400000) { 205 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); 206 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); 207 } else if (port->mapbase == 0xA4410000) 208 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); 209} 210#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) 211static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 212{ 213 unsigned short data; 214 215 if (cflag & CRTSCTS) { 216 /* enable RTS/CTS */ 217 if (port->mapbase == 0xa4430000) { /* SCIF0 */ 218 /* Clear PTCR bit 9-2; enable all scif pins but sck */ 219 data = __raw_readw(PORT_PTCR); 220 __raw_writew((data & 0xfc03), PORT_PTCR); 221 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ 222 /* Clear PVCR bit 9-2 */ 223 data = __raw_readw(PORT_PVCR); 224 __raw_writew((data & 0xfc03), PORT_PVCR); 225 } 226 } else { 227 if (port->mapbase == 0xa4430000) { /* SCIF0 */ 228 /* Clear PTCR bit 5-2; enable only tx and rx */ 229 data = __raw_readw(PORT_PTCR); 230 __raw_writew((data & 0xffc3), PORT_PTCR); 231 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ 232 /* Clear PVCR bit 5-2 */ 233 data = __raw_readw(PORT_PVCR); 234 __raw_writew((data & 0xffc3), PORT_PVCR); 235 } 236 } 237} 238#elif defined(CONFIG_CPU_SH3) 239/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ 240static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 241{ 242 unsigned short data; 243 244 /* We need to set SCPCR to enable RTS/CTS */ 245 data = __raw_readw(SCPCR); 246 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ 247 __raw_writew(data & 0x0fcf, SCPCR); 248 249 if (!(cflag & CRTSCTS)) { 250 /* We need to set SCPCR to enable RTS/CTS */ 251 data = __raw_readw(SCPCR); 252 /* Clear out SCP7MD1,0, SCP4MD1,0, 253 Set SCP6MD1,0 = {01} (output) */ 254 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); 255 256 data = ctrl_inb(SCPDR); 257 /* Set /RTS2 (bit6) = 0 */ 258 ctrl_outb(data & 0xbf, SCPDR); 259 } 260} 261#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 262static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 263{ 264 unsigned short data; 265 266 if (port->mapbase == 0xffe00000) { 267 data = __raw_readw(PSCR); 268 data &= ~0x03cf; 269 if (!(cflag & CRTSCTS)) 270 data |= 0x0340; 271 272 __raw_writew(data, PSCR); 273 } 274} 275#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 276 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 277 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 278 defined(CONFIG_CPU_SUBTYPE_SH7786) || \ 279 defined(CONFIG_CPU_SUBTYPE_SHX3) 280static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 281{ 282 if (!(cflag & CRTSCTS)) 283 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ 284} 285#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) 286static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 287{ 288 if (!(cflag & CRTSCTS)) 289 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ 290} 291#else 292static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 293{ 294 /* Nothing to do */ 295} 296#endif 297 298#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 299 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 300 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 301 defined(CONFIG_CPU_SUBTYPE_SH7786) 302static inline int scif_txroom(struct uart_port *port) 303{ 304 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); 305} 306 307static inline int scif_rxroom(struct uart_port *port) 308{ 309 return sci_in(port, SCRFDR) & 0xff; 310} 311#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 312static inline int scif_txroom(struct uart_port *port) 313{ 314 if ((port->mapbase == 0xffe00000) || 315 (port->mapbase == 0xffe08000)) { 316 /* SCIF0/1*/ 317 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); 318 } else { 319 /* SCIF2 */ 320 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); 321 } 322} 323 324static inline int scif_rxroom(struct uart_port *port) 325{ 326 if ((port->mapbase == 0xffe00000) || 327 (port->mapbase == 0xffe08000)) { 328 /* SCIF0/1*/ 329 return sci_in(port, SCRFDR) & 0xff; 330 } else { 331 /* SCIF2 */ 332 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 333 } 334} 335#else 336static inline int scif_txroom(struct uart_port *port) 337{ 338 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); 339} 340 341static inline int scif_rxroom(struct uart_port *port) 342{ 343 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 344} 345#endif 346 347static inline int sci_txroom(struct uart_port *port) 348{ 349 return (sci_in(port, SCxSR) & SCI_TDRE) != 0; 350} 351 352static inline int sci_rxroom(struct uart_port *port) 353{ 354 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 355} 356 357/* ********************************************************************** * 358 * the interrupt related routines * 359 * ********************************************************************** */ 360 361static void sci_transmit_chars(struct uart_port *port) 362{ 363 struct circ_buf *xmit = &port->info->xmit; 364 unsigned int stopped = uart_tx_stopped(port); 365 unsigned short status; 366 unsigned short ctrl; 367 int count; 368 369 status = sci_in(port, SCxSR); 370 if (!(status & SCxSR_TDxE(port))) { 371 ctrl = sci_in(port, SCSCR); 372 if (uart_circ_empty(xmit)) 373 ctrl &= ~SCI_CTRL_FLAGS_TIE; 374 else 375 ctrl |= SCI_CTRL_FLAGS_TIE; 376 sci_out(port, SCSCR, ctrl); 377 return; 378 } 379 380 if (port->type == PORT_SCI) 381 count = sci_txroom(port); 382 else 383 count = scif_txroom(port); 384 385 do { 386 unsigned char c; 387 388 if (port->x_char) { 389 c = port->x_char; 390 port->x_char = 0; 391 } else if (!uart_circ_empty(xmit) && !stopped) { 392 c = xmit->buf[xmit->tail]; 393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 394 } else { 395 break; 396 } 397 398 sci_out(port, SCxTDR, c); 399 400 port->icount.tx++; 401 } while (--count > 0); 402 403 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 404 405 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 406 uart_write_wakeup(port); 407 if (uart_circ_empty(xmit)) { 408 sci_stop_tx(port); 409 } else { 410 ctrl = sci_in(port, SCSCR); 411 412 if (port->type != PORT_SCI) { 413 sci_in(port, SCxSR); /* Dummy read */ 414 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 415 } 416 417 ctrl |= SCI_CTRL_FLAGS_TIE; 418 sci_out(port, SCSCR, ctrl); 419 } 420} 421 422/* On SH3, SCIF may read end-of-break as a space->mark char */ 423#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 424 425static inline void sci_receive_chars(struct uart_port *port) 426{ 427 struct sci_port *sci_port = to_sci_port(port); 428 struct tty_struct *tty = port->info->port.tty; 429 int i, count, copied = 0; 430 unsigned short status; 431 unsigned char flag; 432 433 status = sci_in(port, SCxSR); 434 if (!(status & SCxSR_RDxF(port))) 435 return; 436 437 while (1) { 438 if (port->type == PORT_SCI) 439 count = sci_rxroom(port); 440 else 441 count = scif_rxroom(port); 442 443 /* Don't copy more bytes than there is room for in the buffer */ 444 count = tty_buffer_request_room(tty, count); 445 446 /* If for any reason we can't copy more data, we're done! */ 447 if (count == 0) 448 break; 449 450 if (port->type == PORT_SCI) { 451 char c = sci_in(port, SCxRDR); 452 if (uart_handle_sysrq_char(port, c) || 453 sci_port->break_flag) 454 count = 0; 455 else 456 tty_insert_flip_char(tty, c, TTY_NORMAL); 457 } else { 458 for (i = 0; i < count; i++) { 459 char c = sci_in(port, SCxRDR); 460 status = sci_in(port, SCxSR); 461#if defined(CONFIG_CPU_SH3) 462 /* Skip "chars" during break */ 463 if (sci_port->break_flag) { 464 if ((c == 0) && 465 (status & SCxSR_FER(port))) { 466 count--; i--; 467 continue; 468 } 469 470 /* Nonzero => end-of-break */ 471 dev_dbg(port->dev, "debounce<%02x>\n", c); 472 sci_port->break_flag = 0; 473 474 if (STEPFN(c)) { 475 count--; i--; 476 continue; 477 } 478 } 479#endif /* CONFIG_CPU_SH3 */ 480 if (uart_handle_sysrq_char(port, c)) { 481 count--; i--; 482 continue; 483 } 484 485 /* Store data and status */ 486 if (status&SCxSR_FER(port)) { 487 flag = TTY_FRAME; 488 dev_notice(port->dev, "frame error\n"); 489 } else if (status&SCxSR_PER(port)) { 490 flag = TTY_PARITY; 491 dev_notice(port->dev, "parity error\n"); 492 } else 493 flag = TTY_NORMAL; 494 495 tty_insert_flip_char(tty, c, flag); 496 } 497 } 498 499 sci_in(port, SCxSR); /* dummy read */ 500 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 501 502 copied += count; 503 port->icount.rx += count; 504 } 505 506 if (copied) { 507 /* Tell the rest of the system the news. New characters! */ 508 tty_flip_buffer_push(tty); 509 } else { 510 sci_in(port, SCxSR); /* dummy read */ 511 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 512 } 513} 514 515#define SCI_BREAK_JIFFIES (HZ/20) 516/* The sci generates interrupts during the break, 517 * 1 per millisecond or so during the break period, for 9600 baud. 518 * So dont bother disabling interrupts. 519 * But dont want more than 1 break event. 520 * Use a kernel timer to periodically poll the rx line until 521 * the break is finished. 522 */ 523static void sci_schedule_break_timer(struct sci_port *port) 524{ 525 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; 526 add_timer(&port->break_timer); 527} 528/* Ensure that two consecutive samples find the break over. */ 529static void sci_break_timer(unsigned long data) 530{ 531 struct sci_port *port = (struct sci_port *)data; 532 533 if (sci_rxd_in(&port->port) == 0) { 534 port->break_flag = 1; 535 sci_schedule_break_timer(port); 536 } else if (port->break_flag == 1) { 537 /* break is over. */ 538 port->break_flag = 2; 539 sci_schedule_break_timer(port); 540 } else 541 port->break_flag = 0; 542} 543 544static inline int sci_handle_errors(struct uart_port *port) 545{ 546 int copied = 0; 547 unsigned short status = sci_in(port, SCxSR); 548 struct tty_struct *tty = port->info->port.tty; 549 550 if (status & SCxSR_ORER(port)) { 551 /* overrun error */ 552 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 553 copied++; 554 555 dev_notice(port->dev, "overrun error"); 556 } 557 558 if (status & SCxSR_FER(port)) { 559 if (sci_rxd_in(port) == 0) { 560 /* Notify of BREAK */ 561 struct sci_port *sci_port = to_sci_port(port); 562 563 if (!sci_port->break_flag) { 564 sci_port->break_flag = 1; 565 sci_schedule_break_timer(sci_port); 566 567 /* Do sysrq handling. */ 568 if (uart_handle_break(port)) 569 return 0; 570 571 dev_dbg(port->dev, "BREAK detected\n"); 572 573 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 574 copied++; 575 } 576 577 } else { 578 /* frame error */ 579 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 580 copied++; 581 582 dev_notice(port->dev, "frame error\n"); 583 } 584 } 585 586 if (status & SCxSR_PER(port)) { 587 /* parity error */ 588 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 589 copied++; 590 591 dev_notice(port->dev, "parity error"); 592 } 593 594 if (copied) 595 tty_flip_buffer_push(tty); 596 597 return copied; 598} 599 600static inline int sci_handle_fifo_overrun(struct uart_port *port) 601{ 602 struct tty_struct *tty = port->info->port.tty; 603 int copied = 0; 604 605 if (port->type != PORT_SCIF) 606 return 0; 607 608 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { 609 sci_out(port, SCLSR, 0); 610 611 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 612 tty_flip_buffer_push(tty); 613 614 dev_notice(port->dev, "overrun error\n"); 615 copied++; 616 } 617 618 return copied; 619} 620 621static inline int sci_handle_breaks(struct uart_port *port) 622{ 623 int copied = 0; 624 unsigned short status = sci_in(port, SCxSR); 625 struct tty_struct *tty = port->info->port.tty; 626 struct sci_port *s = to_sci_port(port); 627 628 if (uart_handle_break(port)) 629 return 0; 630 631 if (!s->break_flag && status & SCxSR_BRK(port)) { 632#if defined(CONFIG_CPU_SH3) 633 /* Debounce break */ 634 s->break_flag = 1; 635#endif 636 /* Notify of BREAK */ 637 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 638 copied++; 639 640 dev_dbg(port->dev, "BREAK detected\n"); 641 } 642 643 if (copied) 644 tty_flip_buffer_push(tty); 645 646 copied += sci_handle_fifo_overrun(port); 647 648 return copied; 649} 650 651static irqreturn_t sci_rx_interrupt(int irq, void *port) 652{ 653 /* I think sci_receive_chars has to be called irrespective 654 * of whether the I_IXOFF is set, otherwise, how is the interrupt 655 * to be disabled? 656 */ 657 sci_receive_chars(port); 658 659 return IRQ_HANDLED; 660} 661 662static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 663{ 664 struct uart_port *port = ptr; 665 666 spin_lock_irq(&port->lock); 667 sci_transmit_chars(port); 668 spin_unlock_irq(&port->lock); 669 670 return IRQ_HANDLED; 671} 672 673static irqreturn_t sci_er_interrupt(int irq, void *ptr) 674{ 675 struct uart_port *port = ptr; 676 677 /* Handle errors */ 678 if (port->type == PORT_SCI) { 679 if (sci_handle_errors(port)) { 680 /* discard character in rx buffer */ 681 sci_in(port, SCxSR); 682 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 683 } 684 } else { 685 sci_handle_fifo_overrun(port); 686 sci_rx_interrupt(irq, ptr); 687 } 688 689 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 690 691 /* Kick the transmission */ 692 sci_tx_interrupt(irq, ptr); 693 694 return IRQ_HANDLED; 695} 696 697static irqreturn_t sci_br_interrupt(int irq, void *ptr) 698{ 699 struct uart_port *port = ptr; 700 701 /* Handle BREAKs */ 702 sci_handle_breaks(port); 703 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 704 705 return IRQ_HANDLED; 706} 707 708static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 709{ 710 unsigned short ssr_status, scr_status; 711 struct uart_port *port = ptr; 712 irqreturn_t ret = IRQ_NONE; 713 714 ssr_status = sci_in(port, SCxSR); 715 scr_status = sci_in(port, SCSCR); 716 717 /* Tx Interrupt */ 718 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE)) 719 ret = sci_tx_interrupt(irq, ptr); 720 /* Rx Interrupt */ 721 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE)) 722 ret = sci_rx_interrupt(irq, ptr); 723 /* Error Interrupt */ 724 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE)) 725 ret = sci_er_interrupt(irq, ptr); 726 /* Break Interrupt */ 727 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE)) 728 ret = sci_br_interrupt(irq, ptr); 729 730 return ret; 731} 732 733#ifdef CONFIG_HAVE_CLK 734/* 735 * Here we define a transistion notifier so that we can update all of our 736 * ports' baud rate when the peripheral clock changes. 737 */ 738static int sci_notifier(struct notifier_block *self, 739 unsigned long phase, void *p) 740{ 741 struct sh_sci_priv *priv = container_of(self, 742 struct sh_sci_priv, clk_nb); 743 struct sci_port *sci_port; 744 unsigned long flags; 745 746 if ((phase == CPUFREQ_POSTCHANGE) || 747 (phase == CPUFREQ_RESUMECHANGE)) { 748 spin_lock_irqsave(&priv->lock, flags); 749 list_for_each_entry(sci_port, &priv->ports, node) 750 sci_port->port.uartclk = clk_get_rate(sci_port->dclk); 751 752 spin_unlock_irqrestore(&priv->lock, flags); 753 } 754 755 return NOTIFY_OK; 756} 757 758static void sci_clk_enable(struct uart_port *port) 759{ 760 struct sci_port *sci_port = to_sci_port(port); 761 762 clk_enable(sci_port->dclk); 763 sci_port->port.uartclk = clk_get_rate(sci_port->dclk); 764 765 if (sci_port->iclk) 766 clk_enable(sci_port->iclk); 767} 768 769static void sci_clk_disable(struct uart_port *port) 770{ 771 struct sci_port *sci_port = to_sci_port(port); 772 773 if (sci_port->iclk) 774 clk_disable(sci_port->iclk); 775 776 clk_disable(sci_port->dclk); 777} 778#endif 779 780static int sci_request_irq(struct sci_port *port) 781{ 782 int i; 783 irqreturn_t (*handlers[4])(int irq, void *ptr) = { 784 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, 785 sci_br_interrupt, 786 }; 787 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", 788 "SCI Transmit Data Empty", "SCI Break" }; 789 790 if (port->irqs[0] == port->irqs[1]) { 791 if (unlikely(!port->irqs[0])) 792 return -ENODEV; 793 794 if (request_irq(port->irqs[0], sci_mpxed_interrupt, 795 IRQF_DISABLED, "sci", port)) { 796 dev_err(port->port.dev, "Can't allocate IRQ\n"); 797 return -ENODEV; 798 } 799 } else { 800 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 801 if (unlikely(!port->irqs[i])) 802 continue; 803 804 if (request_irq(port->irqs[i], handlers[i], 805 IRQF_DISABLED, desc[i], port)) { 806 dev_err(port->port.dev, "Can't allocate IRQ\n"); 807 return -ENODEV; 808 } 809 } 810 } 811 812 return 0; 813} 814 815static void sci_free_irq(struct sci_port *port) 816{ 817 int i; 818 819 if (port->irqs[0] == port->irqs[1]) 820 free_irq(port->irqs[0], port); 821 else { 822 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { 823 if (!port->irqs[i]) 824 continue; 825 826 free_irq(port->irqs[i], port); 827 } 828 } 829} 830 831static unsigned int sci_tx_empty(struct uart_port *port) 832{ 833 /* Can't detect */ 834 return TIOCSER_TEMT; 835} 836 837static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 838{ 839 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ 840 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ 841 /* If you have signals for DTR and DCD, please implement here. */ 842} 843 844static unsigned int sci_get_mctrl(struct uart_port *port) 845{ 846 /* This routine is used for geting signals of: DTR, DCD, DSR, RI, 847 and CTS/RTS */ 848 849 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; 850} 851 852static void sci_start_tx(struct uart_port *port) 853{ 854 unsigned short ctrl; 855 856 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 857 ctrl = sci_in(port, SCSCR); 858 ctrl |= SCI_CTRL_FLAGS_TIE; 859 sci_out(port, SCSCR, ctrl); 860} 861 862static void sci_stop_tx(struct uart_port *port) 863{ 864 unsigned short ctrl; 865 866 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 867 ctrl = sci_in(port, SCSCR); 868 ctrl &= ~SCI_CTRL_FLAGS_TIE; 869 sci_out(port, SCSCR, ctrl); 870} 871 872static void sci_start_rx(struct uart_port *port, unsigned int tty_start) 873{ 874 unsigned short ctrl; 875 876 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 877 ctrl = sci_in(port, SCSCR); 878 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; 879 sci_out(port, SCSCR, ctrl); 880} 881 882static void sci_stop_rx(struct uart_port *port) 883{ 884 unsigned short ctrl; 885 886 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 887 ctrl = sci_in(port, SCSCR); 888 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 889 sci_out(port, SCSCR, ctrl); 890} 891 892static void sci_enable_ms(struct uart_port *port) 893{ 894 /* Nothing here yet .. */ 895} 896 897static void sci_break_ctl(struct uart_port *port, int break_state) 898{ 899 /* Nothing here yet .. */ 900} 901 902static int sci_startup(struct uart_port *port) 903{ 904 struct sci_port *s = to_sci_port(port); 905 906 if (s->enable) 907 s->enable(port); 908 909 sci_request_irq(s); 910 sci_start_tx(port); 911 sci_start_rx(port, 1); 912 913 return 0; 914} 915 916static void sci_shutdown(struct uart_port *port) 917{ 918 struct sci_port *s = to_sci_port(port); 919 920 sci_stop_rx(port); 921 sci_stop_tx(port); 922 sci_free_irq(s); 923 924 if (s->disable) 925 s->disable(port); 926} 927 928static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 929 struct ktermios *old) 930{ 931 unsigned int status, baud, smr_val; 932 int t = -1; 933 934 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 935 if (likely(baud)) 936 t = SCBRR_VALUE(baud, port->uartclk); 937 938 do { 939 status = sci_in(port, SCxSR); 940 } while (!(status & SCxSR_TEND(port))); 941 942 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 943 944 if (port->type != PORT_SCI) 945 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 946 947 smr_val = sci_in(port, SCSMR) & 3; 948 if ((termios->c_cflag & CSIZE) == CS7) 949 smr_val |= 0x40; 950 if (termios->c_cflag & PARENB) 951 smr_val |= 0x20; 952 if (termios->c_cflag & PARODD) 953 smr_val |= 0x30; 954 if (termios->c_cflag & CSTOPB) 955 smr_val |= 0x08; 956 957 uart_update_timeout(port, termios->c_cflag, baud); 958 959 sci_out(port, SCSMR, smr_val); 960 961 if (t > 0) { 962 if (t >= 256) { 963 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 964 t >>= 2; 965 } else 966 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); 967 968 sci_out(port, SCBRR, t); 969 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 970 } 971 972 sci_init_pins(port, termios->c_cflag); 973 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); 974 975 sci_out(port, SCSCR, SCSCR_INIT(port)); 976 977 if ((termios->c_cflag & CREAD) != 0) 978 sci_start_rx(port, 0); 979} 980 981static const char *sci_type(struct uart_port *port) 982{ 983 switch (port->type) { 984 case PORT_IRDA: 985 return "irda"; 986 case PORT_SCI: 987 return "sci"; 988 case PORT_SCIF: 989 return "scif"; 990 case PORT_SCIFA: 991 return "scifa"; 992 } 993 994 return NULL; 995} 996 997static void sci_release_port(struct uart_port *port) 998{ 999 /* Nothing here yet .. */ 1000} 1001 1002static int sci_request_port(struct uart_port *port) 1003{ 1004 /* Nothing here yet .. */ 1005 return 0; 1006} 1007 1008static void sci_config_port(struct uart_port *port, int flags) 1009{ 1010 struct sci_port *s = to_sci_port(port); 1011 1012 port->type = s->type; 1013 1014 if (port->membase) 1015 return; 1016 1017 if (port->flags & UPF_IOREMAP) { 1018 port->membase = ioremap_nocache(port->mapbase, 0x40); 1019 1020 if (IS_ERR(port->membase)) 1021 dev_err(port->dev, "can't remap port#%d\n", port->line); 1022 } else { 1023 /* 1024 * For the simple (and majority of) cases where we don't 1025 * need to do any remapping, just cast the cookie 1026 * directly. 1027 */ 1028 port->membase = (void __iomem *)port->mapbase; 1029 } 1030} 1031 1032static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1033{ 1034 struct sci_port *s = to_sci_port(port); 1035 1036 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1037 return -EINVAL; 1038 if (ser->baud_base < 2400) 1039 /* No paper tape reader for Mitch.. */ 1040 return -EINVAL; 1041 1042 return 0; 1043} 1044 1045static struct uart_ops sci_uart_ops = { 1046 .tx_empty = sci_tx_empty, 1047 .set_mctrl = sci_set_mctrl, 1048 .get_mctrl = sci_get_mctrl, 1049 .start_tx = sci_start_tx, 1050 .stop_tx = sci_stop_tx, 1051 .stop_rx = sci_stop_rx, 1052 .enable_ms = sci_enable_ms, 1053 .break_ctl = sci_break_ctl, 1054 .startup = sci_startup, 1055 .shutdown = sci_shutdown, 1056 .set_termios = sci_set_termios, 1057 .type = sci_type, 1058 .release_port = sci_release_port, 1059 .request_port = sci_request_port, 1060 .config_port = sci_config_port, 1061 .verify_port = sci_verify_port, 1062#ifdef CONFIG_CONSOLE_POLL 1063 .poll_get_char = sci_poll_get_char, 1064 .poll_put_char = sci_poll_put_char, 1065#endif 1066}; 1067 1068static void __devinit sci_init_single(struct platform_device *dev, 1069 struct sci_port *sci_port, 1070 unsigned int index, 1071 struct plat_sci_port *p) 1072{ 1073 sci_port->port.ops = &sci_uart_ops; 1074 sci_port->port.iotype = UPIO_MEM; 1075 sci_port->port.line = index; 1076 sci_port->port.fifosize = 1; 1077 1078#if defined(__H8300H__) || defined(__H8300S__) 1079#ifdef __H8300S__ 1080 sci_port->enable = h8300_sci_enable; 1081 sci_port->disable = h8300_sci_disable; 1082#endif 1083 sci_port->port.uartclk = CONFIG_CPU_CLOCK; 1084#elif defined(CONFIG_HAVE_CLK) 1085 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL; 1086 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk"); 1087 sci_port->enable = sci_clk_enable; 1088 sci_port->disable = sci_clk_disable; 1089#else 1090#error "Need a valid uartclk" 1091#endif 1092 1093 sci_port->break_timer.data = (unsigned long)sci_port; 1094 sci_port->break_timer.function = sci_break_timer; 1095 init_timer(&sci_port->break_timer); 1096 1097 sci_port->port.mapbase = p->mapbase; 1098 sci_port->port.membase = p->membase; 1099 1100 sci_port->port.irq = p->irqs[SCIx_TXI_IRQ]; 1101 sci_port->port.flags = p->flags; 1102 sci_port->port.dev = &dev->dev; 1103 sci_port->type = sci_port->port.type = p->type; 1104 1105 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); 1106 1107} 1108 1109#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1110static struct tty_driver *serial_console_device(struct console *co, int *index) 1111{ 1112 struct uart_driver *p = &sci_uart_driver; 1113 *index = co->index; 1114 return p->tty_driver; 1115} 1116 1117static void serial_console_putchar(struct uart_port *port, int ch) 1118{ 1119 sci_poll_put_char(port, ch); 1120} 1121 1122/* 1123 * Print a string to the serial port trying not to disturb 1124 * any possible real use of the port... 1125 */ 1126static void serial_console_write(struct console *co, const char *s, 1127 unsigned count) 1128{ 1129 struct uart_port *port = co->data; 1130 struct sci_port *sci_port = to_sci_port(port); 1131 unsigned short bits; 1132 1133 if (sci_port->enable) 1134 sci_port->enable(port); 1135 1136 uart_console_write(port, s, count, serial_console_putchar); 1137 1138 /* wait until fifo is empty and last bit has been transmitted */ 1139 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 1140 while ((sci_in(port, SCxSR) & bits) != bits) 1141 cpu_relax(); 1142 1143 if (sci_port->disable); 1144 sci_port->disable(port); 1145} 1146 1147static int __init serial_console_setup(struct console *co, char *options) 1148{ 1149 struct sci_port *sci_port; 1150 struct uart_port *port; 1151 int baud = 115200; 1152 int bits = 8; 1153 int parity = 'n'; 1154 int flow = 'n'; 1155 int ret; 1156 1157 /* 1158 * Check whether an invalid uart number has been specified, and 1159 * if so, search for the first available port that does have 1160 * console support. 1161 */ 1162 if (co->index >= SCI_NPORTS) 1163 co->index = 0; 1164 1165 sci_port = &sci_ports[co->index]; 1166 port = &sci_port->port; 1167 co->data = port; 1168 1169 /* 1170 * Also need to check port->type, we don't actually have any 1171 * UPIO_PORT ports, but uart_report_port() handily misreports 1172 * it anyways if we don't have a port available by the time this is 1173 * called. 1174 */ 1175 if (!port->type) 1176 return -ENODEV; 1177 1178 sci_config_port(port, 0); 1179 1180 if (sci_port->enable) 1181 sci_port->enable(port); 1182 1183 if (options) 1184 uart_parse_options(options, &baud, &parity, &bits, &flow); 1185 1186 ret = uart_set_options(port, co, baud, parity, bits, flow); 1187#if defined(__H8300H__) || defined(__H8300S__) 1188 /* disable rx interrupt */ 1189 if (ret == 0) 1190 sci_stop_rx(port); 1191#endif 1192 /* TODO: disable clock */ 1193 return ret; 1194} 1195 1196static struct console serial_console = { 1197 .name = "ttySC", 1198 .device = serial_console_device, 1199 .write = serial_console_write, 1200 .setup = serial_console_setup, 1201 .flags = CON_PRINTBUFFER, 1202 .index = -1, 1203}; 1204 1205static int __init sci_console_init(void) 1206{ 1207 register_console(&serial_console); 1208 return 0; 1209} 1210console_initcall(sci_console_init); 1211#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 1212 1213#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 1214#define SCI_CONSOLE (&serial_console) 1215#else 1216#define SCI_CONSOLE 0 1217#endif 1218 1219static char banner[] __initdata = 1220 KERN_INFO "SuperH SCI(F) driver initialized\n"; 1221 1222static struct uart_driver sci_uart_driver = { 1223 .owner = THIS_MODULE, 1224 .driver_name = "sci", 1225 .dev_name = "ttySC", 1226 .major = SCI_MAJOR, 1227 .minor = SCI_MINOR_START, 1228 .nr = SCI_NPORTS, 1229 .cons = SCI_CONSOLE, 1230}; 1231 1232 1233static int sci_remove(struct platform_device *dev) 1234{ 1235 struct sh_sci_priv *priv = platform_get_drvdata(dev); 1236 struct sci_port *p; 1237 unsigned long flags; 1238 1239#ifdef CONFIG_HAVE_CLK 1240 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); 1241#endif 1242 1243 spin_lock_irqsave(&priv->lock, flags); 1244 list_for_each_entry(p, &priv->ports, node) 1245 uart_remove_one_port(&sci_uart_driver, &p->port); 1246 1247 spin_unlock_irqrestore(&priv->lock, flags); 1248 1249 kfree(priv); 1250 return 0; 1251} 1252 1253static int __devinit sci_probe_single(struct platform_device *dev, 1254 unsigned int index, 1255 struct plat_sci_port *p, 1256 struct sci_port *sciport) 1257{ 1258 struct sh_sci_priv *priv = platform_get_drvdata(dev); 1259 unsigned long flags; 1260 int ret; 1261 1262 /* Sanity check */ 1263 if (unlikely(index >= SCI_NPORTS)) { 1264 dev_notice(&dev->dev, "Attempting to register port " 1265 "%d when only %d are available.\n", 1266 index+1, SCI_NPORTS); 1267 dev_notice(&dev->dev, "Consider bumping " 1268 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 1269 return 0; 1270 } 1271 1272 sci_init_single(dev, sciport, index, p); 1273 1274 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 1275 if (ret) 1276 return ret; 1277 1278 INIT_LIST_HEAD(&sciport->node); 1279 1280 spin_lock_irqsave(&priv->lock, flags); 1281 list_add(&sciport->node, &priv->ports); 1282 spin_unlock_irqrestore(&priv->lock, flags); 1283 1284 return 0; 1285} 1286 1287/* 1288 * Register a set of serial devices attached to a platform device. The 1289 * list is terminated with a zero flags entry, which means we expect 1290 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need 1291 * remapping (such as sh64) should also set UPF_IOREMAP. 1292 */ 1293static int __devinit sci_probe(struct platform_device *dev) 1294{ 1295 struct plat_sci_port *p = dev->dev.platform_data; 1296 struct sh_sci_priv *priv; 1297 int i, ret = -EINVAL; 1298 1299 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1300 if (!priv) 1301 return -ENOMEM; 1302 1303 INIT_LIST_HEAD(&priv->ports); 1304 spin_lock_init(&priv->lock); 1305 platform_set_drvdata(dev, priv); 1306 1307#ifdef CONFIG_HAVE_CLK 1308 priv->clk_nb.notifier_call = sci_notifier; 1309 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); 1310#endif 1311 1312 if (dev->id != -1) { 1313 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]); 1314 if (ret) 1315 goto err_unreg; 1316 } else { 1317 for (i = 0; p && p->flags != 0; p++, i++) { 1318 ret = sci_probe_single(dev, i, p, &sci_ports[i]); 1319 if (ret) 1320 goto err_unreg; 1321 } 1322 } 1323 1324#ifdef CONFIG_SH_STANDARD_BIOS 1325 sh_bios_gdb_detach(); 1326#endif 1327 1328 return 0; 1329 1330err_unreg: 1331 sci_remove(dev); 1332 return ret; 1333} 1334 1335static int sci_suspend(struct device *dev) 1336{ 1337 struct sh_sci_priv *priv = dev_get_drvdata(dev); 1338 struct sci_port *p; 1339 unsigned long flags; 1340 1341 spin_lock_irqsave(&priv->lock, flags); 1342 list_for_each_entry(p, &priv->ports, node) 1343 uart_suspend_port(&sci_uart_driver, &p->port); 1344 spin_unlock_irqrestore(&priv->lock, flags); 1345 1346 return 0; 1347} 1348 1349static int sci_resume(struct device *dev) 1350{ 1351 struct sh_sci_priv *priv = dev_get_drvdata(dev); 1352 struct sci_port *p; 1353 unsigned long flags; 1354 1355 spin_lock_irqsave(&priv->lock, flags); 1356 list_for_each_entry(p, &priv->ports, node) 1357 uart_resume_port(&sci_uart_driver, &p->port); 1358 spin_unlock_irqrestore(&priv->lock, flags); 1359 1360 return 0; 1361} 1362 1363static struct dev_pm_ops sci_dev_pm_ops = { 1364 .suspend = sci_suspend, 1365 .resume = sci_resume, 1366}; 1367 1368static struct platform_driver sci_driver = { 1369 .probe = sci_probe, 1370 .remove = __devexit_p(sci_remove), 1371 .driver = { 1372 .name = "sh-sci", 1373 .owner = THIS_MODULE, 1374 .pm = &sci_dev_pm_ops, 1375 }, 1376}; 1377 1378static int __init sci_init(void) 1379{ 1380 int ret; 1381 1382 printk(banner); 1383 1384 ret = uart_register_driver(&sci_uart_driver); 1385 if (likely(ret == 0)) { 1386 ret = platform_driver_register(&sci_driver); 1387 if (unlikely(ret)) 1388 uart_unregister_driver(&sci_uart_driver); 1389 } 1390 1391 return ret; 1392} 1393 1394static void __exit sci_exit(void) 1395{ 1396 platform_driver_unregister(&sci_driver); 1397 uart_unregister_driver(&sci_uart_driver); 1398} 1399 1400module_init(sci_init); 1401module_exit(sci_exit); 1402 1403MODULE_LICENSE("GPL"); 1404MODULE_ALIAS("platform:sh-sci");