Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21#ifndef __DMAR_H__
22#define __DMAR_H__
23
24#include <linux/acpi.h>
25#include <linux/types.h>
26#include <linux/msi.h>
27#include <linux/irqreturn.h>
28
29struct intel_iommu;
30#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
31struct dmar_drhd_unit {
32 struct list_head list; /* list of drhd units */
33 struct acpi_dmar_header *hdr; /* ACPI header */
34 u64 reg_base_addr; /* register base address*/
35 struct pci_dev **devices; /* target device array */
36 int devices_cnt; /* target device count */
37 u16 segment; /* PCI domain */
38 u8 ignored:1; /* ignore drhd */
39 u8 include_all:1;
40 struct intel_iommu *iommu;
41};
42
43extern struct list_head dmar_drhd_units;
44
45#define for_each_drhd_unit(drhd) \
46 list_for_each_entry(drhd, &dmar_drhd_units, list)
47
48#define for_each_active_iommu(i, drhd) \
49 list_for_each_entry(drhd, &dmar_drhd_units, list) \
50 if (i=drhd->iommu, drhd->ignored) {} else
51
52#define for_each_iommu(i, drhd) \
53 list_for_each_entry(drhd, &dmar_drhd_units, list) \
54 if (i=drhd->iommu, 0) {} else
55
56extern int dmar_table_init(void);
57extern int dmar_dev_scope_init(void);
58
59/* Intel IOMMU detection */
60extern void detect_intel_iommu(void);
61extern int enable_drhd_fault_handling(void);
62
63extern int parse_ioapics_under_ir(void);
64extern int alloc_iommu(struct dmar_drhd_unit *);
65#else
66static inline void detect_intel_iommu(void)
67{
68 return;
69}
70
71static inline int dmar_table_init(void)
72{
73 return -ENODEV;
74}
75static inline int enable_drhd_fault_handling(void)
76{
77 return -1;
78}
79#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
80
81struct irte {
82 union {
83 struct {
84 __u64 present : 1,
85 fpd : 1,
86 dst_mode : 1,
87 redir_hint : 1,
88 trigger_mode : 1,
89 dlvry_mode : 3,
90 avail : 4,
91 __reserved_1 : 4,
92 vector : 8,
93 __reserved_2 : 8,
94 dest_id : 32;
95 };
96 __u64 low;
97 };
98
99 union {
100 struct {
101 __u64 sid : 16,
102 sq : 2,
103 svt : 2,
104 __reserved_3 : 44;
105 };
106 __u64 high;
107 };
108};
109#ifdef CONFIG_INTR_REMAP
110extern int intr_remapping_enabled;
111extern int enable_intr_remapping(int);
112extern void disable_intr_remapping(void);
113extern int reenable_intr_remapping(int);
114
115extern int get_irte(int irq, struct irte *entry);
116extern int modify_irte(int irq, struct irte *irte_modified);
117extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
118extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
119 u16 sub_handle);
120extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
121extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
122extern int flush_irte(int irq);
123extern int free_irte(int irq);
124
125extern int irq_remapped(int irq);
126extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
127extern struct intel_iommu *map_ioapic_to_ir(int apic);
128#else
129static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
130{
131 return -1;
132}
133static inline int modify_irte(int irq, struct irte *irte_modified)
134{
135 return -1;
136}
137static inline int free_irte(int irq)
138{
139 return -1;
140}
141static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
142{
143 return -1;
144}
145static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
146 u16 sub_handle)
147{
148 return -1;
149}
150static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
151{
152 return NULL;
153}
154static inline struct intel_iommu *map_ioapic_to_ir(int apic)
155{
156 return NULL;
157}
158#define irq_remapped(irq) (0)
159#define enable_intr_remapping(mode) (-1)
160#define intr_remapping_enabled (0)
161#endif
162
163/* Can't use the common MSI interrupt functions
164 * since DMAR is not a pci device
165 */
166extern void dmar_msi_unmask(unsigned int irq);
167extern void dmar_msi_mask(unsigned int irq);
168extern void dmar_msi_read(int irq, struct msi_msg *msg);
169extern void dmar_msi_write(int irq, struct msi_msg *msg);
170extern int dmar_set_interrupt(struct intel_iommu *iommu);
171extern irqreturn_t dmar_fault(int irq, void *dev_id);
172extern int arch_setup_dmar_msi(unsigned int irq);
173
174#ifdef CONFIG_DMAR
175extern int iommu_detected, no_iommu;
176extern struct list_head dmar_rmrr_units;
177struct dmar_rmrr_unit {
178 struct list_head list; /* list of rmrr units */
179 struct acpi_dmar_header *hdr; /* ACPI header */
180 u64 base_address; /* reserved base address*/
181 u64 end_address; /* reserved end address */
182 struct pci_dev **devices; /* target devices */
183 int devices_cnt; /* target device count */
184};
185
186#define for_each_rmrr_units(rmrr) \
187 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
188/* Intel DMAR initialization functions */
189extern int intel_iommu_init(void);
190#else
191static inline int intel_iommu_init(void)
192{
193#ifdef CONFIG_INTR_REMAP
194 return dmar_dev_scope_init();
195#else
196 return -ENODEV;
197#endif
198}
199#endif /* !CONFIG_DMAR */
200#endif /* __DMAR_H__ */