tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
39#define er32(reg) __er32(hw, E1000_##reg)
40#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41#define e1e_flush() er32(STATUS)
42
43#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45
46#define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48
49enum e1e_registers {
50 E1000_CTRL = 0x00000, /* Device Control - RW */
51 E1000_STATUS = 0x00008, /* Device Status - RO */
52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
53 E1000_EERD = 0x00014, /* EEPROM Read - RW */
54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
55 E1000_FLA = 0x0001C, /* Flash Access - RW */
56 E1000_MDIC = 0x00020, /* MDI Control - RW */
57 E1000_SCTL = 0x00024, /* SerDes Control - RW */
58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
60 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
61 E1000_FCT = 0x00030, /* Flow Control Type - RW */
62 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
63 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
64 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
65 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
68 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
69 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
70 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
71 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
72#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
73 E1000_RCTL = 0x00100, /* Rx Control - RW */
74 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
75 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
76 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
77 E1000_TCTL = 0x00400, /* Tx Control - RW */
78 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
79 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
80 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
81 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
82 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
83 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
84 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
85 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
86 E1000_PBS = 0x01008, /* Packet Buffer Size */
87 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
88 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
89 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
90 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
91 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
92 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
93 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
94 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
95 E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
96 E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
97 E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
98 E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
99 E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
100 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
101 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
102#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
103 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
104
105/* Convenience macros
106 *
107 * Note: "_n" is the queue number of the register to be written to.
108 *
109 * Example usage:
110 * E1000_RDBAL_REG(current_rx_queue)
111 *
112 */
113#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
114 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
115 E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
116 E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
117 E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
118 E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
119 E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
120 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
121 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
122#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
123 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
124 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
125#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
126 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
127 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
128 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
129 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
130 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
131 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
132 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
133 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
134 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
135 E1000_COLC = 0x04028, /* Collision Count - R/clr */
136 E1000_DC = 0x04030, /* Defer Count - R/clr */
137 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
138 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
139 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
140 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
141 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
142 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
143 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
144 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
145 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
146 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
147 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
148 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
149 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
150 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
151 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
152 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
153 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
154 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
155 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
156 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
157 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
158 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
159 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
160 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
161 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
162 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
163 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
164 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
165 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
166 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
167 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
168 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
169 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
170 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
171 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
172 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
173 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
174 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
175 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
176 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
177 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
178 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
179 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
180 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
181 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
182 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
183 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
184 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
185 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
186 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
187 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
188 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
189 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
190 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
191 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
192 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
193 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
194 E1000_RFCTL = 0x05008, /* Receive Filter Control */
195 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
196 E1000_RA = 0x05400, /* Receive Address - RW Array */
197 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
198 E1000_WUC = 0x05800, /* Wakeup Control - RW */
199 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
200 E1000_WUS = 0x05810, /* Wakeup Status - RO */
201 E1000_MANC = 0x05820, /* Management Control - RW */
202 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
203 E1000_HOST_IF = 0x08800, /* Host Interface */
204
205 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
206 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
207 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
208 E1000_GCR = 0x05B00, /* PCI-Ex Control */
209 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
210 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
211 E1000_SWSM = 0x05B50, /* SW Semaphore */
212 E1000_FWSM = 0x05B54, /* FW Semaphore */
213 E1000_HICR = 0x08F00, /* Host Interface Control */
214};
215
216/* RSS registers */
217
218/* IGP01E1000 Specific Registers */
219#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
220#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
221#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
222#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
223#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
224#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
225#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
226#define IGP_PAGE_SHIFT 5
227#define PHY_REG_MASK 0x1F
228
229#define BM_WUC_PAGE 800
230#define BM_WUC_ADDRESS_OPCODE 0x11
231#define BM_WUC_DATA_OPCODE 0x12
232#define BM_WUC_ENABLE_PAGE 769
233#define BM_WUC_ENABLE_REG 17
234#define BM_WUC_ENABLE_BIT (1 << 2)
235#define BM_WUC_HOST_WU_BIT (1 << 4)
236
237#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
238#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
239#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
240
241#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
242#define IGP01E1000_PHY_POLARITY_MASK 0x0078
243
244#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
245#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
246
247#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
248
249#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
250#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
251#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
252
253#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
254
255#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
256#define IGP01E1000_PSSR_MDIX 0x0008
257#define IGP01E1000_PSSR_SPEED_MASK 0xC000
258#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
259
260#define IGP02E1000_PHY_CHANNEL_NUM 4
261#define IGP02E1000_PHY_AGC_A 0x11B1
262#define IGP02E1000_PHY_AGC_B 0x12B1
263#define IGP02E1000_PHY_AGC_C 0x14B1
264#define IGP02E1000_PHY_AGC_D 0x18B1
265
266#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
267#define IGP02E1000_AGC_LENGTH_MASK 0x7F
268#define IGP02E1000_AGC_RANGE 15
269
270/* manage.c */
271#define E1000_VFTA_ENTRY_SHIFT 5
272#define E1000_VFTA_ENTRY_MASK 0x7F
273#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
274
275#define E1000_HICR_EN 0x01 /* Enable bit - RO */
276/* Driver sets this bit when done to put command in RAM */
277#define E1000_HICR_C 0x02
278#define E1000_HICR_FW_RESET_ENABLE 0x40
279#define E1000_HICR_FW_RESET 0x80
280
281#define E1000_FWSM_MODE_MASK 0xE
282#define E1000_FWSM_MODE_SHIFT 1
283
284#define E1000_MNG_IAMT_MODE 0x3
285#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
286#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
287#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
288#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
289#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
290#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
291
292/* nvm.c */
293#define E1000_STM_OPCODE 0xDB00
294
295#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
296#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
297#define E1000_KMRNCTRLSTA_REN 0x00200000
298#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
299#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
300
301#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
302#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
303#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
304#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
305
306/* IFE PHY Extended Status Control */
307#define IFE_PESC_POLARITY_REVERSED 0x0100
308
309/* IFE PHY Special Control */
310#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
311#define IFE_PSC_FORCE_POLARITY 0x0020
312
313/* IFE PHY Special Control and LED Control */
314#define IFE_PSCL_PROBE_MODE 0x0020
315#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
316#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
317
318/* IFE PHY MDIX Control */
319#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
320#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
321#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
322
323#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
324
325#define E1000_DEV_ID_82571EB_COPPER 0x105E
326#define E1000_DEV_ID_82571EB_FIBER 0x105F
327#define E1000_DEV_ID_82571EB_SERDES 0x1060
328#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
329#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
330#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
331#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
332#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
333#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
334#define E1000_DEV_ID_82572EI_COPPER 0x107D
335#define E1000_DEV_ID_82572EI_FIBER 0x107E
336#define E1000_DEV_ID_82572EI_SERDES 0x107F
337#define E1000_DEV_ID_82572EI 0x10B9
338#define E1000_DEV_ID_82573E 0x108B
339#define E1000_DEV_ID_82573E_IAMT 0x108C
340#define E1000_DEV_ID_82573L 0x109A
341#define E1000_DEV_ID_82574L 0x10D3
342#define E1000_DEV_ID_82574LA 0x10F6
343#define E1000_DEV_ID_82583V 0x150C
344
345#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
346#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
347#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
348#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
349
350#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
351#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
352#define E1000_DEV_ID_ICH8_IGP_C 0x104B
353#define E1000_DEV_ID_ICH8_IFE 0x104C
354#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
355#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
356#define E1000_DEV_ID_ICH8_IGP_M 0x104D
357#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
358#define E1000_DEV_ID_ICH9_BM 0x10E5
359#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
360#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
361#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
362#define E1000_DEV_ID_ICH9_IGP_C 0x294C
363#define E1000_DEV_ID_ICH9_IFE 0x10C0
364#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
365#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
366#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
367#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
368#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
369#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
370#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
371
372#define E1000_REVISION_4 4
373
374#define E1000_FUNC_1 1
375
376enum e1000_mac_type {
377 e1000_82571,
378 e1000_82572,
379 e1000_82573,
380 e1000_82574,
381 e1000_82583,
382 e1000_80003es2lan,
383 e1000_ich8lan,
384 e1000_ich9lan,
385 e1000_ich10lan,
386};
387
388enum e1000_media_type {
389 e1000_media_type_unknown = 0,
390 e1000_media_type_copper = 1,
391 e1000_media_type_fiber = 2,
392 e1000_media_type_internal_serdes = 3,
393 e1000_num_media_types
394};
395
396enum e1000_nvm_type {
397 e1000_nvm_unknown = 0,
398 e1000_nvm_none,
399 e1000_nvm_eeprom_spi,
400 e1000_nvm_flash_hw,
401 e1000_nvm_flash_sw
402};
403
404enum e1000_nvm_override {
405 e1000_nvm_override_none = 0,
406 e1000_nvm_override_spi_small,
407 e1000_nvm_override_spi_large
408};
409
410enum e1000_phy_type {
411 e1000_phy_unknown = 0,
412 e1000_phy_none,
413 e1000_phy_m88,
414 e1000_phy_igp,
415 e1000_phy_igp_2,
416 e1000_phy_gg82563,
417 e1000_phy_igp_3,
418 e1000_phy_ife,
419 e1000_phy_bm,
420};
421
422enum e1000_bus_width {
423 e1000_bus_width_unknown = 0,
424 e1000_bus_width_pcie_x1,
425 e1000_bus_width_pcie_x2,
426 e1000_bus_width_pcie_x4 = 4,
427 e1000_bus_width_32,
428 e1000_bus_width_64,
429 e1000_bus_width_reserved
430};
431
432enum e1000_1000t_rx_status {
433 e1000_1000t_rx_status_not_ok = 0,
434 e1000_1000t_rx_status_ok,
435 e1000_1000t_rx_status_undefined = 0xFF
436};
437
438enum e1000_rev_polarity{
439 e1000_rev_polarity_normal = 0,
440 e1000_rev_polarity_reversed,
441 e1000_rev_polarity_undefined = 0xFF
442};
443
444enum e1000_fc_mode {
445 e1000_fc_none = 0,
446 e1000_fc_rx_pause,
447 e1000_fc_tx_pause,
448 e1000_fc_full,
449 e1000_fc_default = 0xFF
450};
451
452enum e1000_ms_type {
453 e1000_ms_hw_default = 0,
454 e1000_ms_force_master,
455 e1000_ms_force_slave,
456 e1000_ms_auto
457};
458
459enum e1000_smart_speed {
460 e1000_smart_speed_default = 0,
461 e1000_smart_speed_on,
462 e1000_smart_speed_off
463};
464
465enum e1000_serdes_link_state {
466 e1000_serdes_link_down = 0,
467 e1000_serdes_link_autoneg_progress,
468 e1000_serdes_link_autoneg_complete,
469 e1000_serdes_link_forced_up
470};
471
472/* Receive Descriptor */
473struct e1000_rx_desc {
474 __le64 buffer_addr; /* Address of the descriptor's data buffer */
475 __le16 length; /* Length of data DMAed into data buffer */
476 __le16 csum; /* Packet checksum */
477 u8 status; /* Descriptor status */
478 u8 errors; /* Descriptor Errors */
479 __le16 special;
480};
481
482/* Receive Descriptor - Extended */
483union e1000_rx_desc_extended {
484 struct {
485 __le64 buffer_addr;
486 __le64 reserved;
487 } read;
488 struct {
489 struct {
490 __le32 mrq; /* Multiple Rx Queues */
491 union {
492 __le32 rss; /* RSS Hash */
493 struct {
494 __le16 ip_id; /* IP id */
495 __le16 csum; /* Packet Checksum */
496 } csum_ip;
497 } hi_dword;
498 } lower;
499 struct {
500 __le32 status_error; /* ext status/error */
501 __le16 length;
502 __le16 vlan; /* VLAN tag */
503 } upper;
504 } wb; /* writeback */
505};
506
507#define MAX_PS_BUFFERS 4
508/* Receive Descriptor - Packet Split */
509union e1000_rx_desc_packet_split {
510 struct {
511 /* one buffer for protocol header(s), three data buffers */
512 __le64 buffer_addr[MAX_PS_BUFFERS];
513 } read;
514 struct {
515 struct {
516 __le32 mrq; /* Multiple Rx Queues */
517 union {
518 __le32 rss; /* RSS Hash */
519 struct {
520 __le16 ip_id; /* IP id */
521 __le16 csum; /* Packet Checksum */
522 } csum_ip;
523 } hi_dword;
524 } lower;
525 struct {
526 __le32 status_error; /* ext status/error */
527 __le16 length0; /* length of buffer 0 */
528 __le16 vlan; /* VLAN tag */
529 } middle;
530 struct {
531 __le16 header_status;
532 __le16 length[3]; /* length of buffers 1-3 */
533 } upper;
534 __le64 reserved;
535 } wb; /* writeback */
536};
537
538/* Transmit Descriptor */
539struct e1000_tx_desc {
540 __le64 buffer_addr; /* Address of the descriptor's data buffer */
541 union {
542 __le32 data;
543 struct {
544 __le16 length; /* Data buffer length */
545 u8 cso; /* Checksum offset */
546 u8 cmd; /* Descriptor control */
547 } flags;
548 } lower;
549 union {
550 __le32 data;
551 struct {
552 u8 status; /* Descriptor status */
553 u8 css; /* Checksum start */
554 __le16 special;
555 } fields;
556 } upper;
557};
558
559/* Offload Context Descriptor */
560struct e1000_context_desc {
561 union {
562 __le32 ip_config;
563 struct {
564 u8 ipcss; /* IP checksum start */
565 u8 ipcso; /* IP checksum offset */
566 __le16 ipcse; /* IP checksum end */
567 } ip_fields;
568 } lower_setup;
569 union {
570 __le32 tcp_config;
571 struct {
572 u8 tucss; /* TCP checksum start */
573 u8 tucso; /* TCP checksum offset */
574 __le16 tucse; /* TCP checksum end */
575 } tcp_fields;
576 } upper_setup;
577 __le32 cmd_and_length;
578 union {
579 __le32 data;
580 struct {
581 u8 status; /* Descriptor status */
582 u8 hdr_len; /* Header length */
583 __le16 mss; /* Maximum segment size */
584 } fields;
585 } tcp_seg_setup;
586};
587
588/* Offload data descriptor */
589struct e1000_data_desc {
590 __le64 buffer_addr; /* Address of the descriptor's buffer address */
591 union {
592 __le32 data;
593 struct {
594 __le16 length; /* Data buffer length */
595 u8 typ_len_ext;
596 u8 cmd;
597 } flags;
598 } lower;
599 union {
600 __le32 data;
601 struct {
602 u8 status; /* Descriptor status */
603 u8 popts; /* Packet Options */
604 __le16 special; /* */
605 } fields;
606 } upper;
607};
608
609/* Statistics counters collected by the MAC */
610struct e1000_hw_stats {
611 u64 crcerrs;
612 u64 algnerrc;
613 u64 symerrs;
614 u64 rxerrc;
615 u64 mpc;
616 u64 scc;
617 u64 ecol;
618 u64 mcc;
619 u64 latecol;
620 u64 colc;
621 u64 dc;
622 u64 tncrs;
623 u64 sec;
624 u64 cexterr;
625 u64 rlec;
626 u64 xonrxc;
627 u64 xontxc;
628 u64 xoffrxc;
629 u64 xofftxc;
630 u64 fcruc;
631 u64 prc64;
632 u64 prc127;
633 u64 prc255;
634 u64 prc511;
635 u64 prc1023;
636 u64 prc1522;
637 u64 gprc;
638 u64 bprc;
639 u64 mprc;
640 u64 gptc;
641 u64 gorc;
642 u64 gotc;
643 u64 rnbc;
644 u64 ruc;
645 u64 rfc;
646 u64 roc;
647 u64 rjc;
648 u64 mgprc;
649 u64 mgpdc;
650 u64 mgptc;
651 u64 tor;
652 u64 tot;
653 u64 tpr;
654 u64 tpt;
655 u64 ptc64;
656 u64 ptc127;
657 u64 ptc255;
658 u64 ptc511;
659 u64 ptc1023;
660 u64 ptc1522;
661 u64 mptc;
662 u64 bptc;
663 u64 tsctc;
664 u64 tsctfc;
665 u64 iac;
666 u64 icrxptc;
667 u64 icrxatc;
668 u64 ictxptc;
669 u64 ictxatc;
670 u64 ictxqec;
671 u64 ictxqmtc;
672 u64 icrxdmtc;
673 u64 icrxoc;
674};
675
676struct e1000_phy_stats {
677 u32 idle_errors;
678 u32 receive_errors;
679};
680
681struct e1000_host_mng_dhcp_cookie {
682 u32 signature;
683 u8 status;
684 u8 reserved0;
685 u16 vlan_id;
686 u32 reserved1;
687 u16 reserved2;
688 u8 reserved3;
689 u8 checksum;
690};
691
692/* Host Interface "Rev 1" */
693struct e1000_host_command_header {
694 u8 command_id;
695 u8 command_length;
696 u8 command_options;
697 u8 checksum;
698};
699
700#define E1000_HI_MAX_DATA_LENGTH 252
701struct e1000_host_command_info {
702 struct e1000_host_command_header command_header;
703 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
704};
705
706/* Host Interface "Rev 2" */
707struct e1000_host_mng_command_header {
708 u8 command_id;
709 u8 checksum;
710 u16 reserved1;
711 u16 reserved2;
712 u16 command_length;
713};
714
715#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
716struct e1000_host_mng_command_info {
717 struct e1000_host_mng_command_header command_header;
718 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
719};
720
721/* Function pointers and static data for the MAC. */
722struct e1000_mac_operations {
723 bool (*check_mng_mode)(struct e1000_hw *);
724 s32 (*check_for_link)(struct e1000_hw *);
725 s32 (*cleanup_led)(struct e1000_hw *);
726 void (*clear_hw_cntrs)(struct e1000_hw *);
727 s32 (*get_bus_info)(struct e1000_hw *);
728 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
729 s32 (*led_on)(struct e1000_hw *);
730 s32 (*led_off)(struct e1000_hw *);
731 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
732 s32 (*reset_hw)(struct e1000_hw *);
733 s32 (*init_hw)(struct e1000_hw *);
734 s32 (*setup_link)(struct e1000_hw *);
735 s32 (*setup_physical_interface)(struct e1000_hw *);
736};
737
738/* Function pointers for the PHY. */
739struct e1000_phy_operations {
740 s32 (*acquire_phy)(struct e1000_hw *);
741 s32 (*check_reset_block)(struct e1000_hw *);
742 s32 (*commit_phy)(struct e1000_hw *);
743 s32 (*force_speed_duplex)(struct e1000_hw *);
744 s32 (*get_cfg_done)(struct e1000_hw *hw);
745 s32 (*get_cable_length)(struct e1000_hw *);
746 s32 (*get_phy_info)(struct e1000_hw *);
747 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
748 void (*release_phy)(struct e1000_hw *);
749 s32 (*reset_phy)(struct e1000_hw *);
750 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
751 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
752 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
753 s32 (*cfg_on_link_up)(struct e1000_hw *);
754};
755
756/* Function pointers for the NVM. */
757struct e1000_nvm_operations {
758 s32 (*acquire_nvm)(struct e1000_hw *);
759 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
760 void (*release_nvm)(struct e1000_hw *);
761 s32 (*update_nvm)(struct e1000_hw *);
762 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
763 s32 (*validate_nvm)(struct e1000_hw *);
764 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
765};
766
767struct e1000_mac_info {
768 struct e1000_mac_operations ops;
769
770 u8 addr[6];
771 u8 perm_addr[6];
772
773 enum e1000_mac_type type;
774
775 u32 collision_delta;
776 u32 ledctl_default;
777 u32 ledctl_mode1;
778 u32 ledctl_mode2;
779 u32 mc_filter_type;
780 u32 tx_packet_delta;
781 u32 txcw;
782
783 u16 current_ifs_val;
784 u16 ifs_max_val;
785 u16 ifs_min_val;
786 u16 ifs_ratio;
787 u16 ifs_step_size;
788 u16 mta_reg_count;
789 u16 rar_entry_count;
790
791 u8 forced_speed_duplex;
792
793 bool arc_subsystem_valid;
794 bool autoneg;
795 bool autoneg_failed;
796 bool get_link_status;
797 bool in_ifs_mode;
798 bool serdes_has_link;
799 bool tx_pkt_filtering;
800 enum e1000_serdes_link_state serdes_link_state;
801};
802
803struct e1000_phy_info {
804 struct e1000_phy_operations ops;
805
806 enum e1000_phy_type type;
807
808 enum e1000_1000t_rx_status local_rx;
809 enum e1000_1000t_rx_status remote_rx;
810 enum e1000_ms_type ms_type;
811 enum e1000_ms_type original_ms_type;
812 enum e1000_rev_polarity cable_polarity;
813 enum e1000_smart_speed smart_speed;
814
815 u32 addr;
816 u32 id;
817 u32 reset_delay_us; /* in usec */
818 u32 revision;
819
820 enum e1000_media_type media_type;
821
822 u16 autoneg_advertised;
823 u16 autoneg_mask;
824 u16 cable_length;
825 u16 max_cable_length;
826 u16 min_cable_length;
827
828 u8 mdix;
829
830 bool disable_polarity_correction;
831 bool is_mdix;
832 bool polarity_correction;
833 bool speed_downgraded;
834 bool autoneg_wait_to_complete;
835};
836
837struct e1000_nvm_info {
838 struct e1000_nvm_operations ops;
839
840 enum e1000_nvm_type type;
841 enum e1000_nvm_override override;
842
843 u32 flash_bank_size;
844 u32 flash_base_addr;
845
846 u16 word_size;
847 u16 delay_usec;
848 u16 address_bits;
849 u16 opcode_bits;
850 u16 page_size;
851};
852
853struct e1000_bus_info {
854 enum e1000_bus_width width;
855
856 u16 func;
857};
858
859struct e1000_fc_info {
860 u32 high_water; /* Flow control high-water mark */
861 u32 low_water; /* Flow control low-water mark */
862 u16 pause_time; /* Flow control pause timer */
863 bool send_xon; /* Flow control send XON */
864 bool strict_ieee; /* Strict IEEE mode */
865 enum e1000_fc_mode current_mode; /* FC mode in effect */
866 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
867};
868
869struct e1000_dev_spec_82571 {
870 bool laa_is_present;
871 bool alt_mac_addr_is_present;
872};
873
874struct e1000_shadow_ram {
875 u16 value;
876 bool modified;
877};
878
879#define E1000_ICH8_SHADOW_RAM_WORDS 2048
880
881struct e1000_dev_spec_ich8lan {
882 bool kmrn_lock_loss_workaround_enabled;
883 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
884};
885
886struct e1000_hw {
887 struct e1000_adapter *adapter;
888
889 u8 __iomem *hw_addr;
890 u8 __iomem *flash_address;
891
892 struct e1000_mac_info mac;
893 struct e1000_fc_info fc;
894 struct e1000_phy_info phy;
895 struct e1000_nvm_info nvm;
896 struct e1000_bus_info bus;
897 struct e1000_host_mng_dhcp_cookie mng_cookie;
898
899 union {
900 struct e1000_dev_spec_82571 e82571;
901 struct e1000_dev_spec_ich8lan ich8lan;
902 } dev_spec;
903};
904
905#ifdef DEBUG
906#define hw_dbg(hw, format, arg...) \
907 printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
908#else
909static inline int __attribute__ ((format (printf, 2, 3)))
910hw_dbg(struct e1000_hw *hw, const char *format, ...)
911{
912 return 0;
913}
914#endif
915
916#endif