tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * VIA IDE driver for Linux. Supported southbridges:
3 *
4 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
5 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
6 * vt8235, vt8237, vt8237a
7 *
8 * Copyright (c) 2000-2002 Vojtech Pavlik
9 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
10 *
11 * Based on the work of:
12 * Michel Aubry
13 * Jeff Garzik
14 * Andre Hedrick
15 *
16 * Documentation:
17 * Obsolete device documentation publically available from via.com.tw
18 * Current device documentation available under NDA only
19 */
20
21/*
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License version 2 as published by
24 * the Free Software Foundation.
25 */
26
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/ide.h>
32#include <linux/dmi.h>
33
34#ifdef CONFIG_PPC_CHRP
35#include <asm/processor.h>
36#endif
37
38#define DRV_NAME "via82cxxx"
39
40#define VIA_IDE_ENABLE 0x40
41#define VIA_IDE_CONFIG 0x41
42#define VIA_FIFO_CONFIG 0x43
43#define VIA_MISC_1 0x44
44#define VIA_MISC_2 0x45
45#define VIA_MISC_3 0x46
46#define VIA_DRIVE_TIMING 0x48
47#define VIA_8BIT_TIMING 0x4e
48#define VIA_ADDRESS_SETUP 0x4c
49#define VIA_UDMA_TIMING 0x50
50
51#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
52#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
53#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
54#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
55#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
56#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
57
58/*
59 * VIA SouthBridge chips.
60 */
61
62static struct via_isa_bridge {
63 char *name;
64 u16 id;
65 u8 rev_min;
66 u8 rev_max;
67 u8 udma_mask;
68 u8 flags;
69} via_isa_bridges[] = {
70 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
71 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
72 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
73 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
74 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
76 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
77 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
78 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
79 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
80 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
81 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
82 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
83 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
84 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
85 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
86 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
87 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
88 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
89 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
90 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
91 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
92 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
93 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
94 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
95 { NULL }
96};
97
98static unsigned int via_clock;
99static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
100
101struct via82cxxx_dev
102{
103 struct via_isa_bridge *via_config;
104 unsigned int via_80w;
105};
106
107/**
108 * via_set_speed - write timing registers
109 * @dev: PCI device
110 * @dn: device
111 * @timing: IDE timing data to use
112 *
113 * via_set_speed writes timing values to the chipset registers
114 */
115
116static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
117{
118 struct pci_dev *dev = to_pci_dev(hwif->dev);
119 struct ide_host *host = pci_get_drvdata(dev);
120 struct via82cxxx_dev *vdev = host->host_priv;
121 u8 t;
122
123 if (~vdev->via_config->flags & VIA_BAD_AST) {
124 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
125 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
126 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
127 }
128
129 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
130 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
131
132 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
133 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
134
135 switch (vdev->via_config->udma_mask) {
136 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
137 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
138 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
139 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
140 default: return;
141 }
142
143 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
144}
145
146/**
147 * via_set_drive - configure transfer mode
148 * @drive: Drive to set up
149 * @speed: desired speed
150 *
151 * via_set_drive() computes timing values configures the chipset to
152 * a desired transfer mode. It also can be called by upper layers.
153 */
154
155static void via_set_drive(ide_drive_t *drive, const u8 speed)
156{
157 ide_hwif_t *hwif = drive->hwif;
158 ide_drive_t *peer = ide_get_pair_dev(drive);
159 struct pci_dev *dev = to_pci_dev(hwif->dev);
160 struct ide_host *host = pci_get_drvdata(dev);
161 struct via82cxxx_dev *vdev = host->host_priv;
162 struct ide_timing t, p;
163 unsigned int T, UT;
164
165 T = 1000000000 / via_clock;
166
167 switch (vdev->via_config->udma_mask) {
168 case ATA_UDMA2: UT = T; break;
169 case ATA_UDMA4: UT = T/2; break;
170 case ATA_UDMA5: UT = T/3; break;
171 case ATA_UDMA6: UT = T/4; break;
172 default: UT = T;
173 }
174
175 ide_timing_compute(drive, speed, &t, T, UT);
176
177 if (peer) {
178 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
179 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
180 }
181
182 via_set_speed(hwif, drive->dn, &t);
183}
184
185/**
186 * via_set_pio_mode - set host controller for PIO mode
187 * @drive: drive
188 * @pio: PIO mode number
189 *
190 * A callback from the upper layers for PIO-only tuning.
191 */
192
193static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
194{
195 via_set_drive(drive, XFER_PIO_0 + pio);
196}
197
198static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
199{
200 struct via_isa_bridge *via_config;
201
202 for (via_config = via_isa_bridges; via_config->id; via_config++)
203 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
204 !!(via_config->flags & VIA_BAD_ID),
205 via_config->id, NULL))) {
206
207 if ((*isa)->revision >= via_config->rev_min &&
208 (*isa)->revision <= via_config->rev_max)
209 break;
210 pci_dev_put(*isa);
211 }
212
213 return via_config;
214}
215
216/*
217 * Check and handle 80-wire cable presence
218 */
219static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
220{
221 int i;
222
223 switch (vdev->via_config->udma_mask) {
224 case ATA_UDMA4:
225 for (i = 24; i >= 0; i -= 8)
226 if (((u >> (i & 16)) & 8) &&
227 ((u >> i) & 0x20) &&
228 (((u >> i) & 7) < 2)) {
229 /*
230 * 2x PCI clock and
231 * UDMA w/ < 3T/cycle
232 */
233 vdev->via_80w |= (1 << (1 - (i >> 4)));
234 }
235 break;
236
237 case ATA_UDMA5:
238 for (i = 24; i >= 0; i -= 8)
239 if (((u >> i) & 0x10) ||
240 (((u >> i) & 0x20) &&
241 (((u >> i) & 7) < 4))) {
242 /* BIOS 80-wire bit or
243 * UDMA w/ < 60ns/cycle
244 */
245 vdev->via_80w |= (1 << (1 - (i >> 4)));
246 }
247 break;
248
249 case ATA_UDMA6:
250 for (i = 24; i >= 0; i -= 8)
251 if (((u >> i) & 0x10) ||
252 (((u >> i) & 0x20) &&
253 (((u >> i) & 7) < 6))) {
254 /* BIOS 80-wire bit or
255 * UDMA w/ < 60ns/cycle
256 */
257 vdev->via_80w |= (1 << (1 - (i >> 4)));
258 }
259 break;
260 }
261}
262
263/**
264 * init_chipset_via82cxxx - initialization handler
265 * @dev: PCI device
266 *
267 * The initialization callback. Here we determine the IDE chip type
268 * and initialize its drive independent registers.
269 */
270
271static int init_chipset_via82cxxx(struct pci_dev *dev)
272{
273 struct ide_host *host = pci_get_drvdata(dev);
274 struct via82cxxx_dev *vdev = host->host_priv;
275 struct via_isa_bridge *via_config = vdev->via_config;
276 u8 t, v;
277 u32 u;
278
279 /*
280 * Detect cable and configure Clk66
281 */
282 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
283
284 via_cable_detect(vdev, u);
285
286 if (via_config->udma_mask == ATA_UDMA4) {
287 /* Enable Clk66 */
288 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
289 } else if (via_config->flags & VIA_BAD_CLK66) {
290 /* Would cause trouble on 596a and 686 */
291 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
292 }
293
294 /*
295 * Check whether interfaces are enabled.
296 */
297
298 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
299
300 /*
301 * Set up FIFO sizes and thresholds.
302 */
303
304 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
305
306 /* Disable PREQ# till DDACK# */
307 if (via_config->flags & VIA_BAD_PREQ) {
308 /* Would crash on 586b rev 41 */
309 t &= 0x7f;
310 }
311
312 /* Fix FIFO split between channels */
313 if (via_config->flags & VIA_SET_FIFO) {
314 t &= (t & 0x9f);
315 switch (v & 3) {
316 case 2: t |= 0x00; break; /* 16 on primary */
317 case 1: t |= 0x60; break; /* 16 on secondary */
318 case 3: t |= 0x20; break; /* 8 pri 8 sec */
319 }
320 }
321
322 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
323
324 return 0;
325}
326
327/*
328 * Cable special cases
329 */
330
331static const struct dmi_system_id cable_dmi_table[] = {
332 {
333 .ident = "Acer Ferrari 3400",
334 .matches = {
335 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
336 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
337 },
338 },
339 { }
340};
341
342static int via_cable_override(struct pci_dev *pdev)
343{
344 /* Systems by DMI */
345 if (dmi_check_system(cable_dmi_table))
346 return 1;
347
348 /* Arima W730-K8/Targa Visionary 811/... */
349 if (pdev->subsystem_vendor == 0x161F &&
350 pdev->subsystem_device == 0x2032)
351 return 1;
352
353 return 0;
354}
355
356static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
357{
358 struct pci_dev *pdev = to_pci_dev(hwif->dev);
359 struct ide_host *host = pci_get_drvdata(pdev);
360 struct via82cxxx_dev *vdev = host->host_priv;
361
362 if (via_cable_override(pdev))
363 return ATA_CBL_PATA40_SHORT;
364
365 if ((vdev->via_80w >> hwif->channel) & 1)
366 return ATA_CBL_PATA80;
367 else
368 return ATA_CBL_PATA40;
369}
370
371static const struct ide_port_ops via_port_ops = {
372 .set_pio_mode = via_set_pio_mode,
373 .set_dma_mode = via_set_drive,
374 .cable_detect = via82cxxx_cable_detect,
375};
376
377static const struct ide_port_info via82cxxx_chipset __devinitdata = {
378 .name = DRV_NAME,
379 .init_chipset = init_chipset_via82cxxx,
380 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
381 .port_ops = &via_port_ops,
382 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
383 IDE_HFLAG_POST_SET_MODE |
384 IDE_HFLAG_IO_32BIT,
385 .pio_mask = ATA_PIO5,
386 .swdma_mask = ATA_SWDMA2,
387 .mwdma_mask = ATA_MWDMA2,
388};
389
390static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
391{
392 struct pci_dev *isa = NULL;
393 struct via_isa_bridge *via_config;
394 struct via82cxxx_dev *vdev;
395 int rc;
396 u8 idx = id->driver_data;
397 struct ide_port_info d;
398
399 d = via82cxxx_chipset;
400
401 /*
402 * Find the ISA bridge and check we know what it is.
403 */
404 via_config = via_config_find(&isa);
405 if (!via_config->id) {
406 printk(KERN_WARNING DRV_NAME " %s: unknown chipset, skipping\n",
407 pci_name(dev));
408 return -ENODEV;
409 }
410
411 /*
412 * Print the boot message.
413 */
414 printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
415 pci_name(dev), via_config->name, isa->revision,
416 via_config->udma_mask ? "U" : "MW",
417 via_dma[via_config->udma_mask ?
418 (fls(via_config->udma_mask) - 1) : 0]);
419
420 pci_dev_put(isa);
421
422 /*
423 * Determine system bus clock.
424 */
425 via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
426
427 switch (via_clock) {
428 case 33000: via_clock = 33333; break;
429 case 37000: via_clock = 37500; break;
430 case 41000: via_clock = 41666; break;
431 }
432
433 if (via_clock < 20000 || via_clock > 50000) {
434 printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
435 "impossible (%d), using 33 MHz instead.\n", via_clock);
436 via_clock = 33333;
437 }
438
439 if (idx == 0)
440 d.host_flags |= IDE_HFLAG_NO_AUTODMA;
441 else
442 d.enablebits[1].reg = d.enablebits[0].reg = 0;
443
444 if ((via_config->flags & VIA_NO_UNMASK) == 0)
445 d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
446
447 d.udma_mask = via_config->udma_mask;
448
449 vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
450 if (!vdev) {
451 printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
452 pci_name(dev));
453 return -ENOMEM;
454 }
455
456 vdev->via_config = via_config;
457
458 rc = ide_pci_init_one(dev, &d, vdev);
459 if (rc)
460 kfree(vdev);
461
462 return rc;
463}
464
465static void __devexit via_remove(struct pci_dev *dev)
466{
467 struct ide_host *host = pci_get_drvdata(dev);
468 struct via82cxxx_dev *vdev = host->host_priv;
469
470 ide_pci_remove(dev);
471 kfree(vdev);
472}
473
474static const struct pci_device_id via_pci_tbl[] = {
475 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
476 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
477 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
478 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), 0 },
479 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
480 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
481 { 0, },
482};
483MODULE_DEVICE_TABLE(pci, via_pci_tbl);
484
485static struct pci_driver via_pci_driver = {
486 .name = "VIA_IDE",
487 .id_table = via_pci_tbl,
488 .probe = via_init_one,
489 .remove = __devexit_p(via_remove),
490 .suspend = ide_pci_suspend,
491 .resume = ide_pci_resume,
492};
493
494static int __init via_ide_init(void)
495{
496 return ide_pci_register_driver(&via_pci_driver);
497}
498
499static void __exit via_ide_exit(void)
500{
501 pci_unregister_driver(&via_pci_driver);
502}
503
504module_init(via_ide_init);
505module_exit(via_ide_exit);
506
507MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
508MODULE_DESCRIPTION("PCI driver module for VIA IDE");
509MODULE_LICENSE("GPL");