tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* via_irq.c
2 *
3 * Copyright 2004 BEAM Ltd.
4 * Copyright 2002 Tungsten Graphics, Inc.
5 * Copyright 2005 Thomas Hellstrom.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
23 * DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Terry Barnaby <terry1@beam.ltd.uk>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 * Thomas Hellstrom <unichrome@shipmail.org>
32 *
33 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
34 * interrupt, as well as an infrastructure to handle other interrupts of the chip.
35 * The refresh rate is also calculated for video playback sync purposes.
36 */
37
38#include "drmP.h"
39#include "drm.h"
40#include "via_drm.h"
41#include "via_drv.h"
42
43#define VIA_REG_INTERRUPT 0x200
44
45/* VIA_REG_INTERRUPT */
46#define VIA_IRQ_GLOBAL (1 << 31)
47#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
48#define VIA_IRQ_VBLANK_PENDING (1 << 3)
49#define VIA_IRQ_HQV0_ENABLE (1 << 11)
50#define VIA_IRQ_HQV1_ENABLE (1 << 25)
51#define VIA_IRQ_HQV0_PENDING (1 << 9)
52#define VIA_IRQ_HQV1_PENDING (1 << 10)
53#define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
54#define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
55#define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
56#define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
57#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
58#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
59#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
60#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
61
62
63/*
64 * Device-specific IRQs go here. This type might need to be extended with
65 * the register if there are multiple IRQ control registers.
66 * Currently we activate the HQV interrupts of Unichrome Pro group A.
67 */
68
69static maskarray_t via_pro_group_a_irqs[] = {
70 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
71 0x00000000 },
72 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
73 0x00000000 },
74 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
75 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
76 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
77 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
78};
79static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
80static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
81
82static maskarray_t via_unichrome_irqs[] = {
83 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
84 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
85 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
86 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
87};
88static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
89static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
90
91
92static unsigned time_diff(struct timeval *now, struct timeval *then)
93{
94 return (now->tv_usec >= then->tv_usec) ?
95 now->tv_usec - then->tv_usec :
96 1000000 - (then->tv_usec - now->tv_usec);
97}
98
99u32 via_get_vblank_counter(struct drm_device *dev, int crtc)
100{
101 drm_via_private_t *dev_priv = dev->dev_private;
102 if (crtc != 0)
103 return 0;
104
105 return atomic_read(&dev_priv->vbl_received);
106}
107
108irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
109{
110 struct drm_device *dev = (struct drm_device *) arg;
111 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
112 u32 status;
113 int handled = 0;
114 struct timeval cur_vblank;
115 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
116 int i;
117
118 status = VIA_READ(VIA_REG_INTERRUPT);
119 if (status & VIA_IRQ_VBLANK_PENDING) {
120 atomic_inc(&dev_priv->vbl_received);
121 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
122 do_gettimeofday(&cur_vblank);
123 if (dev_priv->last_vblank_valid) {
124 dev_priv->usec_per_vblank =
125 time_diff(&cur_vblank,
126 &dev_priv->last_vblank) >> 4;
127 }
128 dev_priv->last_vblank = cur_vblank;
129 dev_priv->last_vblank_valid = 1;
130 }
131 if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
132 DRM_DEBUG("US per vblank is: %u\n",
133 dev_priv->usec_per_vblank);
134 }
135 drm_handle_vblank(dev, 0);
136 handled = 1;
137 }
138
139 for (i = 0; i < dev_priv->num_irqs; ++i) {
140 if (status & cur_irq->pending_mask) {
141 atomic_inc(&cur_irq->irq_received);
142 DRM_WAKEUP(&cur_irq->irq_queue);
143 handled = 1;
144 if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
145 via_dmablit_handler(dev, 0, 1);
146 } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {
147 via_dmablit_handler(dev, 1, 1);
148 }
149 }
150 cur_irq++;
151 }
152
153 /* Acknowlege interrupts */
154 VIA_WRITE(VIA_REG_INTERRUPT, status);
155
156
157 if (handled)
158 return IRQ_HANDLED;
159 else
160 return IRQ_NONE;
161}
162
163static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
164{
165 u32 status;
166
167 if (dev_priv) {
168 /* Acknowlege interrupts */
169 status = VIA_READ(VIA_REG_INTERRUPT);
170 VIA_WRITE(VIA_REG_INTERRUPT, status |
171 dev_priv->irq_pending_mask);
172 }
173}
174
175int via_enable_vblank(struct drm_device *dev, int crtc)
176{
177 drm_via_private_t *dev_priv = dev->dev_private;
178 u32 status;
179
180 if (crtc != 0) {
181 DRM_ERROR("%s: bad crtc %d\n", __func__, crtc);
182 return -EINVAL;
183 }
184
185 status = VIA_READ(VIA_REG_INTERRUPT);
186 VIA_WRITE(VIA_REG_INTERRUPT, status & VIA_IRQ_VBLANK_ENABLE);
187
188 VIA_WRITE8(0x83d4, 0x11);
189 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
190
191 return 0;
192}
193
194void via_disable_vblank(struct drm_device *dev, int crtc)
195{
196 drm_via_private_t *dev_priv = dev->dev_private;
197
198 VIA_WRITE8(0x83d4, 0x11);
199 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
200
201 if (crtc != 0)
202 DRM_ERROR("%s: bad crtc %d\n", __func__, crtc);
203}
204
205static int
206via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,
207 unsigned int *sequence)
208{
209 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
210 unsigned int cur_irq_sequence;
211 drm_via_irq_t *cur_irq;
212 int ret = 0;
213 maskarray_t *masks;
214 int real_irq;
215
216 DRM_DEBUG("\n");
217
218 if (!dev_priv) {
219 DRM_ERROR("called with no initialization\n");
220 return -EINVAL;
221 }
222
223 if (irq >= drm_via_irq_num) {
224 DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
225 return -EINVAL;
226 }
227
228 real_irq = dev_priv->irq_map[irq];
229
230 if (real_irq < 0) {
231 DRM_ERROR("Video IRQ %d not available on this hardware.\n",
232 irq);
233 return -EINVAL;
234 }
235
236 masks = dev_priv->irq_masks;
237 cur_irq = dev_priv->via_irqs + real_irq;
238
239 if (masks[real_irq][2] && !force_sequence) {
240 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
241 ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
242 masks[irq][4]));
243 cur_irq_sequence = atomic_read(&cur_irq->irq_received);
244 } else {
245 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
246 (((cur_irq_sequence =
247 atomic_read(&cur_irq->irq_received)) -
248 *sequence) <= (1 << 23)));
249 }
250 *sequence = cur_irq_sequence;
251 return ret;
252}
253
254
255/*
256 * drm_dma.h hooks
257 */
258
259void via_driver_irq_preinstall(struct drm_device * dev)
260{
261 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
262 u32 status;
263 drm_via_irq_t *cur_irq;
264 int i;
265
266 DRM_DEBUG("dev_priv: %p\n", dev_priv);
267 if (dev_priv) {
268 cur_irq = dev_priv->via_irqs;
269
270 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
271 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
272
273 if (dev_priv->chipset == VIA_PRO_GROUP_A ||
274 dev_priv->chipset == VIA_DX9_0) {
275 dev_priv->irq_masks = via_pro_group_a_irqs;
276 dev_priv->num_irqs = via_num_pro_group_a;
277 dev_priv->irq_map = via_irqmap_pro_group_a;
278 } else {
279 dev_priv->irq_masks = via_unichrome_irqs;
280 dev_priv->num_irqs = via_num_unichrome;
281 dev_priv->irq_map = via_irqmap_unichrome;
282 }
283
284 for (i = 0; i < dev_priv->num_irqs; ++i) {
285 atomic_set(&cur_irq->irq_received, 0);
286 cur_irq->enable_mask = dev_priv->irq_masks[i][0];
287 cur_irq->pending_mask = dev_priv->irq_masks[i][1];
288 DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
289 dev_priv->irq_enable_mask |= cur_irq->enable_mask;
290 dev_priv->irq_pending_mask |= cur_irq->pending_mask;
291 cur_irq++;
292
293 DRM_DEBUG("Initializing IRQ %d\n", i);
294 }
295
296 dev_priv->last_vblank_valid = 0;
297
298 /* Clear VSync interrupt regs */
299 status = VIA_READ(VIA_REG_INTERRUPT);
300 VIA_WRITE(VIA_REG_INTERRUPT, status &
301 ~(dev_priv->irq_enable_mask));
302
303 /* Clear bits if they're already high */
304 viadrv_acknowledge_irqs(dev_priv);
305 }
306}
307
308int via_driver_irq_postinstall(struct drm_device *dev)
309{
310 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
311 u32 status;
312
313 DRM_DEBUG("via_driver_irq_postinstall\n");
314 if (!dev_priv)
315 return -EINVAL;
316
317 status = VIA_READ(VIA_REG_INTERRUPT);
318 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
319 | dev_priv->irq_enable_mask);
320
321 /* Some magic, oh for some data sheets ! */
322 VIA_WRITE8(0x83d4, 0x11);
323 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
324
325 return 0;
326}
327
328void via_driver_irq_uninstall(struct drm_device * dev)
329{
330 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
331 u32 status;
332
333 DRM_DEBUG("\n");
334 if (dev_priv) {
335
336 /* Some more magic, oh for some data sheets ! */
337
338 VIA_WRITE8(0x83d4, 0x11);
339 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
340
341 status = VIA_READ(VIA_REG_INTERRUPT);
342 VIA_WRITE(VIA_REG_INTERRUPT, status &
343 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
344 }
345}
346
347int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
348{
349 drm_via_irqwait_t *irqwait = data;
350 struct timeval now;
351 int ret = 0;
352 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
353 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
354 int force_sequence;
355
356 if (irqwait->request.irq >= dev_priv->num_irqs) {
357 DRM_ERROR("Trying to wait on unknown irq %d\n",
358 irqwait->request.irq);
359 return -EINVAL;
360 }
361
362 cur_irq += irqwait->request.irq;
363
364 switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
365 case VIA_IRQ_RELATIVE:
366 irqwait->request.sequence +=
367 atomic_read(&cur_irq->irq_received);
368 irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
369 case VIA_IRQ_ABSOLUTE:
370 break;
371 default:
372 return -EINVAL;
373 }
374
375 if (irqwait->request.type & VIA_IRQ_SIGNAL) {
376 DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
377 return -EINVAL;
378 }
379
380 force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
381
382 ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
383 &irqwait->request.sequence);
384 do_gettimeofday(&now);
385 irqwait->reply.tval_sec = now.tv_sec;
386 irqwait->reply.tval_usec = now.tv_usec;
387
388 return ret;
389}