Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
6
7#include <linux/kernel.h>
8#include <linux/irqflags.h>
9
10#include <asm/hw_irq.h>
11
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * *mb() variants without smp_ prefix must order all types of memory
27 * operations with one another. sync is the only instruction sufficient
28 * to do this.
29 *
30 * For the smp_ barriers, ordering is for cacheable memory operations
31 * only. We have to use the sync instruction for smp_mb(), since lwsync
32 * doesn't order loads with respect to previous stores. Lwsync can be
33 * used for smp_rmb() and smp_wmb().
34 *
35 * However, on CPUs that don't support lwsync, lwsync actually maps to a
36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
37 */
38#define mb() __asm__ __volatile__ ("sync" : : : "memory")
39#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
40#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
41#define read_barrier_depends() do { } while(0)
42
43#define set_mb(var, value) do { var = value; mb(); } while (0)
44
45#ifdef __KERNEL__
46#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
47#ifdef CONFIG_SMP
48
49#ifdef __SUBARCH_HAS_LWSYNC
50# define SMPWMB LWSYNC
51#else
52# define SMPWMB eieio
53#endif
54
55#define smp_mb() mb()
56#define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
57#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
58#define smp_read_barrier_depends() read_barrier_depends()
59#else
60#define smp_mb() barrier()
61#define smp_rmb() barrier()
62#define smp_wmb() barrier()
63#define smp_read_barrier_depends() do { } while(0)
64#endif /* CONFIG_SMP */
65
66/*
67 * This is a barrier which prevents following instructions from being
68 * started until the value of the argument x is known. For example, if
69 * x is a variable loaded from memory, this prevents following
70 * instructions from being executed until the load has been performed.
71 */
72#define data_barrier(x) \
73 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
74
75struct task_struct;
76struct pt_regs;
77
78#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
79
80extern int (*__debugger)(struct pt_regs *regs);
81extern int (*__debugger_ipi)(struct pt_regs *regs);
82extern int (*__debugger_bpt)(struct pt_regs *regs);
83extern int (*__debugger_sstep)(struct pt_regs *regs);
84extern int (*__debugger_iabr_match)(struct pt_regs *regs);
85extern int (*__debugger_dabr_match)(struct pt_regs *regs);
86extern int (*__debugger_fault_handler)(struct pt_regs *regs);
87
88#define DEBUGGER_BOILERPLATE(__NAME) \
89static inline int __NAME(struct pt_regs *regs) \
90{ \
91 if (unlikely(__ ## __NAME)) \
92 return __ ## __NAME(regs); \
93 return 0; \
94}
95
96DEBUGGER_BOILERPLATE(debugger)
97DEBUGGER_BOILERPLATE(debugger_ipi)
98DEBUGGER_BOILERPLATE(debugger_bpt)
99DEBUGGER_BOILERPLATE(debugger_sstep)
100DEBUGGER_BOILERPLATE(debugger_iabr_match)
101DEBUGGER_BOILERPLATE(debugger_dabr_match)
102DEBUGGER_BOILERPLATE(debugger_fault_handler)
103
104#else
105static inline int debugger(struct pt_regs *regs) { return 0; }
106static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
107static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
108static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
109static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
110static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
111static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
112#endif
113
114extern int set_dabr(unsigned long dabr);
115extern void do_dabr(struct pt_regs *regs, unsigned long address,
116 unsigned long error_code);
117extern void print_backtrace(unsigned long *);
118extern void show_regs(struct pt_regs * regs);
119extern void flush_instruction_cache(void);
120extern void hard_reset_now(void);
121extern void poweroff_now(void);
122
123#ifdef CONFIG_6xx
124extern long _get_L2CR(void);
125extern long _get_L3CR(void);
126extern void _set_L2CR(unsigned long);
127extern void _set_L3CR(unsigned long);
128#else
129#define _get_L2CR() 0L
130#define _get_L3CR() 0L
131#define _set_L2CR(val) do { } while(0)
132#define _set_L3CR(val) do { } while(0)
133#endif
134
135extern void via_cuda_init(void);
136extern void read_rtc_time(void);
137extern void pmac_find_display(void);
138extern void giveup_fpu(struct task_struct *);
139extern void disable_kernel_fp(void);
140extern void enable_kernel_fp(void);
141extern void flush_fp_to_thread(struct task_struct *);
142extern void enable_kernel_altivec(void);
143extern void giveup_altivec(struct task_struct *);
144extern void load_up_altivec(struct task_struct *);
145extern int emulate_altivec(struct pt_regs *);
146extern void __giveup_vsx(struct task_struct *);
147extern void giveup_vsx(struct task_struct *);
148extern void enable_kernel_spe(void);
149extern void giveup_spe(struct task_struct *);
150extern void load_up_spe(struct task_struct *);
151extern int fix_alignment(struct pt_regs *);
152extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
153extern void cvt_df(double *from, float *to, struct thread_struct *thread);
154
155#ifndef CONFIG_SMP
156extern void discard_lazy_cpu_state(void);
157#else
158static inline void discard_lazy_cpu_state(void)
159{
160}
161#endif
162
163#ifdef CONFIG_ALTIVEC
164extern void flush_altivec_to_thread(struct task_struct *);
165#else
166static inline void flush_altivec_to_thread(struct task_struct *t)
167{
168}
169#endif
170
171#ifdef CONFIG_VSX
172extern void flush_vsx_to_thread(struct task_struct *);
173#else
174static inline void flush_vsx_to_thread(struct task_struct *t)
175{
176}
177#endif
178
179#ifdef CONFIG_SPE
180extern void flush_spe_to_thread(struct task_struct *);
181#else
182static inline void flush_spe_to_thread(struct task_struct *t)
183{
184}
185#endif
186
187extern int call_rtas(const char *, int, int, unsigned long *, ...);
188extern void cacheable_memzero(void *p, unsigned int nb);
189extern void *cacheable_memcpy(void *, const void *, unsigned int);
190extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
191extern void bad_page_fault(struct pt_regs *, unsigned long, int);
192extern int die(const char *, struct pt_regs *, long);
193extern void _exception(int, struct pt_regs *, int, unsigned long);
194extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
195
196#ifdef CONFIG_BOOKE_WDT
197extern u32 booke_wdt_enabled;
198extern u32 booke_wdt_period;
199#endif /* CONFIG_BOOKE_WDT */
200
201struct device_node;
202extern void note_scsi_host(struct device_node *, void *);
203
204extern struct task_struct *__switch_to(struct task_struct *,
205 struct task_struct *);
206#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
207
208struct thread_struct;
209extern struct task_struct *_switch(struct thread_struct *prev,
210 struct thread_struct *next);
211
212extern unsigned int rtas_data;
213extern int mem_init_done; /* set on boot once kmalloc can be called */
214extern int init_bootmem_done; /* set on !NUMA once bootmem is available */
215extern phys_addr_t memory_limit;
216extern unsigned long klimit;
217
218extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
219extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
220
221extern int powersave_nap; /* set if nap mode can be used in idle loop */
222
223/*
224 * Atomic exchange
225 *
226 * Changes the memory location '*ptr' to be val and returns
227 * the previous value stored there.
228 */
229static __always_inline unsigned long
230__xchg_u32(volatile void *p, unsigned long val)
231{
232 unsigned long prev;
233
234 __asm__ __volatile__(
235 LWSYNC_ON_SMP
236"1: lwarx %0,0,%2 \n"
237 PPC405_ERR77(0,%2)
238" stwcx. %3,0,%2 \n\
239 bne- 1b"
240 ISYNC_ON_SMP
241 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
242 : "r" (p), "r" (val)
243 : "cc", "memory");
244
245 return prev;
246}
247
248/*
249 * Atomic exchange
250 *
251 * Changes the memory location '*ptr' to be val and returns
252 * the previous value stored there.
253 */
254static __always_inline unsigned long
255__xchg_u32_local(volatile void *p, unsigned long val)
256{
257 unsigned long prev;
258
259 __asm__ __volatile__(
260"1: lwarx %0,0,%2 \n"
261 PPC405_ERR77(0,%2)
262" stwcx. %3,0,%2 \n\
263 bne- 1b"
264 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
265 : "r" (p), "r" (val)
266 : "cc", "memory");
267
268 return prev;
269}
270
271#ifdef CONFIG_PPC64
272static __always_inline unsigned long
273__xchg_u64(volatile void *p, unsigned long val)
274{
275 unsigned long prev;
276
277 __asm__ __volatile__(
278 LWSYNC_ON_SMP
279"1: ldarx %0,0,%2 \n"
280 PPC405_ERR77(0,%2)
281" stdcx. %3,0,%2 \n\
282 bne- 1b"
283 ISYNC_ON_SMP
284 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
285 : "r" (p), "r" (val)
286 : "cc", "memory");
287
288 return prev;
289}
290
291static __always_inline unsigned long
292__xchg_u64_local(volatile void *p, unsigned long val)
293{
294 unsigned long prev;
295
296 __asm__ __volatile__(
297"1: ldarx %0,0,%2 \n"
298 PPC405_ERR77(0,%2)
299" stdcx. %3,0,%2 \n\
300 bne- 1b"
301 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
302 : "r" (p), "r" (val)
303 : "cc", "memory");
304
305 return prev;
306}
307#endif
308
309/*
310 * This function doesn't exist, so you'll get a linker error
311 * if something tries to do an invalid xchg().
312 */
313extern void __xchg_called_with_bad_pointer(void);
314
315static __always_inline unsigned long
316__xchg(volatile void *ptr, unsigned long x, unsigned int size)
317{
318 switch (size) {
319 case 4:
320 return __xchg_u32(ptr, x);
321#ifdef CONFIG_PPC64
322 case 8:
323 return __xchg_u64(ptr, x);
324#endif
325 }
326 __xchg_called_with_bad_pointer();
327 return x;
328}
329
330static __always_inline unsigned long
331__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
332{
333 switch (size) {
334 case 4:
335 return __xchg_u32_local(ptr, x);
336#ifdef CONFIG_PPC64
337 case 8:
338 return __xchg_u64_local(ptr, x);
339#endif
340 }
341 __xchg_called_with_bad_pointer();
342 return x;
343}
344#define xchg(ptr,x) \
345 ({ \
346 __typeof__(*(ptr)) _x_ = (x); \
347 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
348 })
349
350#define xchg_local(ptr,x) \
351 ({ \
352 __typeof__(*(ptr)) _x_ = (x); \
353 (__typeof__(*(ptr))) __xchg_local((ptr), \
354 (unsigned long)_x_, sizeof(*(ptr))); \
355 })
356
357/*
358 * Compare and exchange - if *p == old, set it to new,
359 * and return the old value of *p.
360 */
361#define __HAVE_ARCH_CMPXCHG 1
362
363static __always_inline unsigned long
364__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
365{
366 unsigned int prev;
367
368 __asm__ __volatile__ (
369 LWSYNC_ON_SMP
370"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
371 cmpw 0,%0,%3\n\
372 bne- 2f\n"
373 PPC405_ERR77(0,%2)
374" stwcx. %4,0,%2\n\
375 bne- 1b"
376 ISYNC_ON_SMP
377 "\n\
3782:"
379 : "=&r" (prev), "+m" (*p)
380 : "r" (p), "r" (old), "r" (new)
381 : "cc", "memory");
382
383 return prev;
384}
385
386static __always_inline unsigned long
387__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
388 unsigned long new)
389{
390 unsigned int prev;
391
392 __asm__ __volatile__ (
393"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
394 cmpw 0,%0,%3\n\
395 bne- 2f\n"
396 PPC405_ERR77(0,%2)
397" stwcx. %4,0,%2\n\
398 bne- 1b"
399 "\n\
4002:"
401 : "=&r" (prev), "+m" (*p)
402 : "r" (p), "r" (old), "r" (new)
403 : "cc", "memory");
404
405 return prev;
406}
407
408#ifdef CONFIG_PPC64
409static __always_inline unsigned long
410__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
411{
412 unsigned long prev;
413
414 __asm__ __volatile__ (
415 LWSYNC_ON_SMP
416"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
417 cmpd 0,%0,%3\n\
418 bne- 2f\n\
419 stdcx. %4,0,%2\n\
420 bne- 1b"
421 ISYNC_ON_SMP
422 "\n\
4232:"
424 : "=&r" (prev), "+m" (*p)
425 : "r" (p), "r" (old), "r" (new)
426 : "cc", "memory");
427
428 return prev;
429}
430
431static __always_inline unsigned long
432__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
433 unsigned long new)
434{
435 unsigned long prev;
436
437 __asm__ __volatile__ (
438"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
439 cmpd 0,%0,%3\n\
440 bne- 2f\n\
441 stdcx. %4,0,%2\n\
442 bne- 1b"
443 "\n\
4442:"
445 : "=&r" (prev), "+m" (*p)
446 : "r" (p), "r" (old), "r" (new)
447 : "cc", "memory");
448
449 return prev;
450}
451#endif
452
453/* This function doesn't exist, so you'll get a linker error
454 if something tries to do an invalid cmpxchg(). */
455extern void __cmpxchg_called_with_bad_pointer(void);
456
457static __always_inline unsigned long
458__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
459 unsigned int size)
460{
461 switch (size) {
462 case 4:
463 return __cmpxchg_u32(ptr, old, new);
464#ifdef CONFIG_PPC64
465 case 8:
466 return __cmpxchg_u64(ptr, old, new);
467#endif
468 }
469 __cmpxchg_called_with_bad_pointer();
470 return old;
471}
472
473static __always_inline unsigned long
474__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
475 unsigned int size)
476{
477 switch (size) {
478 case 4:
479 return __cmpxchg_u32_local(ptr, old, new);
480#ifdef CONFIG_PPC64
481 case 8:
482 return __cmpxchg_u64_local(ptr, old, new);
483#endif
484 }
485 __cmpxchg_called_with_bad_pointer();
486 return old;
487}
488
489#define cmpxchg(ptr, o, n) \
490 ({ \
491 __typeof__(*(ptr)) _o_ = (o); \
492 __typeof__(*(ptr)) _n_ = (n); \
493 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
494 (unsigned long)_n_, sizeof(*(ptr))); \
495 })
496
497
498#define cmpxchg_local(ptr, o, n) \
499 ({ \
500 __typeof__(*(ptr)) _o_ = (o); \
501 __typeof__(*(ptr)) _n_ = (n); \
502 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
503 (unsigned long)_n_, sizeof(*(ptr))); \
504 })
505
506#ifdef CONFIG_PPC64
507/*
508 * We handle most unaligned accesses in hardware. On the other hand
509 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
510 * powers of 2 writes until it reaches sufficient alignment).
511 *
512 * Based on this we disable the IP header alignment in network drivers.
513 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
514 * cacheline alignment of buffers.
515 */
516#define NET_IP_ALIGN 0
517#define NET_SKB_PAD L1_CACHE_BYTES
518
519#define cmpxchg64(ptr, o, n) \
520 ({ \
521 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
522 cmpxchg((ptr), (o), (n)); \
523 })
524#define cmpxchg64_local(ptr, o, n) \
525 ({ \
526 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
527 cmpxchg_local((ptr), (o), (n)); \
528 })
529#else
530#include <asm-generic/cmpxchg-local.h>
531#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
532#endif
533
534extern unsigned long arch_align_stack(unsigned long sp);
535
536/* Used in very early kernel initialization. */
537extern unsigned long reloc_offset(void);
538extern unsigned long add_reloc_offset(unsigned long);
539extern void reloc_got2(unsigned long);
540
541#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
542
543#ifdef CONFIG_VIRT_CPU_ACCOUNTING
544extern void account_system_vtime(struct task_struct *);
545#endif
546
547extern struct dentry *powerpc_debugfs_root;
548
549#endif /* __KERNEL__ */
550#endif /* _ASM_POWERPC_SYSTEM_H */