Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
at v2.6.30-rc7 1845 lines 49 kB view raw
1/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ 2/* 3 Copyright (c) 2001, 2002 by D-Link Corporation 4 Written by Edward Peng.<edward_peng@dlink.com.tw> 5 Created 03-May-2001, base on Linux' sundance.c. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11*/ 12 13#define DRV_NAME "DL2000/TC902x-based linux driver" 14#define DRV_VERSION "v1.19" 15#define DRV_RELDATE "2007/08/12" 16#include "dl2k.h" 17#include <linux/dma-mapping.h> 18 19static char version[] __devinitdata = 20 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n"; 21#define MAX_UNITS 8 22static int mtu[MAX_UNITS]; 23static int vlan[MAX_UNITS]; 24static int jumbo[MAX_UNITS]; 25static char *media[MAX_UNITS]; 26static int tx_flow=-1; 27static int rx_flow=-1; 28static int copy_thresh; 29static int rx_coalesce=10; /* Rx frame count each interrupt */ 30static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */ 31static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */ 32 33 34MODULE_AUTHOR ("Edward Peng"); 35MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter"); 36MODULE_LICENSE("GPL"); 37module_param_array(mtu, int, NULL, 0); 38module_param_array(media, charp, NULL, 0); 39module_param_array(vlan, int, NULL, 0); 40module_param_array(jumbo, int, NULL, 0); 41module_param(tx_flow, int, 0); 42module_param(rx_flow, int, 0); 43module_param(copy_thresh, int, 0); 44module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */ 45module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */ 46module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */ 47 48 49/* Enable the default interrupts */ 50#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \ 51 UpdateStats | LinkEvent) 52#define EnableInt() \ 53writew(DEFAULT_INTR, ioaddr + IntEnable) 54 55static const int max_intrloop = 50; 56static const int multicast_filter_limit = 0x40; 57 58static int rio_open (struct net_device *dev); 59static void rio_timer (unsigned long data); 60static void rio_tx_timeout (struct net_device *dev); 61static void alloc_list (struct net_device *dev); 62static int start_xmit (struct sk_buff *skb, struct net_device *dev); 63static irqreturn_t rio_interrupt (int irq, void *dev_instance); 64static void rio_free_tx (struct net_device *dev, int irq); 65static void tx_error (struct net_device *dev, int tx_status); 66static int receive_packet (struct net_device *dev); 67static void rio_error (struct net_device *dev, int int_status); 68static int change_mtu (struct net_device *dev, int new_mtu); 69static void set_multicast (struct net_device *dev); 70static struct net_device_stats *get_stats (struct net_device *dev); 71static int clear_stats (struct net_device *dev); 72static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 73static int rio_close (struct net_device *dev); 74static int find_miiphy (struct net_device *dev); 75static int parse_eeprom (struct net_device *dev); 76static int read_eeprom (long ioaddr, int eep_addr); 77static int mii_wait_link (struct net_device *dev, int wait); 78static int mii_set_media (struct net_device *dev); 79static int mii_get_media (struct net_device *dev); 80static int mii_set_media_pcs (struct net_device *dev); 81static int mii_get_media_pcs (struct net_device *dev); 82static int mii_read (struct net_device *dev, int phy_addr, int reg_num); 83static int mii_write (struct net_device *dev, int phy_addr, int reg_num, 84 u16 data); 85 86static const struct ethtool_ops ethtool_ops; 87 88static const struct net_device_ops netdev_ops = { 89 .ndo_open = rio_open, 90 .ndo_start_xmit = start_xmit, 91 .ndo_stop = rio_close, 92 .ndo_get_stats = get_stats, 93 .ndo_validate_addr = eth_validate_addr, 94 .ndo_set_mac_address = eth_mac_addr, 95 .ndo_set_multicast_list = set_multicast, 96 .ndo_do_ioctl = rio_ioctl, 97 .ndo_tx_timeout = rio_tx_timeout, 98 .ndo_change_mtu = change_mtu, 99}; 100 101static int __devinit 102rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) 103{ 104 struct net_device *dev; 105 struct netdev_private *np; 106 static int card_idx; 107 int chip_idx = ent->driver_data; 108 int err, irq; 109 long ioaddr; 110 static int version_printed; 111 void *ring_space; 112 dma_addr_t ring_dma; 113 114 if (!version_printed++) 115 printk ("%s", version); 116 117 err = pci_enable_device (pdev); 118 if (err) 119 return err; 120 121 irq = pdev->irq; 122 err = pci_request_regions (pdev, "dl2k"); 123 if (err) 124 goto err_out_disable; 125 126 pci_set_master (pdev); 127 dev = alloc_etherdev (sizeof (*np)); 128 if (!dev) { 129 err = -ENOMEM; 130 goto err_out_res; 131 } 132 SET_NETDEV_DEV(dev, &pdev->dev); 133 134#ifdef MEM_MAPPING 135 ioaddr = pci_resource_start (pdev, 1); 136 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE); 137 if (!ioaddr) { 138 err = -ENOMEM; 139 goto err_out_dev; 140 } 141#else 142 ioaddr = pci_resource_start (pdev, 0); 143#endif 144 dev->base_addr = ioaddr; 145 dev->irq = irq; 146 np = netdev_priv(dev); 147 np->chip_id = chip_idx; 148 np->pdev = pdev; 149 spin_lock_init (&np->tx_lock); 150 spin_lock_init (&np->rx_lock); 151 152 /* Parse manual configuration */ 153 np->an_enable = 1; 154 np->tx_coalesce = 1; 155 if (card_idx < MAX_UNITS) { 156 if (media[card_idx] != NULL) { 157 np->an_enable = 0; 158 if (strcmp (media[card_idx], "auto") == 0 || 159 strcmp (media[card_idx], "autosense") == 0 || 160 strcmp (media[card_idx], "0") == 0 ) { 161 np->an_enable = 2; 162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 || 163 strcmp (media[card_idx], "4") == 0) { 164 np->speed = 100; 165 np->full_duplex = 1; 166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 167 || strcmp (media[card_idx], "3") == 0) { 168 np->speed = 100; 169 np->full_duplex = 0; 170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || 171 strcmp (media[card_idx], "2") == 0) { 172 np->speed = 10; 173 np->full_duplex = 1; 174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || 175 strcmp (media[card_idx], "1") == 0) { 176 np->speed = 10; 177 np->full_duplex = 0; 178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 || 179 strcmp (media[card_idx], "6") == 0) { 180 np->speed=1000; 181 np->full_duplex=1; 182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 || 183 strcmp (media[card_idx], "5") == 0) { 184 np->speed = 1000; 185 np->full_duplex = 0; 186 } else { 187 np->an_enable = 1; 188 } 189 } 190 if (jumbo[card_idx] != 0) { 191 np->jumbo = 1; 192 dev->mtu = MAX_JUMBO; 193 } else { 194 np->jumbo = 0; 195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE) 196 dev->mtu = mtu[card_idx]; 197 } 198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ? 199 vlan[card_idx] : 0; 200 if (rx_coalesce > 0 && rx_timeout > 0) { 201 np->rx_coalesce = rx_coalesce; 202 np->rx_timeout = rx_timeout; 203 np->coalesce = 1; 204 } 205 np->tx_flow = (tx_flow == 0) ? 0 : 1; 206 np->rx_flow = (rx_flow == 0) ? 0 : 1; 207 208 if (tx_coalesce < 1) 209 tx_coalesce = 1; 210 else if (tx_coalesce > TX_RING_SIZE-1) 211 tx_coalesce = TX_RING_SIZE - 1; 212 } 213 dev->netdev_ops = &netdev_ops; 214 dev->watchdog_timeo = TX_TIMEOUT; 215 SET_ETHTOOL_OPS(dev, &ethtool_ops); 216#if 0 217 dev->features = NETIF_F_IP_CSUM; 218#endif 219 pci_set_drvdata (pdev, dev); 220 221 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma); 222 if (!ring_space) 223 goto err_out_iounmap; 224 np->tx_ring = (struct netdev_desc *) ring_space; 225 np->tx_ring_dma = ring_dma; 226 227 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma); 228 if (!ring_space) 229 goto err_out_unmap_tx; 230 np->rx_ring = (struct netdev_desc *) ring_space; 231 np->rx_ring_dma = ring_dma; 232 233 /* Parse eeprom data */ 234 parse_eeprom (dev); 235 236 /* Find PHY address */ 237 err = find_miiphy (dev); 238 if (err) 239 goto err_out_unmap_rx; 240 241 /* Fiber device? */ 242 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0; 243 np->link_status = 0; 244 /* Set media and reset PHY */ 245 if (np->phy_media) { 246 /* default Auto-Negotiation for fiber deivices */ 247 if (np->an_enable == 2) { 248 np->an_enable = 1; 249 } 250 mii_set_media_pcs (dev); 251 } else { 252 /* Auto-Negotiation is mandatory for 1000BASE-T, 253 IEEE 802.3ab Annex 28D page 14 */ 254 if (np->speed == 1000) 255 np->an_enable = 1; 256 mii_set_media (dev); 257 } 258 259 err = register_netdev (dev); 260 if (err) 261 goto err_out_unmap_rx; 262 263 card_idx++; 264 265 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n", 266 dev->name, np->name, dev->dev_addr, irq); 267 if (tx_coalesce > 1) 268 printk(KERN_INFO "tx_coalesce:\t%d packets\n", 269 tx_coalesce); 270 if (np->coalesce) 271 printk(KERN_INFO "rx_coalesce:\t%d packets\n" 272 KERN_INFO "rx_timeout: \t%d ns\n", 273 np->rx_coalesce, np->rx_timeout*640); 274 if (np->vlan) 275 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan); 276 return 0; 277 278 err_out_unmap_rx: 279 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); 280 err_out_unmap_tx: 281 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); 282 err_out_iounmap: 283#ifdef MEM_MAPPING 284 iounmap ((void *) ioaddr); 285 286 err_out_dev: 287#endif 288 free_netdev (dev); 289 290 err_out_res: 291 pci_release_regions (pdev); 292 293 err_out_disable: 294 pci_disable_device (pdev); 295 return err; 296} 297 298static int 299find_miiphy (struct net_device *dev) 300{ 301 int i, phy_found = 0; 302 struct netdev_private *np; 303 long ioaddr; 304 np = netdev_priv(dev); 305 ioaddr = dev->base_addr; 306 np->phy_addr = 1; 307 308 for (i = 31; i >= 0; i--) { 309 int mii_status = mii_read (dev, i, 1); 310 if (mii_status != 0xffff && mii_status != 0x0000) { 311 np->phy_addr = i; 312 phy_found++; 313 } 314 } 315 if (!phy_found) { 316 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name); 317 return -ENODEV; 318 } 319 return 0; 320} 321 322static int 323parse_eeprom (struct net_device *dev) 324{ 325 int i, j; 326 long ioaddr = dev->base_addr; 327 u8 sromdata[256]; 328 u8 *psib; 329 u32 crc; 330 PSROM_t psrom = (PSROM_t) sromdata; 331 struct netdev_private *np = netdev_priv(dev); 332 333 int cid, next; 334 335#ifdef MEM_MAPPING 336 ioaddr = pci_resource_start (np->pdev, 0); 337#endif 338 /* Read eeprom */ 339 for (i = 0; i < 128; i++) { 340 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i)); 341 } 342#ifdef MEM_MAPPING 343 ioaddr = dev->base_addr; 344#endif 345 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */ 346 /* Check CRC */ 347 crc = ~ether_crc_le (256 - 4, sromdata); 348 if (psrom->crc != crc) { 349 printk (KERN_ERR "%s: EEPROM data CRC error.\n", 350 dev->name); 351 return -1; 352 } 353 } 354 355 /* Set MAC address */ 356 for (i = 0; i < 6; i++) 357 dev->dev_addr[i] = psrom->mac_addr[i]; 358 359 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) { 360 return 0; 361 } 362 363 /* Parse Software Information Block */ 364 i = 0x30; 365 psib = (u8 *) sromdata; 366 do { 367 cid = psib[i++]; 368 next = psib[i++]; 369 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) { 370 printk (KERN_ERR "Cell data error\n"); 371 return -1; 372 } 373 switch (cid) { 374 case 0: /* Format version */ 375 break; 376 case 1: /* End of cell */ 377 return 0; 378 case 2: /* Duplex Polarity */ 379 np->duplex_polarity = psib[i]; 380 writeb (readb (ioaddr + PhyCtrl) | psib[i], 381 ioaddr + PhyCtrl); 382 break; 383 case 3: /* Wake Polarity */ 384 np->wake_polarity = psib[i]; 385 break; 386 case 9: /* Adapter description */ 387 j = (next - i > 255) ? 255 : next - i; 388 memcpy (np->name, &(psib[i]), j); 389 break; 390 case 4: 391 case 5: 392 case 6: 393 case 7: 394 case 8: /* Reversed */ 395 break; 396 default: /* Unknown cell */ 397 return -1; 398 } 399 i = next; 400 } while (1); 401 402 return 0; 403} 404 405static int 406rio_open (struct net_device *dev) 407{ 408 struct netdev_private *np = netdev_priv(dev); 409 long ioaddr = dev->base_addr; 410 int i; 411 u16 macctrl; 412 413 i = request_irq (dev->irq, &rio_interrupt, IRQF_SHARED, dev->name, dev); 414 if (i) 415 return i; 416 417 /* Reset all logic functions */ 418 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset, 419 ioaddr + ASICCtrl + 2); 420 mdelay(10); 421 422 /* DebugCtrl bit 4, 5, 9 must set */ 423 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl); 424 425 /* Jumbo frame */ 426 if (np->jumbo != 0) 427 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize); 428 429 alloc_list (dev); 430 431 /* Get station address */ 432 for (i = 0; i < 6; i++) 433 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i); 434 435 set_multicast (dev); 436 if (np->coalesce) { 437 writel (np->rx_coalesce | np->rx_timeout << 16, 438 ioaddr + RxDMAIntCtrl); 439 } 440 /* Set RIO to poll every N*320nsec. */ 441 writeb (0x20, ioaddr + RxDMAPollPeriod); 442 writeb (0xff, ioaddr + TxDMAPollPeriod); 443 writeb (0x30, ioaddr + RxDMABurstThresh); 444 writeb (0x30, ioaddr + RxDMAUrgentThresh); 445 writel (0x0007ffff, ioaddr + RmonStatMask); 446 /* clear statistics */ 447 clear_stats (dev); 448 449 /* VLAN supported */ 450 if (np->vlan) { 451 /* priority field in RxDMAIntCtrl */ 452 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10, 453 ioaddr + RxDMAIntCtrl); 454 /* VLANId */ 455 writew (np->vlan, ioaddr + VLANId); 456 /* Length/Type should be 0x8100 */ 457 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag); 458 /* Enable AutoVLANuntagging, but disable AutoVLANtagging. 459 VLAN information tagged by TFC' VID, CFI fields. */ 460 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging, 461 ioaddr + MACCtrl); 462 } 463 464 init_timer (&np->timer); 465 np->timer.expires = jiffies + 1*HZ; 466 np->timer.data = (unsigned long) dev; 467 np->timer.function = &rio_timer; 468 add_timer (&np->timer); 469 470 /* Start Tx/Rx */ 471 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable, 472 ioaddr + MACCtrl); 473 474 macctrl = 0; 475 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 476 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 477 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0; 478 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0; 479 writew(macctrl, ioaddr + MACCtrl); 480 481 netif_start_queue (dev); 482 483 /* Enable default interrupts */ 484 EnableInt (); 485 return 0; 486} 487 488static void 489rio_timer (unsigned long data) 490{ 491 struct net_device *dev = (struct net_device *)data; 492 struct netdev_private *np = netdev_priv(dev); 493 unsigned int entry; 494 int next_tick = 1*HZ; 495 unsigned long flags; 496 497 spin_lock_irqsave(&np->rx_lock, flags); 498 /* Recover rx ring exhausted error */ 499 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) { 500 printk(KERN_INFO "Try to recover rx ring exhausted...\n"); 501 /* Re-allocate skbuffs to fill the descriptor ring */ 502 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) { 503 struct sk_buff *skb; 504 entry = np->old_rx % RX_RING_SIZE; 505 /* Dropped packets don't need to re-allocate */ 506 if (np->rx_skbuff[entry] == NULL) { 507 skb = netdev_alloc_skb (dev, np->rx_buf_sz); 508 if (skb == NULL) { 509 np->rx_ring[entry].fraginfo = 0; 510 printk (KERN_INFO 511 "%s: Still unable to re-allocate Rx skbuff.#%d\n", 512 dev->name, entry); 513 break; 514 } 515 np->rx_skbuff[entry] = skb; 516 /* 16 byte align the IP header */ 517 skb_reserve (skb, 2); 518 np->rx_ring[entry].fraginfo = 519 cpu_to_le64 (pci_map_single 520 (np->pdev, skb->data, np->rx_buf_sz, 521 PCI_DMA_FROMDEVICE)); 522 } 523 np->rx_ring[entry].fraginfo |= 524 cpu_to_le64((u64)np->rx_buf_sz << 48); 525 np->rx_ring[entry].status = 0; 526 } /* end for */ 527 } /* end if */ 528 spin_unlock_irqrestore (&np->rx_lock, flags); 529 np->timer.expires = jiffies + next_tick; 530 add_timer(&np->timer); 531} 532 533static void 534rio_tx_timeout (struct net_device *dev) 535{ 536 long ioaddr = dev->base_addr; 537 538 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n", 539 dev->name, readl (ioaddr + TxStatus)); 540 rio_free_tx(dev, 0); 541 dev->if_port = 0; 542 dev->trans_start = jiffies; 543} 544 545 /* allocate and initialize Tx and Rx descriptors */ 546static void 547alloc_list (struct net_device *dev) 548{ 549 struct netdev_private *np = netdev_priv(dev); 550 int i; 551 552 np->cur_rx = np->cur_tx = 0; 553 np->old_rx = np->old_tx = 0; 554 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32); 555 556 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */ 557 for (i = 0; i < TX_RING_SIZE; i++) { 558 np->tx_skbuff[i] = NULL; 559 np->tx_ring[i].status = cpu_to_le64 (TFDDone); 560 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma + 561 ((i+1)%TX_RING_SIZE) * 562 sizeof (struct netdev_desc)); 563 } 564 565 /* Initialize Rx descriptors */ 566 for (i = 0; i < RX_RING_SIZE; i++) { 567 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma + 568 ((i + 1) % RX_RING_SIZE) * 569 sizeof (struct netdev_desc)); 570 np->rx_ring[i].status = 0; 571 np->rx_ring[i].fraginfo = 0; 572 np->rx_skbuff[i] = NULL; 573 } 574 575 /* Allocate the rx buffers */ 576 for (i = 0; i < RX_RING_SIZE; i++) { 577 /* Allocated fixed size of skbuff */ 578 struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz); 579 np->rx_skbuff[i] = skb; 580 if (skb == NULL) { 581 printk (KERN_ERR 582 "%s: alloc_list: allocate Rx buffer error! ", 583 dev->name); 584 break; 585 } 586 skb_reserve (skb, 2); /* 16 byte align the IP header. */ 587 /* Rubicon now supports 40 bits of addressing space. */ 588 np->rx_ring[i].fraginfo = 589 cpu_to_le64 ( pci_map_single ( 590 np->pdev, skb->data, np->rx_buf_sz, 591 PCI_DMA_FROMDEVICE)); 592 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); 593 } 594 595 /* Set RFDListPtr */ 596 writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0); 597 writel (0, dev->base_addr + RFDListPtr1); 598 599 return; 600} 601 602static int 603start_xmit (struct sk_buff *skb, struct net_device *dev) 604{ 605 struct netdev_private *np = netdev_priv(dev); 606 struct netdev_desc *txdesc; 607 unsigned entry; 608 u32 ioaddr; 609 u64 tfc_vlan_tag = 0; 610 611 if (np->link_status == 0) { /* Link Down */ 612 dev_kfree_skb(skb); 613 return 0; 614 } 615 ioaddr = dev->base_addr; 616 entry = np->cur_tx % TX_RING_SIZE; 617 np->tx_skbuff[entry] = skb; 618 txdesc = &np->tx_ring[entry]; 619 620#if 0 621 if (skb->ip_summed == CHECKSUM_PARTIAL) { 622 txdesc->status |= 623 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable | 624 IPChecksumEnable); 625 } 626#endif 627 if (np->vlan) { 628 tfc_vlan_tag = VLANTagInsert | 629 ((u64)np->vlan << 32) | 630 ((u64)skb->priority << 45); 631 } 632 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data, 633 skb->len, 634 PCI_DMA_TODEVICE)); 635 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48); 636 637 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode 638 * Work around: Always use 1 descriptor in 10Mbps mode */ 639 if (entry % np->tx_coalesce == 0 || np->speed == 10) 640 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 641 WordAlignDisable | 642 TxDMAIndicate | 643 (1 << FragCountShift)); 644 else 645 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 646 WordAlignDisable | 647 (1 << FragCountShift)); 648 649 /* TxDMAPollNow */ 650 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl); 651 /* Schedule ISR */ 652 writel(10000, ioaddr + CountDown); 653 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE; 654 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 655 < TX_QUEUE_LEN - 1 && np->speed != 10) { 656 /* do nothing */ 657 } else if (!netif_queue_stopped(dev)) { 658 netif_stop_queue (dev); 659 } 660 661 /* The first TFDListPtr */ 662 if (readl (dev->base_addr + TFDListPtr0) == 0) { 663 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc), 664 dev->base_addr + TFDListPtr0); 665 writel (0, dev->base_addr + TFDListPtr1); 666 } 667 668 /* NETDEV WATCHDOG timer */ 669 dev->trans_start = jiffies; 670 return 0; 671} 672 673static irqreturn_t 674rio_interrupt (int irq, void *dev_instance) 675{ 676 struct net_device *dev = dev_instance; 677 struct netdev_private *np; 678 unsigned int_status; 679 long ioaddr; 680 int cnt = max_intrloop; 681 int handled = 0; 682 683 ioaddr = dev->base_addr; 684 np = netdev_priv(dev); 685 while (1) { 686 int_status = readw (ioaddr + IntStatus); 687 writew (int_status, ioaddr + IntStatus); 688 int_status &= DEFAULT_INTR; 689 if (int_status == 0 || --cnt < 0) 690 break; 691 handled = 1; 692 /* Processing received packets */ 693 if (int_status & RxDMAComplete) 694 receive_packet (dev); 695 /* TxDMAComplete interrupt */ 696 if ((int_status & (TxDMAComplete|IntRequested))) { 697 int tx_status; 698 tx_status = readl (ioaddr + TxStatus); 699 if (tx_status & 0x01) 700 tx_error (dev, tx_status); 701 /* Free used tx skbuffs */ 702 rio_free_tx (dev, 1); 703 } 704 705 /* Handle uncommon events */ 706 if (int_status & 707 (HostError | LinkEvent | UpdateStats)) 708 rio_error (dev, int_status); 709 } 710 if (np->cur_tx != np->old_tx) 711 writel (100, ioaddr + CountDown); 712 return IRQ_RETVAL(handled); 713} 714 715static inline dma_addr_t desc_to_dma(struct netdev_desc *desc) 716{ 717 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48); 718} 719 720static void 721rio_free_tx (struct net_device *dev, int irq) 722{ 723 struct netdev_private *np = netdev_priv(dev); 724 int entry = np->old_tx % TX_RING_SIZE; 725 int tx_use = 0; 726 unsigned long flag = 0; 727 728 if (irq) 729 spin_lock(&np->tx_lock); 730 else 731 spin_lock_irqsave(&np->tx_lock, flag); 732 733 /* Free used tx skbuffs */ 734 while (entry != np->cur_tx) { 735 struct sk_buff *skb; 736 737 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone))) 738 break; 739 skb = np->tx_skbuff[entry]; 740 pci_unmap_single (np->pdev, 741 desc_to_dma(&np->tx_ring[entry]), 742 skb->len, PCI_DMA_TODEVICE); 743 if (irq) 744 dev_kfree_skb_irq (skb); 745 else 746 dev_kfree_skb (skb); 747 748 np->tx_skbuff[entry] = NULL; 749 entry = (entry + 1) % TX_RING_SIZE; 750 tx_use++; 751 } 752 if (irq) 753 spin_unlock(&np->tx_lock); 754 else 755 spin_unlock_irqrestore(&np->tx_lock, flag); 756 np->old_tx = entry; 757 758 /* If the ring is no longer full, clear tx_full and 759 call netif_wake_queue() */ 760 761 if (netif_queue_stopped(dev) && 762 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 763 < TX_QUEUE_LEN - 1 || np->speed == 10)) { 764 netif_wake_queue (dev); 765 } 766} 767 768static void 769tx_error (struct net_device *dev, int tx_status) 770{ 771 struct netdev_private *np; 772 long ioaddr = dev->base_addr; 773 int frame_id; 774 int i; 775 776 np = netdev_priv(dev); 777 778 frame_id = (tx_status & 0xffff0000); 779 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n", 780 dev->name, tx_status, frame_id); 781 np->stats.tx_errors++; 782 /* Ttransmit Underrun */ 783 if (tx_status & 0x10) { 784 np->stats.tx_fifo_errors++; 785 writew (readw (ioaddr + TxStartThresh) + 0x10, 786 ioaddr + TxStartThresh); 787 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */ 788 writew (TxReset | DMAReset | FIFOReset | NetworkReset, 789 ioaddr + ASICCtrl + 2); 790 /* Wait for ResetBusy bit clear */ 791 for (i = 50; i > 0; i--) { 792 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0) 793 break; 794 mdelay (1); 795 } 796 rio_free_tx (dev, 1); 797 /* Reset TFDListPtr */ 798 writel (np->tx_ring_dma + 799 np->old_tx * sizeof (struct netdev_desc), 800 dev->base_addr + TFDListPtr0); 801 writel (0, dev->base_addr + TFDListPtr1); 802 803 /* Let TxStartThresh stay default value */ 804 } 805 /* Late Collision */ 806 if (tx_status & 0x04) { 807 np->stats.tx_fifo_errors++; 808 /* TxReset and clear FIFO */ 809 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2); 810 /* Wait reset done */ 811 for (i = 50; i > 0; i--) { 812 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0) 813 break; 814 mdelay (1); 815 } 816 /* Let TxStartThresh stay default value */ 817 } 818 /* Maximum Collisions */ 819#ifdef ETHER_STATS 820 if (tx_status & 0x08) 821 np->stats.collisions16++; 822#else 823 if (tx_status & 0x08) 824 np->stats.collisions++; 825#endif 826 /* Restart the Tx */ 827 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl); 828} 829 830static int 831receive_packet (struct net_device *dev) 832{ 833 struct netdev_private *np = netdev_priv(dev); 834 int entry = np->cur_rx % RX_RING_SIZE; 835 int cnt = 30; 836 837 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */ 838 while (1) { 839 struct netdev_desc *desc = &np->rx_ring[entry]; 840 int pkt_len; 841 u64 frame_status; 842 843 if (!(desc->status & cpu_to_le64(RFDDone)) || 844 !(desc->status & cpu_to_le64(FrameStart)) || 845 !(desc->status & cpu_to_le64(FrameEnd))) 846 break; 847 848 /* Chip omits the CRC. */ 849 frame_status = le64_to_cpu(desc->status); 850 pkt_len = frame_status & 0xffff; 851 if (--cnt < 0) 852 break; 853 /* Update rx error statistics, drop packet. */ 854 if (frame_status & RFS_Errors) { 855 np->stats.rx_errors++; 856 if (frame_status & (RxRuntFrame | RxLengthError)) 857 np->stats.rx_length_errors++; 858 if (frame_status & RxFCSError) 859 np->stats.rx_crc_errors++; 860 if (frame_status & RxAlignmentError && np->speed != 1000) 861 np->stats.rx_frame_errors++; 862 if (frame_status & RxFIFOOverrun) 863 np->stats.rx_fifo_errors++; 864 } else { 865 struct sk_buff *skb; 866 867 /* Small skbuffs for short packets */ 868 if (pkt_len > copy_thresh) { 869 pci_unmap_single (np->pdev, 870 desc_to_dma(desc), 871 np->rx_buf_sz, 872 PCI_DMA_FROMDEVICE); 873 skb_put (skb = np->rx_skbuff[entry], pkt_len); 874 np->rx_skbuff[entry] = NULL; 875 } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) { 876 pci_dma_sync_single_for_cpu(np->pdev, 877 desc_to_dma(desc), 878 np->rx_buf_sz, 879 PCI_DMA_FROMDEVICE); 880 /* 16 byte align the IP header */ 881 skb_reserve (skb, 2); 882 skb_copy_to_linear_data (skb, 883 np->rx_skbuff[entry]->data, 884 pkt_len); 885 skb_put (skb, pkt_len); 886 pci_dma_sync_single_for_device(np->pdev, 887 desc_to_dma(desc), 888 np->rx_buf_sz, 889 PCI_DMA_FROMDEVICE); 890 } 891 skb->protocol = eth_type_trans (skb, dev); 892#if 0 893 /* Checksum done by hw, but csum value unavailable. */ 894 if (np->pdev->pci_rev_id >= 0x0c && 895 !(frame_status & (TCPError | UDPError | IPError))) { 896 skb->ip_summed = CHECKSUM_UNNECESSARY; 897 } 898#endif 899 netif_rx (skb); 900 } 901 entry = (entry + 1) % RX_RING_SIZE; 902 } 903 spin_lock(&np->rx_lock); 904 np->cur_rx = entry; 905 /* Re-allocate skbuffs to fill the descriptor ring */ 906 entry = np->old_rx; 907 while (entry != np->cur_rx) { 908 struct sk_buff *skb; 909 /* Dropped packets don't need to re-allocate */ 910 if (np->rx_skbuff[entry] == NULL) { 911 skb = netdev_alloc_skb(dev, np->rx_buf_sz); 912 if (skb == NULL) { 913 np->rx_ring[entry].fraginfo = 0; 914 printk (KERN_INFO 915 "%s: receive_packet: " 916 "Unable to re-allocate Rx skbuff.#%d\n", 917 dev->name, entry); 918 break; 919 } 920 np->rx_skbuff[entry] = skb; 921 /* 16 byte align the IP header */ 922 skb_reserve (skb, 2); 923 np->rx_ring[entry].fraginfo = 924 cpu_to_le64 (pci_map_single 925 (np->pdev, skb->data, np->rx_buf_sz, 926 PCI_DMA_FROMDEVICE)); 927 } 928 np->rx_ring[entry].fraginfo |= 929 cpu_to_le64((u64)np->rx_buf_sz << 48); 930 np->rx_ring[entry].status = 0; 931 entry = (entry + 1) % RX_RING_SIZE; 932 } 933 np->old_rx = entry; 934 spin_unlock(&np->rx_lock); 935 return 0; 936} 937 938static void 939rio_error (struct net_device *dev, int int_status) 940{ 941 long ioaddr = dev->base_addr; 942 struct netdev_private *np = netdev_priv(dev); 943 u16 macctrl; 944 945 /* Link change event */ 946 if (int_status & LinkEvent) { 947 if (mii_wait_link (dev, 10) == 0) { 948 printk (KERN_INFO "%s: Link up\n", dev->name); 949 if (np->phy_media) 950 mii_get_media_pcs (dev); 951 else 952 mii_get_media (dev); 953 if (np->speed == 1000) 954 np->tx_coalesce = tx_coalesce; 955 else 956 np->tx_coalesce = 1; 957 macctrl = 0; 958 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 959 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 960 macctrl |= (np->tx_flow) ? 961 TxFlowControlEnable : 0; 962 macctrl |= (np->rx_flow) ? 963 RxFlowControlEnable : 0; 964 writew(macctrl, ioaddr + MACCtrl); 965 np->link_status = 1; 966 netif_carrier_on(dev); 967 } else { 968 printk (KERN_INFO "%s: Link off\n", dev->name); 969 np->link_status = 0; 970 netif_carrier_off(dev); 971 } 972 } 973 974 /* UpdateStats statistics registers */ 975 if (int_status & UpdateStats) { 976 get_stats (dev); 977 } 978 979 /* PCI Error, a catastronphic error related to the bus interface 980 occurs, set GlobalReset and HostReset to reset. */ 981 if (int_status & HostError) { 982 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n", 983 dev->name, int_status); 984 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2); 985 mdelay (500); 986 } 987} 988 989static struct net_device_stats * 990get_stats (struct net_device *dev) 991{ 992 long ioaddr = dev->base_addr; 993 struct netdev_private *np = netdev_priv(dev); 994#ifdef MEM_MAPPING 995 int i; 996#endif 997 unsigned int stat_reg; 998 999 /* All statistics registers need to be acknowledged, 1000 else statistic overflow could cause problems */ 1001 1002 np->stats.rx_packets += readl (ioaddr + FramesRcvOk); 1003 np->stats.tx_packets += readl (ioaddr + FramesXmtOk); 1004 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk); 1005 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk); 1006 1007 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk); 1008 np->stats.collisions += readl (ioaddr + SingleColFrames) 1009 + readl (ioaddr + MultiColFrames); 1010 1011 /* detailed tx errors */ 1012 stat_reg = readw (ioaddr + FramesAbortXSColls); 1013 np->stats.tx_aborted_errors += stat_reg; 1014 np->stats.tx_errors += stat_reg; 1015 1016 stat_reg = readw (ioaddr + CarrierSenseErrors); 1017 np->stats.tx_carrier_errors += stat_reg; 1018 np->stats.tx_errors += stat_reg; 1019 1020 /* Clear all other statistic register. */ 1021 readl (ioaddr + McstOctetXmtOk); 1022 readw (ioaddr + BcstFramesXmtdOk); 1023 readl (ioaddr + McstFramesXmtdOk); 1024 readw (ioaddr + BcstFramesRcvdOk); 1025 readw (ioaddr + MacControlFramesRcvd); 1026 readw (ioaddr + FrameTooLongErrors); 1027 readw (ioaddr + InRangeLengthErrors); 1028 readw (ioaddr + FramesCheckSeqErrors); 1029 readw (ioaddr + FramesLostRxErrors); 1030 readl (ioaddr + McstOctetXmtOk); 1031 readl (ioaddr + BcstOctetXmtOk); 1032 readl (ioaddr + McstFramesXmtdOk); 1033 readl (ioaddr + FramesWDeferredXmt); 1034 readl (ioaddr + LateCollisions); 1035 readw (ioaddr + BcstFramesXmtdOk); 1036 readw (ioaddr + MacControlFramesXmtd); 1037 readw (ioaddr + FramesWEXDeferal); 1038 1039#ifdef MEM_MAPPING 1040 for (i = 0x100; i <= 0x150; i += 4) 1041 readl (ioaddr + i); 1042#endif 1043 readw (ioaddr + TxJumboFrames); 1044 readw (ioaddr + RxJumboFrames); 1045 readw (ioaddr + TCPCheckSumErrors); 1046 readw (ioaddr + UDPCheckSumErrors); 1047 readw (ioaddr + IPCheckSumErrors); 1048 return &np->stats; 1049} 1050 1051static int 1052clear_stats (struct net_device *dev) 1053{ 1054 long ioaddr = dev->base_addr; 1055#ifdef MEM_MAPPING 1056 int i; 1057#endif 1058 1059 /* All statistics registers need to be acknowledged, 1060 else statistic overflow could cause problems */ 1061 readl (ioaddr + FramesRcvOk); 1062 readl (ioaddr + FramesXmtOk); 1063 readl (ioaddr + OctetRcvOk); 1064 readl (ioaddr + OctetXmtOk); 1065 1066 readl (ioaddr + McstFramesRcvdOk); 1067 readl (ioaddr + SingleColFrames); 1068 readl (ioaddr + MultiColFrames); 1069 readl (ioaddr + LateCollisions); 1070 /* detailed rx errors */ 1071 readw (ioaddr + FrameTooLongErrors); 1072 readw (ioaddr + InRangeLengthErrors); 1073 readw (ioaddr + FramesCheckSeqErrors); 1074 readw (ioaddr + FramesLostRxErrors); 1075 1076 /* detailed tx errors */ 1077 readw (ioaddr + FramesAbortXSColls); 1078 readw (ioaddr + CarrierSenseErrors); 1079 1080 /* Clear all other statistic register. */ 1081 readl (ioaddr + McstOctetXmtOk); 1082 readw (ioaddr + BcstFramesXmtdOk); 1083 readl (ioaddr + McstFramesXmtdOk); 1084 readw (ioaddr + BcstFramesRcvdOk); 1085 readw (ioaddr + MacControlFramesRcvd); 1086 readl (ioaddr + McstOctetXmtOk); 1087 readl (ioaddr + BcstOctetXmtOk); 1088 readl (ioaddr + McstFramesXmtdOk); 1089 readl (ioaddr + FramesWDeferredXmt); 1090 readw (ioaddr + BcstFramesXmtdOk); 1091 readw (ioaddr + MacControlFramesXmtd); 1092 readw (ioaddr + FramesWEXDeferal); 1093#ifdef MEM_MAPPING 1094 for (i = 0x100; i <= 0x150; i += 4) 1095 readl (ioaddr + i); 1096#endif 1097 readw (ioaddr + TxJumboFrames); 1098 readw (ioaddr + RxJumboFrames); 1099 readw (ioaddr + TCPCheckSumErrors); 1100 readw (ioaddr + UDPCheckSumErrors); 1101 readw (ioaddr + IPCheckSumErrors); 1102 return 0; 1103} 1104 1105 1106static int 1107change_mtu (struct net_device *dev, int new_mtu) 1108{ 1109 struct netdev_private *np = netdev_priv(dev); 1110 int max = (np->jumbo) ? MAX_JUMBO : 1536; 1111 1112 if ((new_mtu < 68) || (new_mtu > max)) { 1113 return -EINVAL; 1114 } 1115 1116 dev->mtu = new_mtu; 1117 1118 return 0; 1119} 1120 1121static void 1122set_multicast (struct net_device *dev) 1123{ 1124 long ioaddr = dev->base_addr; 1125 u32 hash_table[2]; 1126 u16 rx_mode = 0; 1127 struct netdev_private *np = netdev_priv(dev); 1128 1129 hash_table[0] = hash_table[1] = 0; 1130 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */ 1131 hash_table[1] |= 0x02000000; 1132 if (dev->flags & IFF_PROMISC) { 1133 /* Receive all frames promiscuously. */ 1134 rx_mode = ReceiveAllFrames; 1135 } else if ((dev->flags & IFF_ALLMULTI) || 1136 (dev->mc_count > multicast_filter_limit)) { 1137 /* Receive broadcast and multicast frames */ 1138 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast; 1139 } else if (dev->mc_count > 0) { 1140 int i; 1141 struct dev_mc_list *mclist; 1142 /* Receive broadcast frames and multicast frames filtering 1143 by Hashtable */ 1144 rx_mode = 1145 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast; 1146 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count; 1147 i++, mclist=mclist->next) 1148 { 1149 int bit, index = 0; 1150 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr); 1151 /* The inverted high significant 6 bits of CRC are 1152 used as an index to hashtable */ 1153 for (bit = 0; bit < 6; bit++) 1154 if (crc & (1 << (31 - bit))) 1155 index |= (1 << bit); 1156 hash_table[index / 32] |= (1 << (index % 32)); 1157 } 1158 } else { 1159 rx_mode = ReceiveBroadcast | ReceiveUnicast; 1160 } 1161 if (np->vlan) { 1162 /* ReceiveVLANMatch field in ReceiveMode */ 1163 rx_mode |= ReceiveVLANMatch; 1164 } 1165 1166 writel (hash_table[0], ioaddr + HashTable0); 1167 writel (hash_table[1], ioaddr + HashTable1); 1168 writew (rx_mode, ioaddr + ReceiveMode); 1169} 1170 1171static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1172{ 1173 struct netdev_private *np = netdev_priv(dev); 1174 strcpy(info->driver, "dl2k"); 1175 strcpy(info->version, DRV_VERSION); 1176 strcpy(info->bus_info, pci_name(np->pdev)); 1177} 1178 1179static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1180{ 1181 struct netdev_private *np = netdev_priv(dev); 1182 if (np->phy_media) { 1183 /* fiber device */ 1184 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE; 1185 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE; 1186 cmd->port = PORT_FIBRE; 1187 cmd->transceiver = XCVR_INTERNAL; 1188 } else { 1189 /* copper device */ 1190 cmd->supported = SUPPORTED_10baseT_Half | 1191 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half 1192 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | 1193 SUPPORTED_Autoneg | SUPPORTED_MII; 1194 cmd->advertising = ADVERTISED_10baseT_Half | 1195 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half | 1196 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full| 1197 ADVERTISED_Autoneg | ADVERTISED_MII; 1198 cmd->port = PORT_MII; 1199 cmd->transceiver = XCVR_INTERNAL; 1200 } 1201 if ( np->link_status ) { 1202 cmd->speed = np->speed; 1203 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 1204 } else { 1205 cmd->speed = -1; 1206 cmd->duplex = -1; 1207 } 1208 if ( np->an_enable) 1209 cmd->autoneg = AUTONEG_ENABLE; 1210 else 1211 cmd->autoneg = AUTONEG_DISABLE; 1212 1213 cmd->phy_address = np->phy_addr; 1214 return 0; 1215} 1216 1217static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1218{ 1219 struct netdev_private *np = netdev_priv(dev); 1220 netif_carrier_off(dev); 1221 if (cmd->autoneg == AUTONEG_ENABLE) { 1222 if (np->an_enable) 1223 return 0; 1224 else { 1225 np->an_enable = 1; 1226 mii_set_media(dev); 1227 return 0; 1228 } 1229 } else { 1230 np->an_enable = 0; 1231 if (np->speed == 1000) { 1232 cmd->speed = SPEED_100; 1233 cmd->duplex = DUPLEX_FULL; 1234 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n"); 1235 } 1236 switch(cmd->speed + cmd->duplex) { 1237 1238 case SPEED_10 + DUPLEX_HALF: 1239 np->speed = 10; 1240 np->full_duplex = 0; 1241 break; 1242 1243 case SPEED_10 + DUPLEX_FULL: 1244 np->speed = 10; 1245 np->full_duplex = 1; 1246 break; 1247 case SPEED_100 + DUPLEX_HALF: 1248 np->speed = 100; 1249 np->full_duplex = 0; 1250 break; 1251 case SPEED_100 + DUPLEX_FULL: 1252 np->speed = 100; 1253 np->full_duplex = 1; 1254 break; 1255 case SPEED_1000 + DUPLEX_HALF:/* not supported */ 1256 case SPEED_1000 + DUPLEX_FULL:/* not supported */ 1257 default: 1258 return -EINVAL; 1259 } 1260 mii_set_media(dev); 1261 } 1262 return 0; 1263} 1264 1265static u32 rio_get_link(struct net_device *dev) 1266{ 1267 struct netdev_private *np = netdev_priv(dev); 1268 return np->link_status; 1269} 1270 1271static const struct ethtool_ops ethtool_ops = { 1272 .get_drvinfo = rio_get_drvinfo, 1273 .get_settings = rio_get_settings, 1274 .set_settings = rio_set_settings, 1275 .get_link = rio_get_link, 1276}; 1277 1278static int 1279rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) 1280{ 1281 int phy_addr; 1282 struct netdev_private *np = netdev_priv(dev); 1283 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru; 1284 1285 struct netdev_desc *desc; 1286 int i; 1287 1288 phy_addr = np->phy_addr; 1289 switch (cmd) { 1290 case SIOCDEVPRIVATE: 1291 break; 1292 1293 case SIOCDEVPRIVATE + 1: 1294 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num); 1295 break; 1296 case SIOCDEVPRIVATE + 2: 1297 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value); 1298 break; 1299 case SIOCDEVPRIVATE + 3: 1300 break; 1301 case SIOCDEVPRIVATE + 4: 1302 break; 1303 case SIOCDEVPRIVATE + 5: 1304 netif_stop_queue (dev); 1305 break; 1306 case SIOCDEVPRIVATE + 6: 1307 netif_wake_queue (dev); 1308 break; 1309 case SIOCDEVPRIVATE + 7: 1310 printk 1311 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n", 1312 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx, 1313 np->old_rx); 1314 break; 1315 case SIOCDEVPRIVATE + 8: 1316 printk("TX ring:\n"); 1317 for (i = 0; i < TX_RING_SIZE; i++) { 1318 desc = &np->tx_ring[i]; 1319 printk 1320 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x", 1321 i, 1322 (u32) (np->tx_ring_dma + i * sizeof (*desc)), 1323 (u32)le64_to_cpu(desc->next_desc), 1324 (u32)le64_to_cpu(desc->status), 1325 (u32)(le64_to_cpu(desc->fraginfo) >> 32), 1326 (u32)le64_to_cpu(desc->fraginfo)); 1327 printk ("\n"); 1328 } 1329 printk ("\n"); 1330 break; 1331 1332 default: 1333 return -EOPNOTSUPP; 1334 } 1335 return 0; 1336} 1337 1338#define EEP_READ 0x0200 1339#define EEP_BUSY 0x8000 1340/* Read the EEPROM word */ 1341/* We use I/O instruction to read/write eeprom to avoid fail on some machines */ 1342static int 1343read_eeprom (long ioaddr, int eep_addr) 1344{ 1345 int i = 1000; 1346 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl); 1347 while (i-- > 0) { 1348 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) { 1349 return inw (ioaddr + EepromData); 1350 } 1351 } 1352 return 0; 1353} 1354 1355enum phy_ctrl_bits { 1356 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04, 1357 MII_DUPLEX = 0x08, 1358}; 1359 1360#define mii_delay() readb(ioaddr) 1361static void 1362mii_sendbit (struct net_device *dev, u32 data) 1363{ 1364 long ioaddr = dev->base_addr + PhyCtrl; 1365 data = (data) ? MII_DATA1 : 0; 1366 data |= MII_WRITE; 1367 data |= (readb (ioaddr) & 0xf8) | MII_WRITE; 1368 writeb (data, ioaddr); 1369 mii_delay (); 1370 writeb (data | MII_CLK, ioaddr); 1371 mii_delay (); 1372} 1373 1374static int 1375mii_getbit (struct net_device *dev) 1376{ 1377 long ioaddr = dev->base_addr + PhyCtrl; 1378 u8 data; 1379 1380 data = (readb (ioaddr) & 0xf8) | MII_READ; 1381 writeb (data, ioaddr); 1382 mii_delay (); 1383 writeb (data | MII_CLK, ioaddr); 1384 mii_delay (); 1385 return ((readb (ioaddr) >> 1) & 1); 1386} 1387 1388static void 1389mii_send_bits (struct net_device *dev, u32 data, int len) 1390{ 1391 int i; 1392 for (i = len - 1; i >= 0; i--) { 1393 mii_sendbit (dev, data & (1 << i)); 1394 } 1395} 1396 1397static int 1398mii_read (struct net_device *dev, int phy_addr, int reg_num) 1399{ 1400 u32 cmd; 1401 int i; 1402 u32 retval = 0; 1403 1404 /* Preamble */ 1405 mii_send_bits (dev, 0xffffffff, 32); 1406 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1407 /* ST,OP = 0110'b for read operation */ 1408 cmd = (0x06 << 10 | phy_addr << 5 | reg_num); 1409 mii_send_bits (dev, cmd, 14); 1410 /* Turnaround */ 1411 if (mii_getbit (dev)) 1412 goto err_out; 1413 /* Read data */ 1414 for (i = 0; i < 16; i++) { 1415 retval |= mii_getbit (dev); 1416 retval <<= 1; 1417 } 1418 /* End cycle */ 1419 mii_getbit (dev); 1420 return (retval >> 1) & 0xffff; 1421 1422 err_out: 1423 return 0; 1424} 1425static int 1426mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data) 1427{ 1428 u32 cmd; 1429 1430 /* Preamble */ 1431 mii_send_bits (dev, 0xffffffff, 32); 1432 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1433 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1434 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data; 1435 mii_send_bits (dev, cmd, 32); 1436 /* End cycle */ 1437 mii_getbit (dev); 1438 return 0; 1439} 1440static int 1441mii_wait_link (struct net_device *dev, int wait) 1442{ 1443 __u16 bmsr; 1444 int phy_addr; 1445 struct netdev_private *np; 1446 1447 np = netdev_priv(dev); 1448 phy_addr = np->phy_addr; 1449 1450 do { 1451 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1452 if (bmsr & MII_BMSR_LINK_STATUS) 1453 return 0; 1454 mdelay (1); 1455 } while (--wait > 0); 1456 return -1; 1457} 1458static int 1459mii_get_media (struct net_device *dev) 1460{ 1461 __u16 negotiate; 1462 __u16 bmsr; 1463 __u16 mscr; 1464 __u16 mssr; 1465 int phy_addr; 1466 struct netdev_private *np; 1467 1468 np = netdev_priv(dev); 1469 phy_addr = np->phy_addr; 1470 1471 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1472 if (np->an_enable) { 1473 if (!(bmsr & MII_BMSR_AN_COMPLETE)) { 1474 /* Auto-Negotiation not completed */ 1475 return -1; 1476 } 1477 negotiate = mii_read (dev, phy_addr, MII_ANAR) & 1478 mii_read (dev, phy_addr, MII_ANLPAR); 1479 mscr = mii_read (dev, phy_addr, MII_MSCR); 1480 mssr = mii_read (dev, phy_addr, MII_MSSR); 1481 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) { 1482 np->speed = 1000; 1483 np->full_duplex = 1; 1484 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1485 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) { 1486 np->speed = 1000; 1487 np->full_duplex = 0; 1488 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); 1489 } else if (negotiate & MII_ANAR_100BX_FD) { 1490 np->speed = 100; 1491 np->full_duplex = 1; 1492 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); 1493 } else if (negotiate & MII_ANAR_100BX_HD) { 1494 np->speed = 100; 1495 np->full_duplex = 0; 1496 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); 1497 } else if (negotiate & MII_ANAR_10BT_FD) { 1498 np->speed = 10; 1499 np->full_duplex = 1; 1500 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); 1501 } else if (negotiate & MII_ANAR_10BT_HD) { 1502 np->speed = 10; 1503 np->full_duplex = 0; 1504 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); 1505 } 1506 if (negotiate & MII_ANAR_PAUSE) { 1507 np->tx_flow &= 1; 1508 np->rx_flow &= 1; 1509 } else if (negotiate & MII_ANAR_ASYMMETRIC) { 1510 np->tx_flow = 0; 1511 np->rx_flow &= 1; 1512 } 1513 /* else tx_flow, rx_flow = user select */ 1514 } else { 1515 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1516 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) { 1517 case MII_BMCR_SPEED_1000: 1518 printk (KERN_INFO "Operating at 1000 Mbps, "); 1519 break; 1520 case MII_BMCR_SPEED_100: 1521 printk (KERN_INFO "Operating at 100 Mbps, "); 1522 break; 1523 case 0: 1524 printk (KERN_INFO "Operating at 10 Mbps, "); 1525 } 1526 if (bmcr & MII_BMCR_DUPLEX_MODE) { 1527 printk ("Full duplex\n"); 1528 } else { 1529 printk ("Half duplex\n"); 1530 } 1531 } 1532 if (np->tx_flow) 1533 printk(KERN_INFO "Enable Tx Flow Control\n"); 1534 else 1535 printk(KERN_INFO "Disable Tx Flow Control\n"); 1536 if (np->rx_flow) 1537 printk(KERN_INFO "Enable Rx Flow Control\n"); 1538 else 1539 printk(KERN_INFO "Disable Rx Flow Control\n"); 1540 1541 return 0; 1542} 1543 1544static int 1545mii_set_media (struct net_device *dev) 1546{ 1547 __u16 pscr; 1548 __u16 bmcr; 1549 __u16 bmsr; 1550 __u16 anar; 1551 int phy_addr; 1552 struct netdev_private *np; 1553 np = netdev_priv(dev); 1554 phy_addr = np->phy_addr; 1555 1556 /* Does user set speed? */ 1557 if (np->an_enable) { 1558 /* Advertise capabilities */ 1559 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1560 anar = mii_read (dev, phy_addr, MII_ANAR) & 1561 ~MII_ANAR_100BX_FD & 1562 ~MII_ANAR_100BX_HD & 1563 ~MII_ANAR_100BT4 & 1564 ~MII_ANAR_10BT_FD & 1565 ~MII_ANAR_10BT_HD; 1566 if (bmsr & MII_BMSR_100BX_FD) 1567 anar |= MII_ANAR_100BX_FD; 1568 if (bmsr & MII_BMSR_100BX_HD) 1569 anar |= MII_ANAR_100BX_HD; 1570 if (bmsr & MII_BMSR_100BT4) 1571 anar |= MII_ANAR_100BT4; 1572 if (bmsr & MII_BMSR_10BT_FD) 1573 anar |= MII_ANAR_10BT_FD; 1574 if (bmsr & MII_BMSR_10BT_HD) 1575 anar |= MII_ANAR_10BT_HD; 1576 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC; 1577 mii_write (dev, phy_addr, MII_ANAR, anar); 1578 1579 /* Enable Auto crossover */ 1580 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1581 pscr |= 3 << 5; /* 11'b */ 1582 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1583 1584 /* Soft reset PHY */ 1585 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); 1586 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET; 1587 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1588 mdelay(1); 1589 } else { 1590 /* Force speed setting */ 1591 /* 1) Disable Auto crossover */ 1592 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1593 pscr &= ~(3 << 5); 1594 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1595 1596 /* 2) PHY Reset */ 1597 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1598 bmcr |= MII_BMCR_RESET; 1599 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1600 1601 /* 3) Power Down */ 1602 bmcr = 0x1940; /* must be 0x1940 */ 1603 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1604 mdelay (100); /* wait a certain time */ 1605 1606 /* 4) Advertise nothing */ 1607 mii_write (dev, phy_addr, MII_ANAR, 0); 1608 1609 /* 5) Set media and Power Up */ 1610 bmcr = MII_BMCR_POWER_DOWN; 1611 if (np->speed == 100) { 1612 bmcr |= MII_BMCR_SPEED_100; 1613 printk (KERN_INFO "Manual 100 Mbps, "); 1614 } else if (np->speed == 10) { 1615 printk (KERN_INFO "Manual 10 Mbps, "); 1616 } 1617 if (np->full_duplex) { 1618 bmcr |= MII_BMCR_DUPLEX_MODE; 1619 printk ("Full duplex\n"); 1620 } else { 1621 printk ("Half duplex\n"); 1622 } 1623#if 0 1624 /* Set 1000BaseT Master/Slave setting */ 1625 mscr = mii_read (dev, phy_addr, MII_MSCR); 1626 mscr |= MII_MSCR_CFG_ENABLE; 1627 mscr &= ~MII_MSCR_CFG_VALUE = 0; 1628#endif 1629 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1630 mdelay(10); 1631 } 1632 return 0; 1633} 1634 1635static int 1636mii_get_media_pcs (struct net_device *dev) 1637{ 1638 __u16 negotiate; 1639 __u16 bmsr; 1640 int phy_addr; 1641 struct netdev_private *np; 1642 1643 np = netdev_priv(dev); 1644 phy_addr = np->phy_addr; 1645 1646 bmsr = mii_read (dev, phy_addr, PCS_BMSR); 1647 if (np->an_enable) { 1648 if (!(bmsr & MII_BMSR_AN_COMPLETE)) { 1649 /* Auto-Negotiation not completed */ 1650 return -1; 1651 } 1652 negotiate = mii_read (dev, phy_addr, PCS_ANAR) & 1653 mii_read (dev, phy_addr, PCS_ANLPAR); 1654 np->speed = 1000; 1655 if (negotiate & PCS_ANAR_FULL_DUPLEX) { 1656 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1657 np->full_duplex = 1; 1658 } else { 1659 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); 1660 np->full_duplex = 0; 1661 } 1662 if (negotiate & PCS_ANAR_PAUSE) { 1663 np->tx_flow &= 1; 1664 np->rx_flow &= 1; 1665 } else if (negotiate & PCS_ANAR_ASYMMETRIC) { 1666 np->tx_flow = 0; 1667 np->rx_flow &= 1; 1668 } 1669 /* else tx_flow, rx_flow = user select */ 1670 } else { 1671 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); 1672 printk (KERN_INFO "Operating at 1000 Mbps, "); 1673 if (bmcr & MII_BMCR_DUPLEX_MODE) { 1674 printk ("Full duplex\n"); 1675 } else { 1676 printk ("Half duplex\n"); 1677 } 1678 } 1679 if (np->tx_flow) 1680 printk(KERN_INFO "Enable Tx Flow Control\n"); 1681 else 1682 printk(KERN_INFO "Disable Tx Flow Control\n"); 1683 if (np->rx_flow) 1684 printk(KERN_INFO "Enable Rx Flow Control\n"); 1685 else 1686 printk(KERN_INFO "Disable Rx Flow Control\n"); 1687 1688 return 0; 1689} 1690 1691static int 1692mii_set_media_pcs (struct net_device *dev) 1693{ 1694 __u16 bmcr; 1695 __u16 esr; 1696 __u16 anar; 1697 int phy_addr; 1698 struct netdev_private *np; 1699 np = netdev_priv(dev); 1700 phy_addr = np->phy_addr; 1701 1702 /* Auto-Negotiation? */ 1703 if (np->an_enable) { 1704 /* Advertise capabilities */ 1705 esr = mii_read (dev, phy_addr, PCS_ESR); 1706 anar = mii_read (dev, phy_addr, MII_ANAR) & 1707 ~PCS_ANAR_HALF_DUPLEX & 1708 ~PCS_ANAR_FULL_DUPLEX; 1709 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) 1710 anar |= PCS_ANAR_HALF_DUPLEX; 1711 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) 1712 anar |= PCS_ANAR_FULL_DUPLEX; 1713 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; 1714 mii_write (dev, phy_addr, MII_ANAR, anar); 1715 1716 /* Soft reset PHY */ 1717 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); 1718 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | 1719 MII_BMCR_RESET; 1720 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1721 mdelay(1); 1722 } else { 1723 /* Force speed setting */ 1724 /* PHY Reset */ 1725 bmcr = MII_BMCR_RESET; 1726 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1727 mdelay(10); 1728 if (np->full_duplex) { 1729 bmcr = MII_BMCR_DUPLEX_MODE; 1730 printk (KERN_INFO "Manual full duplex\n"); 1731 } else { 1732 bmcr = 0; 1733 printk (KERN_INFO "Manual half duplex\n"); 1734 } 1735 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1736 mdelay(10); 1737 1738 /* Advertise nothing */ 1739 mii_write (dev, phy_addr, MII_ANAR, 0); 1740 } 1741 return 0; 1742} 1743 1744 1745static int 1746rio_close (struct net_device *dev) 1747{ 1748 long ioaddr = dev->base_addr; 1749 struct netdev_private *np = netdev_priv(dev); 1750 struct sk_buff *skb; 1751 int i; 1752 1753 netif_stop_queue (dev); 1754 1755 /* Disable interrupts */ 1756 writew (0, ioaddr + IntEnable); 1757 1758 /* Stop Tx and Rx logics */ 1759 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl); 1760 1761 free_irq (dev->irq, dev); 1762 del_timer_sync (&np->timer); 1763 1764 /* Free all the skbuffs in the queue. */ 1765 for (i = 0; i < RX_RING_SIZE; i++) { 1766 np->rx_ring[i].status = 0; 1767 np->rx_ring[i].fraginfo = 0; 1768 skb = np->rx_skbuff[i]; 1769 if (skb) { 1770 pci_unmap_single(np->pdev, 1771 desc_to_dma(&np->rx_ring[i]), 1772 skb->len, PCI_DMA_FROMDEVICE); 1773 dev_kfree_skb (skb); 1774 np->rx_skbuff[i] = NULL; 1775 } 1776 } 1777 for (i = 0; i < TX_RING_SIZE; i++) { 1778 skb = np->tx_skbuff[i]; 1779 if (skb) { 1780 pci_unmap_single(np->pdev, 1781 desc_to_dma(&np->tx_ring[i]), 1782 skb->len, PCI_DMA_TODEVICE); 1783 dev_kfree_skb (skb); 1784 np->tx_skbuff[i] = NULL; 1785 } 1786 } 1787 1788 return 0; 1789} 1790 1791static void __devexit 1792rio_remove1 (struct pci_dev *pdev) 1793{ 1794 struct net_device *dev = pci_get_drvdata (pdev); 1795 1796 if (dev) { 1797 struct netdev_private *np = netdev_priv(dev); 1798 1799 unregister_netdev (dev); 1800 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, 1801 np->rx_ring_dma); 1802 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, 1803 np->tx_ring_dma); 1804#ifdef MEM_MAPPING 1805 iounmap ((char *) (dev->base_addr)); 1806#endif 1807 free_netdev (dev); 1808 pci_release_regions (pdev); 1809 pci_disable_device (pdev); 1810 } 1811 pci_set_drvdata (pdev, NULL); 1812} 1813 1814static struct pci_driver rio_driver = { 1815 .name = "dl2k", 1816 .id_table = rio_pci_tbl, 1817 .probe = rio_probe1, 1818 .remove = __devexit_p(rio_remove1), 1819}; 1820 1821static int __init 1822rio_init (void) 1823{ 1824 return pci_register_driver(&rio_driver); 1825} 1826 1827static void __exit 1828rio_exit (void) 1829{ 1830 pci_unregister_driver (&rio_driver); 1831} 1832 1833module_init (rio_init); 1834module_exit (rio_exit); 1835 1836/* 1837 1838Compile command: 1839 1840gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c 1841 1842Read Documentation/networking/dl2k.txt for details. 1843 1844*/ 1845