tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 * Copyright (C) 2008 MontaVista Software, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it would be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 *
13 * You should have received a copy of the GNU General Public
14 * License along with this program; if not, write the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 * For further information regarding this notice, see:
18 *
19 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
20 */
21
22#include <linux/module.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/ioport.h>
29#include <linux/blkdev.h>
30#include <linux/scatterlist.h>
31#include <linux/ioc4.h>
32#include <asm/io.h>
33
34#include <linux/ide.h>
35
36#define DRV_NAME "SGIIOC4"
37
38/* IOC4 Specific Definitions */
39#define IOC4_CMD_OFFSET 0x100
40#define IOC4_CTRL_OFFSET 0x120
41#define IOC4_DMA_OFFSET 0x140
42#define IOC4_INTR_OFFSET 0x0
43
44#define IOC4_TIMING 0x00
45#define IOC4_DMA_PTR_L 0x01
46#define IOC4_DMA_PTR_H 0x02
47#define IOC4_DMA_ADDR_L 0x03
48#define IOC4_DMA_ADDR_H 0x04
49#define IOC4_BC_DEV 0x05
50#define IOC4_BC_MEM 0x06
51#define IOC4_DMA_CTRL 0x07
52#define IOC4_DMA_END_ADDR 0x08
53
54/* Bits in the IOC4 Control/Status Register */
55#define IOC4_S_DMA_START 0x01
56#define IOC4_S_DMA_STOP 0x02
57#define IOC4_S_DMA_DIR 0x04
58#define IOC4_S_DMA_ACTIVE 0x08
59#define IOC4_S_DMA_ERROR 0x10
60#define IOC4_ATA_MEMERR 0x02
61
62/* Read/Write Directions */
63#define IOC4_DMA_WRITE 0x04
64#define IOC4_DMA_READ 0x00
65
66/* Interrupt Register Offsets */
67#define IOC4_INTR_REG 0x03
68#define IOC4_INTR_SET 0x05
69#define IOC4_INTR_CLEAR 0x07
70
71#define IOC4_IDE_CACHELINE_SIZE 128
72#define IOC4_CMD_CTL_BLK_SIZE 0x20
73#define IOC4_SUPPORTED_FIRMWARE_REV 46
74
75typedef struct {
76 u32 timing_reg0;
77 u32 timing_reg1;
78 u32 low_mem_ptr;
79 u32 high_mem_ptr;
80 u32 low_mem_addr;
81 u32 high_mem_addr;
82 u32 dev_byte_count;
83 u32 mem_byte_count;
84 u32 status;
85} ioc4_dma_regs_t;
86
87/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
88/* IOC4 has only 1 IDE channel */
89#define IOC4_PRD_BYTES 16
90#define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
91
92
93static void
94sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
95 unsigned long ctrl_port, unsigned long irq_port)
96{
97 unsigned long reg = data_port;
98 int i;
99
100 /* Registers are word (32 bit) aligned */
101 for (i = 0; i <= 7; i++)
102 hw->io_ports_array[i] = reg + i * 4;
103
104 hw->io_ports.ctl_addr = ctrl_port;
105 hw->io_ports.irq_addr = irq_port;
106}
107
108static int
109sgiioc4_checkirq(ide_hwif_t * hwif)
110{
111 unsigned long intr_addr =
112 hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
113
114 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
115 return 1;
116
117 return 0;
118}
119
120static u8 sgiioc4_read_status(ide_hwif_t *);
121
122static int
123sgiioc4_clearirq(ide_drive_t * drive)
124{
125 u32 intr_reg;
126 ide_hwif_t *hwif = drive->hwif;
127 struct ide_io_ports *io_ports = &hwif->io_ports;
128 unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
129
130 /* Code to check for PCI error conditions */
131 intr_reg = readl((void __iomem *)other_ir);
132 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
133 /*
134 * Using sgiioc4_read_status to read the Status register has a
135 * side effect of clearing the interrupt. The first read should
136 * clear it if it is set. The second read should return
137 * a "clear" status if it got cleared. If not, then spin
138 * for a bit trying to clear it.
139 */
140 u8 stat = sgiioc4_read_status(hwif);
141 int count = 0;
142
143 stat = sgiioc4_read_status(hwif);
144 while ((stat & ATA_BUSY) && (count++ < 100)) {
145 udelay(1);
146 stat = sgiioc4_read_status(hwif);
147 }
148
149 if (intr_reg & 0x02) {
150 struct pci_dev *dev = to_pci_dev(hwif->dev);
151 /* Error when transferring DMA data on PCI bus */
152 u32 pci_err_addr_low, pci_err_addr_high,
153 pci_stat_cmd_reg;
154
155 pci_err_addr_low =
156 readl((void __iomem *)io_ports->irq_addr);
157 pci_err_addr_high =
158 readl((void __iomem *)(io_ports->irq_addr + 4));
159 pci_read_config_dword(dev, PCI_COMMAND,
160 &pci_stat_cmd_reg);
161 printk(KERN_ERR
162 "%s(%s) : PCI Bus Error when doing DMA:"
163 " status-cmd reg is 0x%x\n",
164 __func__, drive->name, pci_stat_cmd_reg);
165 printk(KERN_ERR
166 "%s(%s) : PCI Error Address is 0x%x%x\n",
167 __func__, drive->name,
168 pci_err_addr_high, pci_err_addr_low);
169 /* Clear the PCI Error indicator */
170 pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
171 }
172
173 /* Clear the Interrupt, Error bits on the IOC4 */
174 writel(0x03, (void __iomem *)other_ir);
175
176 intr_reg = readl((void __iomem *)other_ir);
177 }
178
179 return intr_reg & 3;
180}
181
182static void sgiioc4_dma_start(ide_drive_t *drive)
183{
184 ide_hwif_t *hwif = drive->hwif;
185 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
186 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
187 unsigned int temp_reg = reg | IOC4_S_DMA_START;
188
189 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
190}
191
192static u32
193sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
194{
195 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
196 u32 ioc4_dma;
197 int count;
198
199 count = 0;
200 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
201 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
202 udelay(1);
203 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
204 }
205 return ioc4_dma;
206}
207
208/* Stops the IOC4 DMA Engine */
209static int sgiioc4_dma_end(ide_drive_t *drive)
210{
211 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
212 ide_hwif_t *hwif = drive->hwif;
213 unsigned long dma_base = hwif->dma_base;
214 int dma_stat = 0;
215 unsigned long *ending_dma = ide_get_hwifdata(hwif);
216
217 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
218
219 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
220
221 if (ioc4_dma & IOC4_S_DMA_STOP) {
222 printk(KERN_ERR
223 "%s(%s): IOC4 DMA STOP bit is still 1 :"
224 "ioc4_dma_reg 0x%x\n",
225 __func__, drive->name, ioc4_dma);
226 dma_stat = 1;
227 }
228
229 /*
230 * The IOC4 will DMA 1's to the ending dma area to indicate that
231 * previous data DMA is complete. This is necessary because of relaxed
232 * ordering between register reads and DMA writes on the Altix.
233 */
234 while ((cnt++ < 200) && (!valid)) {
235 for (num = 0; num < 16; num++) {
236 if (ending_dma[num]) {
237 valid = 1;
238 break;
239 }
240 }
241 udelay(1);
242 }
243 if (!valid) {
244 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
245 drive->name);
246 dma_stat = 1;
247 }
248
249 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
250 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
251
252 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
253 if (bc_dev > bc_mem + 8) {
254 printk(KERN_ERR
255 "%s(%s): WARNING!! byte_count_dev %d "
256 "!= byte_count_mem %d\n",
257 __func__, drive->name, bc_dev, bc_mem);
258 }
259 }
260
261 return dma_stat;
262}
263
264static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
265{
266}
267
268/* returns 1 if dma irq issued, 0 otherwise */
269static int sgiioc4_dma_test_irq(ide_drive_t *drive)
270{
271 return sgiioc4_checkirq(drive->hwif);
272}
273
274static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
275{
276 if (!on)
277 sgiioc4_clearirq(drive);
278}
279
280static void sgiioc4_resetproc(ide_drive_t *drive)
281{
282 struct ide_cmd *cmd = &drive->hwif->cmd;
283
284 sgiioc4_dma_end(drive);
285 ide_dma_unmap_sg(drive, cmd);
286 sgiioc4_clearirq(drive);
287}
288
289static void
290sgiioc4_dma_lost_irq(ide_drive_t * drive)
291{
292 sgiioc4_resetproc(drive);
293
294 ide_dma_lost_irq(drive);
295}
296
297static u8 sgiioc4_read_status(ide_hwif_t *hwif)
298{
299 unsigned long port = hwif->io_ports.status_addr;
300 u8 reg = (u8) readb((void __iomem *) port);
301
302 if (!(reg & ATA_BUSY)) { /* Not busy... check for interrupt */
303 unsigned long other_ir = port - 0x110;
304 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
305
306 /* Clear the Interrupt, Error bits on the IOC4 */
307 if (intr_reg & 0x03) {
308 writel(0x03, (void __iomem *) other_ir);
309 intr_reg = (u32) readl((void __iomem *) other_ir);
310 }
311 }
312
313 return reg;
314}
315
316/* Creates a dma map for the scatter-gather list entries */
317static int __devinit
318ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
319{
320 struct pci_dev *dev = to_pci_dev(hwif->dev);
321 unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
322 int num_ports = sizeof (ioc4_dma_regs_t);
323 void *pad;
324
325 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
326
327 if (request_mem_region(dma_base, num_ports, hwif->name) == NULL) {
328 printk(KERN_ERR "%s(%s) -- ERROR: addresses 0x%08lx to 0x%08lx "
329 "already in use\n", __func__, hwif->name,
330 dma_base, dma_base + num_ports - 1);
331 return -1;
332 }
333
334 hwif->dma_base = (unsigned long)hwif->io_ports.irq_addr +
335 IOC4_DMA_OFFSET;
336
337 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
338
339 hwif->prd_max_nents = IOC4_PRD_ENTRIES;
340 hwif->prd_ent_size = IOC4_PRD_BYTES;
341
342 if (ide_allocate_dma_engine(hwif))
343 goto dma_pci_alloc_failure;
344
345 pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
346 (dma_addr_t *)&hwif->extra_base);
347 if (pad) {
348 ide_set_hwifdata(hwif, pad);
349 return 0;
350 }
351
352 ide_release_dma_engine(hwif);
353
354 printk(KERN_ERR "%s(%s) -- ERROR: Unable to allocate DMA maps\n",
355 __func__, hwif->name);
356 printk(KERN_INFO "%s: changing from DMA to PIO mode", hwif->name);
357
358dma_pci_alloc_failure:
359 release_mem_region(dma_base, num_ports);
360
361 return -1;
362}
363
364/* Initializes the IOC4 DMA Engine */
365static void
366sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
367{
368 u32 ioc4_dma;
369 ide_hwif_t *hwif = drive->hwif;
370 unsigned long dma_base = hwif->dma_base;
371 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
372 u32 dma_addr, ending_dma_addr;
373
374 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
375
376 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
377 printk(KERN_WARNING
378 "%s(%s):Warning!! DMA from previous transfer was still active\n",
379 __func__, drive->name);
380 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
381 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
382
383 if (ioc4_dma & IOC4_S_DMA_STOP)
384 printk(KERN_ERR
385 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
386 __func__, drive->name);
387 }
388
389 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
390 if (ioc4_dma & IOC4_S_DMA_ERROR) {
391 printk(KERN_WARNING
392 "%s(%s) : Warning!! - DMA Error during Previous"
393 " transfer | status 0x%x\n",
394 __func__, drive->name, ioc4_dma);
395 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
396 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
397
398 if (ioc4_dma & IOC4_S_DMA_STOP)
399 printk(KERN_ERR
400 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
401 __func__, drive->name);
402 }
403
404 /* Address of the Scatter Gather List */
405 dma_addr = cpu_to_le32(hwif->dmatable_dma);
406 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
407
408 /* Address of the Ending DMA */
409 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
410 ending_dma_addr = cpu_to_le32(hwif->extra_base);
411 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
412
413 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
414}
415
416/* IOC4 Scatter Gather list Format */
417/* 128 Bit entries to support 64 bit addresses in the future */
418/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
419/* --------------------------------------------------------------------- */
420/* | Upper 32 bits - Zero | Lower 32 bits- address | */
421/* --------------------------------------------------------------------- */
422/* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
423/* --------------------------------------------------------------------- */
424/* Creates the scatter gather list, DMA Table */
425static int sgiioc4_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
426{
427 ide_hwif_t *hwif = drive->hwif;
428 unsigned int *table = hwif->dmatable_cpu;
429 unsigned int count = 0, i = cmd->sg_nents;
430 struct scatterlist *sg = hwif->sg_table;
431
432 while (i && sg_dma_len(sg)) {
433 dma_addr_t cur_addr;
434 int cur_len;
435 cur_addr = sg_dma_address(sg);
436 cur_len = sg_dma_len(sg);
437
438 while (cur_len) {
439 if (count++ >= IOC4_PRD_ENTRIES) {
440 printk(KERN_WARNING
441 "%s: DMA table too small\n",
442 drive->name);
443 return 0;
444 } else {
445 u32 bcount =
446 0x10000 - (cur_addr & 0xffff);
447
448 if (bcount > cur_len)
449 bcount = cur_len;
450
451 /* put the addr, length in
452 * the IOC4 dma-table format */
453 *table = 0x0;
454 table++;
455 *table = cpu_to_be32(cur_addr);
456 table++;
457 *table = 0x0;
458 table++;
459
460 *table = cpu_to_be32(bcount);
461 table++;
462
463 cur_addr += bcount;
464 cur_len -= bcount;
465 }
466 }
467
468 sg = sg_next(sg);
469 i--;
470 }
471
472 if (count) {
473 table--;
474 *table |= cpu_to_be32(0x80000000);
475 return count;
476 }
477
478 return 0; /* revert to PIO for this request */
479}
480
481static int sgiioc4_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
482{
483 int ddir;
484 u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
485
486 if (sgiioc4_build_dmatable(drive, cmd) == 0)
487 /* try PIO instead of DMA */
488 return 1;
489
490 if (write)
491 /* Writes TO the IOC4 FROM Main Memory */
492 ddir = IOC4_DMA_READ;
493 else
494 /* Writes FROM the IOC4 TO Main Memory */
495 ddir = IOC4_DMA_WRITE;
496
497 sgiioc4_configure_for_dma(ddir, drive);
498
499 return 0;
500}
501
502static const struct ide_tp_ops sgiioc4_tp_ops = {
503 .exec_command = ide_exec_command,
504 .read_status = sgiioc4_read_status,
505 .read_altstatus = ide_read_altstatus,
506 .write_devctl = ide_write_devctl,
507
508 .dev_select = ide_dev_select,
509 .tf_load = ide_tf_load,
510 .tf_read = ide_tf_read,
511
512 .input_data = ide_input_data,
513 .output_data = ide_output_data,
514};
515
516static const struct ide_port_ops sgiioc4_port_ops = {
517 .set_dma_mode = sgiioc4_set_dma_mode,
518 /* reset DMA engine, clear IRQs */
519 .resetproc = sgiioc4_resetproc,
520};
521
522static const struct ide_dma_ops sgiioc4_dma_ops = {
523 .dma_host_set = sgiioc4_dma_host_set,
524 .dma_setup = sgiioc4_dma_setup,
525 .dma_start = sgiioc4_dma_start,
526 .dma_end = sgiioc4_dma_end,
527 .dma_test_irq = sgiioc4_dma_test_irq,
528 .dma_lost_irq = sgiioc4_dma_lost_irq,
529};
530
531static const struct ide_port_info sgiioc4_port_info __devinitconst = {
532 .name = DRV_NAME,
533 .chipset = ide_pci,
534 .init_dma = ide_dma_sgiioc4,
535 .tp_ops = &sgiioc4_tp_ops,
536 .port_ops = &sgiioc4_port_ops,
537 .dma_ops = &sgiioc4_dma_ops,
538 .host_flags = IDE_HFLAG_MMIO,
539 .irq_flags = IRQF_SHARED,
540 .mwdma_mask = ATA_MWDMA2_ONLY,
541};
542
543static int __devinit
544sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
545{
546 unsigned long cmd_base, irqport;
547 unsigned long bar0, cmd_phys_base, ctl;
548 void __iomem *virt_base;
549 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
550 int rc;
551
552 /* Get the CmdBlk and CtrlBlk Base Registers */
553 bar0 = pci_resource_start(dev, 0);
554 virt_base = pci_ioremap_bar(dev, 0);
555 if (virt_base == NULL) {
556 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
557 DRV_NAME, bar0);
558 return -ENOMEM;
559 }
560 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
561 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
562 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
563
564 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
565 if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
566 DRV_NAME) == NULL) {
567 printk(KERN_ERR "%s %s -- ERROR: addresses 0x%08lx to 0x%08lx "
568 "already in use\n", DRV_NAME, pci_name(dev),
569 cmd_phys_base, cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
570 rc = -EBUSY;
571 goto req_mem_rgn_err;
572 }
573
574 /* Initialize the IO registers */
575 memset(&hw, 0, sizeof(hw));
576 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
577 hw.irq = dev->irq;
578 hw.chipset = ide_pci;
579 hw.dev = &dev->dev;
580
581 /* Initializing chipset IRQ Registers */
582 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
583
584 rc = ide_host_add(&sgiioc4_port_info, hws, NULL);
585 if (!rc)
586 return 0;
587
588 release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
589req_mem_rgn_err:
590 iounmap(virt_base);
591 return rc;
592}
593
594static unsigned int __devinit
595pci_init_sgiioc4(struct pci_dev *dev)
596{
597 int ret;
598
599 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
600 DRV_NAME, pci_name(dev), dev->revision);
601
602 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
603 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
604 "firmware is obsolete - please upgrade to "
605 "revision46 or higher\n",
606 DRV_NAME, pci_name(dev));
607 ret = -EAGAIN;
608 goto out;
609 }
610 ret = sgiioc4_ide_setup_pci_device(dev);
611out:
612 return ret;
613}
614
615int __devinit
616ioc4_ide_attach_one(struct ioc4_driver_data *idd)
617{
618 /* PCI-RT does not bring out IDE connection.
619 * Do not attach to this particular IOC4.
620 */
621 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
622 return 0;
623
624 return pci_init_sgiioc4(idd->idd_pdev);
625}
626
627static struct ioc4_submodule __devinitdata ioc4_ide_submodule = {
628 .is_name = "IOC4_ide",
629 .is_owner = THIS_MODULE,
630 .is_probe = ioc4_ide_attach_one,
631/* .is_remove = ioc4_ide_remove_one, */
632};
633
634static int __init ioc4_ide_init(void)
635{
636 return ioc4_register_submodule(&ioc4_ide_submodule);
637}
638
639late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
640
641MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
642MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
643MODULE_LICENSE("GPL");