Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1#include <linux/serial_core.h>
2#include <asm/io.h>
3#include <linux/gpio.h>
4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
24# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
34# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
35# define PORT_PTCR 0xA405011EUL
36# define PORT_PVCR 0xA4050122UL
37# define SCIF_ORER 0x0200 /* overrun error bit */
38#elif defined(CONFIG_SH_RTS7751R2D)
39# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751R)
49# define SCSPTR1 0xffe0001c /* 8 bit SCI */
50# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51# define SCIF_ORER 0x0001 /* overrun error bit */
52# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
53 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
54 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
55#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
56# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
57# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
58# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
59# define SCIF_ORER 0x0001 /* overrun error bit */
60# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
61#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
62# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
63# define SCIF_ORER 0x0001 /* overrun error bit */
64# define PACR 0xa4050100
65# define PBCR 0xa4050102
66# define SCSCR_INIT(port) 0x3B
67#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
68# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
69# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
70# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
71# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
72# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
73#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
74# define PADR 0xA4050120
75# define PSDR 0xA405013e
76# define PWDR 0xA4050166
77# define PSCR 0xA405011E
78# define SCIF_ORER 0x0001 /* overrun error bit */
79# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
80#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
81# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
82# define SCSPTR0 SCPDR0
83# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
86# define SCSPTR0 0xa4050160
87# define SCSPTR1 0xa405013e
88# define SCSPTR2 0xa4050160
89# define SCSPTR3 0xa405013e
90# define SCSPTR4 0xa4050128
91# define SCSPTR5 0xa4050128
92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
95# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
96# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
99# define SCIF_BASE_ADDR 0x01030000
100# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
101# define SCIF_PTR2_OFFS 0x0000020
102# define SCIF_LSR2_OFFS 0x0000024
103# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
104# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
105# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
106#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
107# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
108# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
109#elif defined(CONFIG_H8S2678)
110# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
111# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
112#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
113# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
114# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
115# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
116# define SCIF_ORER 0x0001 /* overrun error bit */
117# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
118#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
119# define SCSPTR0 0xff923020 /* 16 bit SCIF */
120# define SCSPTR1 0xff924020 /* 16 bit SCIF */
121# define SCSPTR2 0xff925020 /* 16 bit SCIF */
122# define SCIF_ORER 0x0001 /* overrun error bit */
123# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
124#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
125# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
126# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
127# define SCIF_ORER 0x0001 /* Overrun error bit */
128# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
129#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
130 defined(CONFIG_CPU_SUBTYPE_SH7786)
131# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
132# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
133# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
134# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
135# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
136# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
137# define SCIF_ORER 0x0001 /* Overrun error bit */
138# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
139#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
140 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
141 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
142 defined(CONFIG_CPU_SUBTYPE_SH7263)
143# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
144# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
145# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
146# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
147# if defined(CONFIG_CPU_SUBTYPE_SH7201)
148# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
149# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
150# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
151# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
152# endif
153# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
154#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
155# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
156# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
157# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
158# define SCIF_ORER 0x0001 /* overrun error bit */
159# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
160#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
161# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
162# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
163# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
164# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
165# define SCIF_ORER 0x0001 /* Overrun error bit */
166# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
167#else
168# error CPU subtype not defined
169#endif
170
171/* SCSCR */
172#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
173#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
174#define SCI_CTRL_FLAGS_TE 0x20 /* all */
175#define SCI_CTRL_FLAGS_RE 0x10 /* all */
176#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
177 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
178 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
179 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
187 defined(CONFIG_CPU_SUBTYPE_SHX3)
188#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
189#else
190#define SCI_CTRL_FLAGS_REIE 0
191#endif
192/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
193/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
194/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
195/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
196
197/* SCxSR SCI */
198#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206
207#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
208
209/* SCxSR SCIF */
210#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218
219#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
220 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
221 defined(CONFIG_CPU_SUBTYPE_SH7721)
222# define SCIF_ORER 0x0200
223# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
224# define SCIF_RFDC_MASK 0x007f
225# define SCIF_TXROOM_MAX 64
226#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
227# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
228# define SCIF_RFDC_MASK 0x007f
229# define SCIF_TXROOM_MAX 64
230/* SH7763 SCIF2 support */
231# define SCIF2_RFDC_MASK 0x001f
232# define SCIF2_TXROOM_MAX 16
233#else
234# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
235# define SCIF_RFDC_MASK 0x001f
236# define SCIF_TXROOM_MAX 16
237#endif
238
239#ifndef SCIF_ORER
240#define SCIF_ORER 0x0000
241#endif
242
243#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
244#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
245#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
246#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
247#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
248#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
249#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
250#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
251
252#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
253 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
254 defined(CONFIG_CPU_SUBTYPE_SH7721)
255# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
256# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
257# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
258# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
259#else
260# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
261# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
262# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
263# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
264#endif
265
266/* SCFCR */
267#define SCFCR_RFRST 0x0002
268#define SCFCR_TFRST 0x0004
269#define SCFCR_TCRST 0x4000
270#define SCFCR_MCE 0x0008
271
272#define SCI_MAJOR 204
273#define SCI_MINOR_START 8
274
275/* Generic serial flags */
276#define SCI_RX_THROTTLE 0x0000001
277
278#define SCI_MAGIC 0xbabeface
279
280/*
281 * Events are used to schedule things to happen at timer-interrupt
282 * time, instead of at rs interrupt time.
283 */
284#define SCI_EVENT_WRITE_WAKEUP 0
285
286#define SCI_IN(size, offset) \
287 if ((size) == 8) { \
288 return ioread8(port->membase + (offset)); \
289 } else { \
290 return ioread16(port->membase + (offset)); \
291 }
292#define SCI_OUT(size, offset, value) \
293 if ((size) == 8) { \
294 iowrite8(value, port->membase + (offset)); \
295 } else if ((size) == 16) { \
296 iowrite16(value, port->membase + (offset)); \
297 }
298
299#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
300 static inline unsigned int sci_##name##_in(struct uart_port *port) \
301 { \
302 if (port->type == PORT_SCIF) { \
303 SCI_IN(scif_size, scif_offset) \
304 } else { /* PORT_SCI or PORT_SCIFA */ \
305 SCI_IN(sci_size, sci_offset); \
306 } \
307 } \
308 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
309 { \
310 if (port->type == PORT_SCIF) { \
311 SCI_OUT(scif_size, scif_offset, value) \
312 } else { /* PORT_SCI or PORT_SCIFA */ \
313 SCI_OUT(sci_size, sci_offset, value); \
314 } \
315 }
316
317#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
318 static inline unsigned int sci_##name##_in(struct uart_port *port) \
319 { \
320 SCI_IN(scif_size, scif_offset); \
321 } \
322 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
323 { \
324 SCI_OUT(scif_size, scif_offset, value); \
325 }
326
327#define CPU_SCI_FNS(name, sci_offset, sci_size) \
328 static inline unsigned int sci_##name##_in(struct uart_port* port) \
329 { \
330 SCI_IN(sci_size, sci_offset); \
331 } \
332 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
333 { \
334 SCI_OUT(sci_size, sci_offset, value); \
335 }
336
337#ifdef CONFIG_CPU_SH3
338#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
339#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
340 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
341 h8_sci_offset, h8_sci_size) \
342 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
343#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
344 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
345#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
346 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
347 defined(CONFIG_CPU_SUBTYPE_SH7721)
348#define SCIF_FNS(name, scif_offset, scif_size) \
349 CPU_SCIF_FNS(name, scif_offset, scif_size)
350#else
351#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
352 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
353 h8_sci_offset, h8_sci_size) \
354 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
355#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
356 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
357#endif
358#elif defined(__H8300H__) || defined(__H8300S__)
359#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
360 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
361 h8_sci_offset, h8_sci_size) \
362 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
364#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
365 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
366 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
367 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
368 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
369#else
370#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
371 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
372 h8_sci_offset, h8_sci_size) \
373 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
374#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
375 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
376#endif
377
378#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
379 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
380 defined(CONFIG_CPU_SUBTYPE_SH7721)
381
382SCIF_FNS(SCSMR, 0x00, 16)
383SCIF_FNS(SCBRR, 0x04, 8)
384SCIF_FNS(SCSCR, 0x08, 16)
385SCIF_FNS(SCTDSR, 0x0c, 8)
386SCIF_FNS(SCFER, 0x10, 16)
387SCIF_FNS(SCxSR, 0x14, 16)
388SCIF_FNS(SCFCR, 0x18, 16)
389SCIF_FNS(SCFDR, 0x1c, 16)
390SCIF_FNS(SCxTDR, 0x20, 8)
391SCIF_FNS(SCxRDR, 0x24, 8)
392SCIF_FNS(SCLSR, 0x24, 16)
393#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
394SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
395SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
396SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
397SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
398SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
399SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
400SCIx_FNS(SCSPTR, 0, 0, 0, 0)
401SCIF_FNS(SCTDSR, 0x0c, 8)
402SCIF_FNS(SCFER, 0x10, 16)
403SCIF_FNS(SCFCR, 0x18, 16)
404SCIF_FNS(SCFDR, 0x1c, 16)
405SCIF_FNS(SCLSR, 0x24, 16)
406#else
407/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
408/* name off sz off sz off sz off sz off sz*/
409SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
410SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
411SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
412SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
413SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
414SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
415SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
416#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
417 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
418 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
419 defined(CONFIG_CPU_SUBTYPE_SH7786)
420SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
421SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
422SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
423SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
424SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
425#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
426SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
427SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
428SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
429SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
430SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
431SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
432SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
433#else
434SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
435#if defined(CONFIG_CPU_SUBTYPE_SH7722)
436SCIF_FNS(SCSPTR, 0, 0, 0, 0)
437#else
438SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
439#endif
440SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
441#endif
442#endif
443#define sci_in(port, reg) sci_##reg##_in(port)
444#define sci_out(port, reg, value) sci_##reg##_out(port, value)
445
446/* H8/300 series SCI pins assignment */
447#if defined(__H8300H__) || defined(__H8300S__)
448static const struct __attribute__((packed)) {
449 int port; /* GPIO port no */
450 unsigned short rx,tx; /* GPIO bit no */
451} h8300_sci_pins[] = {
452#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
453 { /* SCI0 */
454 .port = H8300_GPIO_P9,
455 .rx = H8300_GPIO_B2,
456 .tx = H8300_GPIO_B0,
457 },
458 { /* SCI1 */
459 .port = H8300_GPIO_P9,
460 .rx = H8300_GPIO_B3,
461 .tx = H8300_GPIO_B1,
462 },
463 { /* SCI2 */
464 .port = H8300_GPIO_PB,
465 .rx = H8300_GPIO_B7,
466 .tx = H8300_GPIO_B6,
467 }
468#elif defined(CONFIG_H8S2678)
469 { /* SCI0 */
470 .port = H8300_GPIO_P3,
471 .rx = H8300_GPIO_B2,
472 .tx = H8300_GPIO_B0,
473 },
474 { /* SCI1 */
475 .port = H8300_GPIO_P3,
476 .rx = H8300_GPIO_B3,
477 .tx = H8300_GPIO_B1,
478 },
479 { /* SCI2 */
480 .port = H8300_GPIO_P5,
481 .rx = H8300_GPIO_B1,
482 .tx = H8300_GPIO_B0,
483 }
484#endif
485};
486#endif
487
488#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
489 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
490 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
491 defined(CONFIG_CPU_SUBTYPE_SH7709)
492static inline int sci_rxd_in(struct uart_port *port)
493{
494 if (port->mapbase == 0xfffffe80)
495 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
496 if (port->mapbase == 0xa4000150)
497 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
498 if (port->mapbase == 0xa4000140)
499 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
500 return 1;
501}
502#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
503static inline int sci_rxd_in(struct uart_port *port)
504{
505 if (port->mapbase == SCIF0)
506 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
507 if (port->mapbase == SCIF2)
508 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
509 return 1;
510}
511#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
512static inline int sci_rxd_in(struct uart_port *port)
513{
514 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
515}
516#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
517 defined(CONFIG_CPU_SUBTYPE_SH7721)
518static inline int sci_rxd_in(struct uart_port *port)
519{
520 if (port->mapbase == 0xa4430000)
521 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
522 else if (port->mapbase == 0xa4438000)
523 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
524 return 1;
525}
526#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
528 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
529 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
530 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
531 defined(CONFIG_CPU_SUBTYPE_SH7091)
532static inline int sci_rxd_in(struct uart_port *port)
533{
534 if (port->mapbase == 0xffe00000)
535 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
536 if (port->mapbase == 0xffe80000)
537 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
538 return 1;
539}
540#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
541static inline int sci_rxd_in(struct uart_port *port)
542{
543 if (port->mapbase == 0xffe80000)
544 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
545 return 1;
546}
547#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
548static inline int sci_rxd_in(struct uart_port *port)
549{
550 if (port->mapbase == 0xfe600000)
551 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
552 if (port->mapbase == 0xfe610000)
553 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
554 if (port->mapbase == 0xfe620000)
555 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
556 return 1;
557}
558#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
559static inline int sci_rxd_in(struct uart_port *port)
560{
561 if (port->mapbase == 0xffe00000)
562 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
563 if (port->mapbase == 0xffe10000)
564 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
565 if (port->mapbase == 0xffe20000)
566 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
567 if (port->mapbase == 0xffe30000)
568 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
569 return 1;
570}
571#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
572static inline int sci_rxd_in(struct uart_port *port)
573{
574 if (port->mapbase == 0xffe00000)
575 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
576 return 1;
577}
578#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
579static inline int sci_rxd_in(struct uart_port *port)
580{
581 if (port->mapbase == 0xffe00000)
582 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
583 if (port->mapbase == 0xffe10000)
584 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
585 if (port->mapbase == 0xffe20000)
586 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
587
588 return 1;
589}
590#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
591static inline int sci_rxd_in(struct uart_port *port)
592{
593 if (port->mapbase == 0xffe00000)
594 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
595 if (port->mapbase == 0xffe10000)
596 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
597 if (port->mapbase == 0xffe20000)
598 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
599 if (port->mapbase == 0xa4e30000)
600 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
601 if (port->mapbase == 0xa4e40000)
602 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
603 if (port->mapbase == 0xa4e50000)
604 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
605 return 1;
606}
607#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
608static inline int sci_rxd_in(struct uart_port *port)
609{
610 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
611}
612#elif defined(__H8300H__) || defined(__H8300S__)
613static inline int sci_rxd_in(struct uart_port *port)
614{
615 int ch = (port->mapbase - SMR0) >> 3;
616 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
617}
618#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
619static inline int sci_rxd_in(struct uart_port *port)
620{
621 if (port->mapbase == 0xffe00000)
622 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
623 if (port->mapbase == 0xffe08000)
624 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
625 if (port->mapbase == 0xffe10000)
626 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
627
628 return 1;
629}
630#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
631static inline int sci_rxd_in(struct uart_port *port)
632{
633 if (port->mapbase == 0xff923000)
634 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
635 if (port->mapbase == 0xff924000)
636 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
637 if (port->mapbase == 0xff925000)
638 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
639 return 1;
640}
641#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
642static inline int sci_rxd_in(struct uart_port *port)
643{
644 if (port->mapbase == 0xffe00000)
645 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
646 if (port->mapbase == 0xffe10000)
647 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
648 return 1;
649}
650#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
651 defined(CONFIG_CPU_SUBTYPE_SH7786)
652static inline int sci_rxd_in(struct uart_port *port)
653{
654 if (port->mapbase == 0xffea0000)
655 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
656 if (port->mapbase == 0xffeb0000)
657 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
658 if (port->mapbase == 0xffec0000)
659 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
660 if (port->mapbase == 0xffed0000)
661 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
662 if (port->mapbase == 0xffee0000)
663 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
664 if (port->mapbase == 0xffef0000)
665 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
666 return 1;
667}
668#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
669 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
670 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
671 defined(CONFIG_CPU_SUBTYPE_SH7263)
672static inline int sci_rxd_in(struct uart_port *port)
673{
674 if (port->mapbase == 0xfffe8000)
675 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
676 if (port->mapbase == 0xfffe8800)
677 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
678 if (port->mapbase == 0xfffe9000)
679 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
680 if (port->mapbase == 0xfffe9800)
681 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
682#if defined(CONFIG_CPU_SUBTYPE_SH7201)
683 if (port->mapbase == 0xfffeA000)
684 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
685 if (port->mapbase == 0xfffeA800)
686 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
687 if (port->mapbase == 0xfffeB000)
688 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
689 if (port->mapbase == 0xfffeB800)
690 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
691#endif
692 return 1;
693}
694#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
695static inline int sci_rxd_in(struct uart_port *port)
696{
697 if (port->mapbase == 0xf8400000)
698 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
699 if (port->mapbase == 0xf8410000)
700 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
701 if (port->mapbase == 0xf8420000)
702 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
703 return 1;
704}
705#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
706static inline int sci_rxd_in(struct uart_port *port)
707{
708 if (port->mapbase == 0xffc30000)
709 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
710 if (port->mapbase == 0xffc40000)
711 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
712 if (port->mapbase == 0xffc50000)
713 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
714 if (port->mapbase == 0xffc60000)
715 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
716 return 1;
717}
718#endif
719
720/*
721 * Values for the BitRate Register (SCBRR)
722 *
723 * The values are actually divisors for a frequency which can
724 * be internal to the SH3 (14.7456MHz) or derived from an external
725 * clock source. This driver assumes the internal clock is used;
726 * to support using an external clock source, config options or
727 * possibly command-line options would need to be added.
728 *
729 * Also, to support speeds below 2400 (why?) the lower 2 bits of
730 * the SCSMR register would also need to be set to non-zero values.
731 *
732 * -- Greg Banks 27Feb2000
733 *
734 * Answer: The SCBRR register is only eight bits, and the value in
735 * it gets larger with lower baud rates. At around 2400 (depending on
736 * the peripherial module clock) you run out of bits. However the
737 * lower two bits of SCSMR allow the module clock to be divided down,
738 * scaling the value which is needed in SCBRR.
739 *
740 * -- Stuart Menefy - 23 May 2000
741 *
742 * I meant, why would anyone bother with bitrates below 2400.
743 *
744 * -- Greg Banks - 7Jul2000
745 *
746 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
747 * tape reader as a console!
748 *
749 * -- Mitch Davis - 15 Jul 2000
750 */
751
752#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
753 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
754 defined(CONFIG_CPU_SUBTYPE_SH7786)
755#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
756#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
757 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
758 defined(CONFIG_CPU_SUBTYPE_SH7721)
759#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
760#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
761static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
762{
763 if (port->type == PORT_SCIF)
764 return (clk+16*bps)/(32*bps)-1;
765 else
766 return ((clk*2)+16*bps)/(16*bps)-1;
767}
768#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
769#elif defined(__H8300H__) || defined(__H8300S__)
770#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
771#else /* Generic SH */
772#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
773#endif