tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Q40 I/O port IDE Driver
3 *
4 * (c) Richard Zidlicky
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 *
11 */
12
13#include <linux/types.h>
14#include <linux/mm.h>
15#include <linux/interrupt.h>
16#include <linux/blkdev.h>
17#include <linux/ide.h>
18
19#include <asm/ide.h>
20
21 /*
22 * Bases of the IDE interfaces
23 */
24
25#define Q40IDE_NUM_HWIFS 2
26
27#define PCIDE_BASE1 0x1f0
28#define PCIDE_BASE2 0x170
29#define PCIDE_BASE3 0x1e8
30#define PCIDE_BASE4 0x168
31#define PCIDE_BASE5 0x1e0
32#define PCIDE_BASE6 0x160
33
34static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
35 PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
36 PCIDE_BASE6 */
37};
38
39static int q40ide_default_irq(unsigned long base)
40{
41 switch (base) {
42 case 0x1f0: return 14;
43 case 0x170: return 15;
44 case 0x1e8: return 11;
45 default:
46 return 0;
47 }
48}
49
50
51/*
52 * Addresses are pretranslated for Q40 ISA access.
53 */
54static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
55 ide_ack_intr_t *ack_intr,
56 int irq)
57{
58 memset(hw, 0, sizeof(hw_regs_t));
59 /* BIG FAT WARNING:
60 assumption: only DATA port is ever used in 16 bit mode */
61 hw->io_ports.data_addr = Q40_ISA_IO_W(base);
62 hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
63 hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
64 hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
65 hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
66 hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
67 hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
68 hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
69 hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
70
71 hw->irq = irq;
72 hw->ack_intr = ack_intr;
73
74 hw->chipset = ide_generic;
75}
76
77static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
78 void *buf, unsigned int len)
79{
80 unsigned long data_addr = drive->hwif->io_ports.data_addr;
81
82 if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
83 __ide_mm_insw(data_addr, buf, (len + 1) / 2);
84 return;
85 }
86
87 raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
88}
89
90static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
91 void *buf, unsigned int len)
92{
93 unsigned long data_addr = drive->hwif->io_ports.data_addr;
94
95 if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
96 __ide_mm_outsw(data_addr, buf, (len + 1) / 2);
97 return;
98 }
99
100 raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
101}
102
103/* Q40 has a byte-swapped IDE interface */
104static const struct ide_tp_ops q40ide_tp_ops = {
105 .exec_command = ide_exec_command,
106 .read_status = ide_read_status,
107 .read_altstatus = ide_read_altstatus,
108 .write_devctl = ide_write_devctl,
109
110 .dev_select = ide_dev_select,
111 .tf_load = ide_tf_load,
112 .tf_read = ide_tf_read,
113
114 .input_data = q40ide_input_data,
115 .output_data = q40ide_output_data,
116};
117
118static const struct ide_port_info q40ide_port_info = {
119 .tp_ops = &q40ide_tp_ops,
120 .host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
121 .irq_flags = IRQF_SHARED,
122};
123
124/*
125 * the static array is needed to have the name reported in /proc/ioports,
126 * hwif->name unfortunately isn't available yet
127 */
128static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
129 "ide0", "ide1"
130};
131
132/*
133 * Probe for Q40 IDE interfaces
134 */
135
136static int __init q40ide_init(void)
137{
138 int i;
139 hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
140
141 if (!MACH_IS_Q40)
142 return -ENODEV;
143
144 printk(KERN_INFO "ide: Q40 IDE controller\n");
145
146 for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
147 const char *name = q40_ide_names[i];
148
149 if (!request_region(pcide_bases[i], 8, name)) {
150 printk("could not reserve ports %lx-%lx for %s\n",
151 pcide_bases[i],pcide_bases[i]+8,name);
152 continue;
153 }
154 if (!request_region(pcide_bases[i]+0x206, 1, name)) {
155 printk("could not reserve port %lx for %s\n",
156 pcide_bases[i]+0x206,name);
157 release_region(pcide_bases[i], 8);
158 continue;
159 }
160 q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
161 q40ide_default_irq(pcide_bases[i]));
162
163 hws[i] = &hw[i];
164 }
165
166 return ide_host_add(&q40ide_port_info, hws, NULL);
167}
168
169module_init(q40ide_init);
170
171MODULE_LICENSE("GPL");