tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
7#include <linux/stringify.h>
8#include <asm/asm-compat.h>
9#include <asm/processor.h>
10#include <asm/ppc-opcode.h>
11
12#ifndef __ASSEMBLY__
13#error __FILE__ should only be used in assembler files
14#else
15
16#define SZL (BITS_PER_LONG/8)
17
18/*
19 * Stuff for accurate CPU time accounting.
20 * These macros handle transitions between user and system state
21 * in exception entry and exit and accumulate time to the
22 * user_time and system_time fields in the paca.
23 */
24
25#ifndef CONFIG_VIRT_CPU_ACCOUNTING
26#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
27#define ACCOUNT_CPU_USER_EXIT(ra, rb)
28#else
29#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
30 beq 2f; /* if from kernel mode */ \
31BEGIN_FTR_SECTION; \
32 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
33END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
34BEGIN_FTR_SECTION; \
35 MFTB(ra); /* or get TB if no PURR */ \
36END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
37 ld rb,PACA_STARTPURR(r13); \
38 std ra,PACA_STARTPURR(r13); \
39 subf rb,rb,ra; /* subtract start value */ \
40 ld ra,PACA_USER_TIME(r13); \
41 add ra,ra,rb; /* add on to user time */ \
42 std ra,PACA_USER_TIME(r13); \
432:
44
45#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
46BEGIN_FTR_SECTION; \
47 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
48END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
49BEGIN_FTR_SECTION; \
50 MFTB(ra); /* or get TB if no PURR */ \
51END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
52 ld rb,PACA_STARTPURR(r13); \
53 std ra,PACA_STARTPURR(r13); \
54 subf rb,rb,ra; /* subtract start value */ \
55 ld ra,PACA_SYSTEM_TIME(r13); \
56 add ra,ra,rb; /* add on to user time */ \
57 std ra,PACA_SYSTEM_TIME(r13);
58#endif
59
60/*
61 * Macros for storing registers into and loading registers from
62 * exception frames.
63 */
64#ifdef __powerpc64__
65#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
66#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
67#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
68#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
69#else
70#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
71#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
72#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
73 SAVE_10GPRS(22, base)
74#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
75 REST_10GPRS(22, base)
76#endif
77
78/*
79 * Define what the VSX XX1 form instructions will look like, then add
80 * the 128 bit load store instructions based on that.
81 */
82#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
83 ((rb) << 11) | (((xs) >> 5)))
84
85#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
86#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
87
88#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
89#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
90#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
91#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
92#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
93#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
94#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
95#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
96
97#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
98#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
99#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
100#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
101#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
102#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
103#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
104#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
105#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
106#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
107#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
108#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
109
110#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
111#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
112#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
113#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
114#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
115#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
116#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
117#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
118#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
119#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
120#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
121#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
122
123/* Save the lower 32 VSRs in the thread VSR region */
124#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base)
125#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
126#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
127#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
128#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
129#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
130#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
131#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
132#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
133#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
134#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
135#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
136/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
137#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base)
138#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
139#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
140#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
141#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
142#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
143#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
144#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
145#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
146#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
147#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
148#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
149
150#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
151#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
152#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
153#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
154#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
155#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
156#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
157#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
158#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
159#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
160#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
161#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
162
163/* Macros to adjust thread priority for hardware multithreading */
164#define HMT_VERY_LOW or 31,31,31 # very low priority
165#define HMT_LOW or 1,1,1
166#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
167#define HMT_MEDIUM or 2,2,2
168#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
169#define HMT_HIGH or 3,3,3
170
171#ifdef __KERNEL__
172#ifdef CONFIG_PPC64
173
174#define XGLUE(a,b) a##b
175#define GLUE(a,b) XGLUE(a,b)
176
177#define _GLOBAL(name) \
178 .section ".text"; \
179 .align 2 ; \
180 .globl name; \
181 .globl GLUE(.,name); \
182 .section ".opd","aw"; \
183name: \
184 .quad GLUE(.,name); \
185 .quad .TOC.@tocbase; \
186 .quad 0; \
187 .previous; \
188 .type GLUE(.,name),@function; \
189GLUE(.,name):
190
191#define _INIT_GLOBAL(name) \
192 .section ".text.init.refok"; \
193 .align 2 ; \
194 .globl name; \
195 .globl GLUE(.,name); \
196 .section ".opd","aw"; \
197name: \
198 .quad GLUE(.,name); \
199 .quad .TOC.@tocbase; \
200 .quad 0; \
201 .previous; \
202 .type GLUE(.,name),@function; \
203GLUE(.,name):
204
205#define _KPROBE(name) \
206 .section ".kprobes.text","a"; \
207 .align 2 ; \
208 .globl name; \
209 .globl GLUE(.,name); \
210 .section ".opd","aw"; \
211name: \
212 .quad GLUE(.,name); \
213 .quad .TOC.@tocbase; \
214 .quad 0; \
215 .previous; \
216 .type GLUE(.,name),@function; \
217GLUE(.,name):
218
219#define _STATIC(name) \
220 .section ".text"; \
221 .align 2 ; \
222 .section ".opd","aw"; \
223name: \
224 .quad GLUE(.,name); \
225 .quad .TOC.@tocbase; \
226 .quad 0; \
227 .previous; \
228 .type GLUE(.,name),@function; \
229GLUE(.,name):
230
231#define _INIT_STATIC(name) \
232 .section ".text.init.refok"; \
233 .align 2 ; \
234 .section ".opd","aw"; \
235name: \
236 .quad GLUE(.,name); \
237 .quad .TOC.@tocbase; \
238 .quad 0; \
239 .previous; \
240 .type GLUE(.,name),@function; \
241GLUE(.,name):
242
243#else /* 32-bit */
244
245#define _ENTRY(n) \
246 .globl n; \
247n:
248
249#define _GLOBAL(n) \
250 .text; \
251 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
252 .globl n; \
253n:
254
255#define _KPROBE(n) \
256 .section ".kprobes.text","a"; \
257 .globl n; \
258n:
259
260#endif
261
262/*
263 * LOAD_REG_IMMEDIATE(rn, expr)
264 * Loads the value of the constant expression 'expr' into register 'rn'
265 * using immediate instructions only. Use this when it's important not
266 * to reference other data (i.e. on ppc64 when the TOC pointer is not
267 * valid) and when 'expr' is a constant or absolute address.
268 *
269 * LOAD_REG_ADDR(rn, name)
270 * Loads the address of label 'name' into register 'rn'. Use this when
271 * you don't particularly need immediate instructions only, but you need
272 * the whole address in one register (e.g. it's a structure address and
273 * you want to access various offsets within it). On ppc32 this is
274 * identical to LOAD_REG_IMMEDIATE.
275 *
276 * LOAD_REG_ADDRBASE(rn, name)
277 * ADDROFF(name)
278 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
279 * register 'rn'. ADDROFF(name) returns the remainder of the address as
280 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
281 * in size, so is suitable for use directly as an offset in load and store
282 * instructions. Use this when loading/storing a single word or less as:
283 * LOAD_REG_ADDRBASE(rX, name)
284 * ld rY,ADDROFF(name)(rX)
285 */
286#ifdef __powerpc64__
287#define LOAD_REG_IMMEDIATE(reg,expr) \
288 lis (reg),(expr)@highest; \
289 ori (reg),(reg),(expr)@higher; \
290 rldicr (reg),(reg),32,31; \
291 oris (reg),(reg),(expr)@h; \
292 ori (reg),(reg),(expr)@l;
293
294#define LOAD_REG_ADDR(reg,name) \
295 ld (reg),name@got(r2)
296
297#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
298#define ADDROFF(name) 0
299
300/* offsets for stack frame layout */
301#define LRSAVE 16
302
303#else /* 32-bit */
304
305#define LOAD_REG_IMMEDIATE(reg,expr) \
306 lis (reg),(expr)@ha; \
307 addi (reg),(reg),(expr)@l;
308
309#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
310
311#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
312#define ADDROFF(name) name@l
313
314/* offsets for stack frame layout */
315#define LRSAVE 4
316
317#endif
318
319/* various errata or part fixups */
320#ifdef CONFIG_PPC601_SYNC_FIX
321#define SYNC \
322BEGIN_FTR_SECTION \
323 sync; \
324 isync; \
325END_FTR_SECTION_IFSET(CPU_FTR_601)
326#define SYNC_601 \
327BEGIN_FTR_SECTION \
328 sync; \
329END_FTR_SECTION_IFSET(CPU_FTR_601)
330#define ISYNC_601 \
331BEGIN_FTR_SECTION \
332 isync; \
333END_FTR_SECTION_IFSET(CPU_FTR_601)
334#else
335#define SYNC
336#define SYNC_601
337#define ISYNC_601
338#endif
339
340#ifdef CONFIG_PPC_CELL
341#define MFTB(dest) \
34290: mftb dest; \
343BEGIN_FTR_SECTION_NESTED(96); \
344 cmpwi dest,0; \
345 beq- 90b; \
346END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
347#else
348#define MFTB(dest) mftb dest
349#endif
350
351#ifndef CONFIG_SMP
352#define TLBSYNC
353#else /* CONFIG_SMP */
354/* tlbsync is not implemented on 601 */
355#define TLBSYNC \
356BEGIN_FTR_SECTION \
357 tlbsync; \
358 sync; \
359END_FTR_SECTION_IFCLR(CPU_FTR_601)
360#endif
361
362
363/*
364 * This instruction is not implemented on the PPC 603 or 601; however, on
365 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
366 * All of these instructions exist in the 8xx, they have magical powers,
367 * and they must be used.
368 */
369
370#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
371#define tlbia \
372 li r4,1024; \
373 mtctr r4; \
374 lis r4,KERNELBASE@h; \
3750: tlbie r4; \
376 addi r4,r4,0x1000; \
377 bdnz 0b
378#endif
379
380
381#ifdef CONFIG_IBM440EP_ERR42
382#define PPC440EP_ERR42 isync
383#else
384#define PPC440EP_ERR42
385#endif
386
387
388#if defined(CONFIG_BOOKE)
389#define toreal(rd)
390#define fromreal(rd)
391
392/*
393 * We use addis to ensure compatibility with the "classic" ppc versions of
394 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
395 * converting the address in r0, and so this version has to do that too
396 * (i.e. set register rd to 0 when rs == 0).
397 */
398#define tophys(rd,rs) \
399 addis rd,rs,0
400
401#define tovirt(rd,rs) \
402 addis rd,rs,0
403
404#elif defined(CONFIG_PPC64)
405#define toreal(rd) /* we can access c000... in real mode */
406#define fromreal(rd)
407
408#define tophys(rd,rs) \
409 clrldi rd,rs,2
410
411#define tovirt(rd,rs) \
412 rotldi rd,rs,16; \
413 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
414 rotldi rd,rd,48
415#else
416/*
417 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
418 * physical base address of RAM at compile time.
419 */
420#define toreal(rd) tophys(rd,rd)
421#define fromreal(rd) tovirt(rd,rd)
422
423#define tophys(rd,rs) \
4240: addis rd,rs,-PAGE_OFFSET@h; \
425 .section ".vtop_fixup","aw"; \
426 .align 1; \
427 .long 0b; \
428 .previous
429
430#define tovirt(rd,rs) \
4310: addis rd,rs,PAGE_OFFSET@h; \
432 .section ".ptov_fixup","aw"; \
433 .align 1; \
434 .long 0b; \
435 .previous
436#endif
437
438#ifdef CONFIG_PPC64
439#define RFI rfid
440#define MTMSRD(r) mtmsrd r
441
442#else
443#define FIX_SRR1(ra, rb)
444#ifndef CONFIG_40x
445#define RFI rfi
446#else
447#define RFI rfi; b . /* Prevent prefetch past rfi */
448#endif
449#define MTMSRD(r) mtmsr r
450#define CLR_TOP32(r)
451#endif
452
453#endif /* __KERNEL__ */
454
455/* The boring bits... */
456
457/* Condition Register Bit Fields */
458
459#define cr0 0
460#define cr1 1
461#define cr2 2
462#define cr3 3
463#define cr4 4
464#define cr5 5
465#define cr6 6
466#define cr7 7
467
468
469/* General Purpose Registers (GPRs) */
470
471#define r0 0
472#define r1 1
473#define r2 2
474#define r3 3
475#define r4 4
476#define r5 5
477#define r6 6
478#define r7 7
479#define r8 8
480#define r9 9
481#define r10 10
482#define r11 11
483#define r12 12
484#define r13 13
485#define r14 14
486#define r15 15
487#define r16 16
488#define r17 17
489#define r18 18
490#define r19 19
491#define r20 20
492#define r21 21
493#define r22 22
494#define r23 23
495#define r24 24
496#define r25 25
497#define r26 26
498#define r27 27
499#define r28 28
500#define r29 29
501#define r30 30
502#define r31 31
503
504
505/* Floating Point Registers (FPRs) */
506
507#define fr0 0
508#define fr1 1
509#define fr2 2
510#define fr3 3
511#define fr4 4
512#define fr5 5
513#define fr6 6
514#define fr7 7
515#define fr8 8
516#define fr9 9
517#define fr10 10
518#define fr11 11
519#define fr12 12
520#define fr13 13
521#define fr14 14
522#define fr15 15
523#define fr16 16
524#define fr17 17
525#define fr18 18
526#define fr19 19
527#define fr20 20
528#define fr21 21
529#define fr22 22
530#define fr23 23
531#define fr24 24
532#define fr25 25
533#define fr26 26
534#define fr27 27
535#define fr28 28
536#define fr29 29
537#define fr30 30
538#define fr31 31
539
540/* AltiVec Registers (VPRs) */
541
542#define vr0 0
543#define vr1 1
544#define vr2 2
545#define vr3 3
546#define vr4 4
547#define vr5 5
548#define vr6 6
549#define vr7 7
550#define vr8 8
551#define vr9 9
552#define vr10 10
553#define vr11 11
554#define vr12 12
555#define vr13 13
556#define vr14 14
557#define vr15 15
558#define vr16 16
559#define vr17 17
560#define vr18 18
561#define vr19 19
562#define vr20 20
563#define vr21 21
564#define vr22 22
565#define vr23 23
566#define vr24 24
567#define vr25 25
568#define vr26 26
569#define vr27 27
570#define vr28 28
571#define vr29 29
572#define vr30 30
573#define vr31 31
574
575/* VSX Registers (VSRs) */
576
577#define vsr0 0
578#define vsr1 1
579#define vsr2 2
580#define vsr3 3
581#define vsr4 4
582#define vsr5 5
583#define vsr6 6
584#define vsr7 7
585#define vsr8 8
586#define vsr9 9
587#define vsr10 10
588#define vsr11 11
589#define vsr12 12
590#define vsr13 13
591#define vsr14 14
592#define vsr15 15
593#define vsr16 16
594#define vsr17 17
595#define vsr18 18
596#define vsr19 19
597#define vsr20 20
598#define vsr21 21
599#define vsr22 22
600#define vsr23 23
601#define vsr24 24
602#define vsr25 25
603#define vsr26 26
604#define vsr27 27
605#define vsr28 28
606#define vsr29 29
607#define vsr30 30
608#define vsr31 31
609#define vsr32 32
610#define vsr33 33
611#define vsr34 34
612#define vsr35 35
613#define vsr36 36
614#define vsr37 37
615#define vsr38 38
616#define vsr39 39
617#define vsr40 40
618#define vsr41 41
619#define vsr42 42
620#define vsr43 43
621#define vsr44 44
622#define vsr45 45
623#define vsr46 46
624#define vsr47 47
625#define vsr48 48
626#define vsr49 49
627#define vsr50 50
628#define vsr51 51
629#define vsr52 52
630#define vsr53 53
631#define vsr54 54
632#define vsr55 55
633#define vsr56 56
634#define vsr57 57
635#define vsr58 58
636#define vsr59 59
637#define vsr60 60
638#define vsr61 61
639#define vsr62 62
640#define vsr63 63
641
642/* SPE Registers (EVPRs) */
643
644#define evr0 0
645#define evr1 1
646#define evr2 2
647#define evr3 3
648#define evr4 4
649#define evr5 5
650#define evr6 6
651#define evr7 7
652#define evr8 8
653#define evr9 9
654#define evr10 10
655#define evr11 11
656#define evr12 12
657#define evr13 13
658#define evr14 14
659#define evr15 15
660#define evr16 16
661#define evr17 17
662#define evr18 18
663#define evr19 19
664#define evr20 20
665#define evr21 21
666#define evr22 22
667#define evr23 23
668#define evr24 24
669#define evr25 25
670#define evr26 26
671#define evr27 27
672#define evr28 28
673#define evr29 29
674#define evr30 30
675#define evr31 31
676
677/* some stab codes */
678#define N_FUN 36
679#define N_RSYM 64
680#define N_SLINE 68
681#define N_SO 100
682
683#endif /* __ASSEMBLY__ */
684
685#endif /* _ASM_POWERPC_PPC_ASM_H */