Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
3 * AVR32 systems.)
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef DW_DMAC_H
12#define DW_DMAC_H
13
14#include <linux/dmaengine.h>
15
16/**
17 * struct dw_dma_platform_data - Controller configuration parameters
18 * @nr_channels: Number of channels supported by hardware (max 8)
19 */
20struct dw_dma_platform_data {
21 unsigned int nr_channels;
22};
23
24/**
25 * enum dw_dma_slave_width - DMA slave register access width.
26 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
27 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
28 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
29 */
30enum dw_dma_slave_width {
31 DW_DMA_SLAVE_WIDTH_8BIT,
32 DW_DMA_SLAVE_WIDTH_16BIT,
33 DW_DMA_SLAVE_WIDTH_32BIT,
34};
35
36/**
37 * struct dw_dma_slave - Controller-specific information about a slave
38 *
39 * @dma_dev: required DMA master device
40 * @tx_reg: physical address of data register used for
41 * memory-to-peripheral transfers
42 * @rx_reg: physical address of data register used for
43 * peripheral-to-memory transfers
44 * @reg_width: peripheral register width
45 * @cfg_hi: Platform-specific initializer for the CFG_HI register
46 * @cfg_lo: Platform-specific initializer for the CFG_LO register
47 */
48struct dw_dma_slave {
49 struct device *dma_dev;
50 dma_addr_t tx_reg;
51 dma_addr_t rx_reg;
52 enum dw_dma_slave_width reg_width;
53 u32 cfg_hi;
54 u32 cfg_lo;
55};
56
57/* Platform-configurable bits in CFG_HI */
58#define DWC_CFGH_FCMODE (1 << 0)
59#define DWC_CFGH_FIFO_MODE (1 << 1)
60#define DWC_CFGH_PROTCTL(x) ((x) << 2)
61#define DWC_CFGH_SRC_PER(x) ((x) << 7)
62#define DWC_CFGH_DST_PER(x) ((x) << 11)
63
64/* Platform-configurable bits in CFG_LO */
65#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
66#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
67#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
68#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
69#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
70#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
71#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
72#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
73#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
74#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
75#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
76
77#endif /* DW_DMAC_H */