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1/* Blackfin KGDB header
2 *
3 * Copyright 2005-2009 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef __ASM_BLACKFIN_KGDB_H__
9#define __ASM_BLACKFIN_KGDB_H__
10
11#include <linux/ptrace.h>
12
13/* gdb locks */
14#define KGDB_MAX_NO_CPUS 8
15
16/*
17 * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
18 * At least NUMREGBYTES*2 are needed for register packets.
19 * Longer buffer is needed to list all threads.
20 */
21#define BUFMAX 2048
22
23/*
24 * Note that this register image is different from
25 * the register image that Linux produces at interrupt time.
26 *
27 * Linux's register image is defined by struct pt_regs in ptrace.h.
28 */
29enum regnames {
30 /* Core Registers */
31 BFIN_R0 = 0,
32 BFIN_R1,
33 BFIN_R2,
34 BFIN_R3,
35 BFIN_R4,
36 BFIN_R5,
37 BFIN_R6,
38 BFIN_R7,
39 BFIN_P0,
40 BFIN_P1,
41 BFIN_P2,
42 BFIN_P3,
43 BFIN_P4,
44 BFIN_P5,
45 BFIN_SP,
46 BFIN_FP,
47 BFIN_I0,
48 BFIN_I1,
49 BFIN_I2,
50 BFIN_I3,
51 BFIN_M0,
52 BFIN_M1,
53 BFIN_M2,
54 BFIN_M3,
55 BFIN_B0,
56 BFIN_B1,
57 BFIN_B2,
58 BFIN_B3,
59 BFIN_L0,
60 BFIN_L1,
61 BFIN_L2,
62 BFIN_L3,
63 BFIN_A0_DOT_X,
64 BFIN_A0_DOT_W,
65 BFIN_A1_DOT_X,
66 BFIN_A1_DOT_W,
67 BFIN_ASTAT,
68 BFIN_RETS,
69 BFIN_LC0,
70 BFIN_LT0,
71 BFIN_LB0,
72 BFIN_LC1,
73 BFIN_LT1,
74 BFIN_LB1,
75 BFIN_CYCLES,
76 BFIN_CYCLES2,
77 BFIN_USP,
78 BFIN_SEQSTAT,
79 BFIN_SYSCFG,
80 BFIN_RETI,
81 BFIN_RETX,
82 BFIN_RETN,
83 BFIN_RETE,
84
85 /* Pseudo Registers */
86 BFIN_PC,
87 BFIN_CC,
88 BFIN_EXTRA1, /* Address of .text section. */
89 BFIN_EXTRA2, /* Address of .data section. */
90 BFIN_EXTRA3, /* Address of .bss section. */
91 BFIN_FDPIC_EXEC,
92 BFIN_FDPIC_INTERP,
93
94 /* MMRs */
95 BFIN_IPEND,
96
97 /* LAST ENTRY SHOULD NOT BE CHANGED. */
98 BFIN_NUM_REGS /* The number of all registers. */
99};
100
101/* Number of bytes of registers. */
102#define NUMREGBYTES BFIN_NUM_REGS*4
103
104static inline void arch_kgdb_breakpoint(void)
105{
106 asm("EXCPT 2;");
107}
108#define BREAK_INSTR_SIZE 2
109#define CACHE_FLUSH_IS_SAFE 1
110#define HW_INST_WATCHPOINT_NUM 6
111#define HW_WATCHPOINT_NUM 8
112#define TYPE_INST_WATCHPOINT 0
113#define TYPE_DATA_WATCHPOINT 1
114
115/* Instruction watchpoint address control register bits mask */
116#define WPPWR 0x1
117#define WPIREN01 0x2
118#define WPIRINV01 0x4
119#define WPIAEN0 0x8
120#define WPIAEN1 0x10
121#define WPICNTEN0 0x20
122#define WPICNTEN1 0x40
123#define EMUSW0 0x80
124#define EMUSW1 0x100
125#define WPIREN23 0x200
126#define WPIRINV23 0x400
127#define WPIAEN2 0x800
128#define WPIAEN3 0x1000
129#define WPICNTEN2 0x2000
130#define WPICNTEN3 0x4000
131#define EMUSW2 0x8000
132#define EMUSW3 0x10000
133#define WPIREN45 0x20000
134#define WPIRINV45 0x40000
135#define WPIAEN4 0x80000
136#define WPIAEN5 0x100000
137#define WPICNTEN4 0x200000
138#define WPICNTEN5 0x400000
139#define EMUSW4 0x800000
140#define EMUSW5 0x1000000
141#define WPAND 0x2000000
142
143/* Data watchpoint address control register bits mask */
144#define WPDREN01 0x1
145#define WPDRINV01 0x2
146#define WPDAEN0 0x4
147#define WPDAEN1 0x8
148#define WPDCNTEN0 0x10
149#define WPDCNTEN1 0x20
150
151#define WPDSRC0 0xc0
152#define WPDACC0_OFFSET 8
153#define WPDSRC1 0xc00
154#define WPDACC1_OFFSET 12
155
156/* Watchpoint status register bits mask */
157#define STATIA0 0x1
158#define STATIA1 0x2
159#define STATIA2 0x4
160#define STATIA3 0x8
161#define STATIA4 0x10
162#define STATIA5 0x20
163#define STATDA0 0x40
164#define STATDA1 0x80
165
166#endif