tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* bnx2x_fw_defs.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
13#define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16 (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
17 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
18 0x40) + (index * 0x4)))
19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20 (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
21 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23 (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
24 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
25#define CSTORM_FUNCTION_MODE_OFFSET \
26 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
27#define CSTORM_HC_BTR_OFFSET(port) \
28 (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30 (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
32 (index * 0x4)))
33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34 (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
36 (index * 0x4)))
37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38 (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41 (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43#define CSTORM_STATS_FLAGS_OFFSET(function) \
44 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
45 (function * 0x8)))
46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
50#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \
54 : (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
55#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
56 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
57 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
58 0x28) + (index * 0x4)))
59#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
60 (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
61 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
62#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
63 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
64 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
65#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
66 (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
67 (function * 0x8)))
68#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
69 (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
70 (function * 0x38)))
71#define TSTORM_FUNCTION_MODE_OFFSET \
72 (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
73#define TSTORM_HC_BTR_OFFSET(port) \
74 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
75#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
76 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
77 (function * 0x80)))
78#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
79#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
80 (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
81 (function * 0x38)))
82#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
83 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
84 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))
85#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
86 (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
87 : (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
88#define TSTORM_STATS_FLAGS_OFFSET(function) \
89 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
90 (function * 0x8)))
91#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)
92#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
93#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
94#define USTORM_ASSERT_LIST_INDEX_OFFSET \
95 (IS_E1H_OFFSET ? 0x8000 : 0x1000)
96#define USTORM_ASSERT_LIST_OFFSET(idx) \
97 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
98#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
99 (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
100 (0x5450 + (port * 0x1c8) + (clientId * 0x18)))
101#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
102 (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \
103 ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \
104 0x28) + (index * 0x4)))
105#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
106 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \
107 ((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))
108#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
109 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \
110 ((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))
111#define USTORM_FUNCTION_MODE_OFFSET \
112 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
113#define USTORM_HC_BTR_OFFSET(port) \
114 (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
115#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
116 (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
117 (0x5448 + (port * 0x1c8) + (clientId * 0x18)))
118#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
119 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \
120 (function * 0x8)))
121#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
122 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
123 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
124 (index * 0x4)))
125#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
126 (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
127 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
128 (index * 0x4)))
129#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
130 (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
131 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
132#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
133 (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
134 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
135#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
136 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
137#define XSTORM_ASSERT_LIST_OFFSET(idx) \
138 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
139#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
140 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
141#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
142 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
143 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
144 0x28) + (index * 0x4)))
145#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
146 (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
147 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
148#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
149 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
150 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
151#define XSTORM_E1HOV_OFFSET(function) \
152 (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)
153#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
154 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
155 (function * 0x8)))
156#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
157 (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \
158 (function * 0x70)))
159#define XSTORM_FUNCTION_MODE_OFFSET \
160 (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)
161#define XSTORM_HC_BTR_OFFSET(port) \
162 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
163#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
164 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
165 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
166#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
167 (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \
168 (function * 0x70)))
169#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
170 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
171 (function * 0x10)))
172#define XSTORM_SPQ_PROD_OFFSET(function) \
173 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
174 (function * 0x10)))
175#define XSTORM_STATS_FLAGS_OFFSET(function) \
176 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
177 (function * 0x8)))
178#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
179
180/**
181* This file defines HSI constatnts for the ETH flow
182*/
183#ifdef _EVEREST_MICROCODE
184#include "microcode_constants.h"
185#include "eth_rx_bd.h"
186#include "eth_tx_bd.h"
187#include "eth_rx_cqe.h"
188#include "eth_rx_sge.h"
189#include "eth_rx_cqe_next_page.h"
190#endif
191
192/* RSS hash types */
193#define DEFAULT_HASH_TYPE 0
194#define IPV4_HASH_TYPE 1
195#define TCP_IPV4_HASH_TYPE 2
196#define IPV6_HASH_TYPE 3
197#define TCP_IPV6_HASH_TYPE 4
198
199/* Ethernet Ring parmaters */
200#define X_ETH_LOCAL_RING_SIZE 13
201#define FIRST_BD_IN_PKT 0
202#define PARSE_BD_INDEX 1
203#define NUM_OF_ETH_BDS_IN_PAGE \
204 ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
205
206
207/* Rx ring params */
208#define U_ETH_LOCAL_BD_RING_SIZE (16)
209#define U_ETH_LOCAL_SGE_RING_SIZE (12)
210#define U_ETH_SGL_SIZE (8)
211
212
213#define U_ETH_BDS_PER_PAGE_MASK \
214 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
215#define U_ETH_CQE_PER_PAGE_MASK \
216 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
217#define U_ETH_SGES_PER_PAGE_MASK \
218 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
219
220#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
221 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
222
223
224#define TU_ETH_CQES_PER_PAGE \
225 (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
226#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
227#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
228
229#define U_ETH_UNDEFINED_Q 0xFF
230
231/* values of command IDs in the ramrod message */
232#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
233#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
234#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
235#define RAMROD_CMD_ID_ETH_UPDATE (100)
236#define RAMROD_CMD_ID_ETH_HALT (105)
237#define RAMROD_CMD_ID_ETH_SET_MAC (110)
238#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
239#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
240#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
241
242
243/* command values for set mac command */
244#define T_ETH_MAC_COMMAND_SET 0
245#define T_ETH_MAC_COMMAND_INVALIDATE 1
246
247#define T_ETH_INDIRECTION_TABLE_SIZE 128
248
249/*The CRC32 seed, that is used for the hash(reduction) multicast address */
250#define T_ETH_CRC32_HASH_SEED 0x00000000
251
252/* Maximal L2 clients supported */
253#define ETH_MAX_RX_CLIENTS_E1 19
254#define ETH_MAX_RX_CLIENTS_E1H 25
255
256/* Maximal aggregation queues supported */
257#define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
258#define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
259
260
261/**
262* This file defines HSI constatnts common to all microcode flows
263*/
264
265/* Connection types */
266#define ETH_CONNECTION_TYPE 0
267#define TOE_CONNECTION_TYPE 1
268#define RDMA_CONNECTION_TYPE 2
269#define ISCSI_CONNECTION_TYPE 3
270#define FCOE_CONNECTION_TYPE 4
271#define RESERVED_CONNECTION_TYPE_0 5
272#define RESERVED_CONNECTION_TYPE_1 6
273#define RESERVED_CONNECTION_TYPE_2 7
274
275
276#define PROTOCOL_STATE_BIT_OFFSET 6
277
278#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
279#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
280#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
281#define ISCSI_STATE \
282 (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
283#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
284
285/* microcode fixed page page size 4K (chains and ring segments) */
286#define MC_PAGE_SIZE (4096)
287
288
289/* Host coalescing constants */
290
291/* index numbers */
292#define HC_USTORM_DEF_SB_NUM_INDICES 4
293#define HC_CSTORM_DEF_SB_NUM_INDICES 8
294#define HC_XSTORM_DEF_SB_NUM_INDICES 4
295#define HC_TSTORM_DEF_SB_NUM_INDICES 4
296#define HC_USTORM_SB_NUM_INDICES 4
297#define HC_CSTORM_SB_NUM_INDICES 4
298
299/* index values - which counterto update */
300
301#define HC_INDEX_U_TOE_RX_CQ_CONS 0
302#define HC_INDEX_U_ETH_RX_CQ_CONS 1
303#define HC_INDEX_U_ETH_RX_BD_CONS 2
304#define HC_INDEX_U_FCOE_EQ_CONS 3
305
306#define HC_INDEX_C_TOE_TX_CQ_CONS 0
307#define HC_INDEX_C_ETH_TX_CQ_CONS 1
308#define HC_INDEX_C_ISCSI_EQ_CONS 2
309
310#define HC_INDEX_DEF_X_SPQ_CONS 0
311
312#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
313#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
314#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
315#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
316#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
317#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
318
319#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
320#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
321#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
322#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
323
324
325/* used by the driver to get the SB offset */
326#define USTORM_ID 0
327#define CSTORM_ID 1
328#define XSTORM_ID 2
329#define TSTORM_ID 3
330#define ATTENTION_ID 4
331
332/* max number of slow path commands per port */
333#define MAX_RAMRODS_PER_PORT (8)
334
335/* values for RX ETH CQE type field */
336#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
337#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
338
339
340/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
341#define EMULATION_FREQUENCY_FACTOR (1600)
342#define FPGA_FREQUENCY_FACTOR (100)
343
344#define TIMERS_TICK_SIZE_CHIP (1e-3)
345#define TIMERS_TICK_SIZE_EMUL \
346 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
347#define TIMERS_TICK_SIZE_FPGA \
348 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
349
350#define TSEMI_CLK1_RESUL_CHIP (1e-3)
351#define TSEMI_CLK1_RESUL_EMUL \
352 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
353#define TSEMI_CLK1_RESUL_FPGA \
354 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
355
356#define USEMI_CLK1_RESUL_CHIP \
357 (TIMERS_TICK_SIZE_CHIP)
358#define USEMI_CLK1_RESUL_EMUL \
359 (TIMERS_TICK_SIZE_EMUL)
360#define USEMI_CLK1_RESUL_FPGA \
361 (TIMERS_TICK_SIZE_FPGA)
362
363#define XSEMI_CLK1_RESUL_CHIP (1e-3)
364#define XSEMI_CLK1_RESUL_EMUL \
365 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
366#define XSEMI_CLK1_RESUL_FPGA \
367 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
368
369#define XSEMI_CLK2_RESUL_CHIP (1e-6)
370#define XSEMI_CLK2_RESUL_EMUL \
371 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
372#define XSEMI_CLK2_RESUL_FPGA \
373 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
374
375#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
376#define SDM_TIMER_TICK_RESUL_EMUL \
377 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
378#define SDM_TIMER_TICK_RESUL_FPGA \
379 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
380
381
382/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
383#define XSTORM_IP_ID_ROLL_HALF 0x8000
384#define XSTORM_IP_ID_ROLL_ALL 0
385
386#define FW_LOG_LIST_SIZE (50)
387
388#define NUM_OF_PROTOCOLS 4
389#define MAX_COS_NUMBER 16
390#define MAX_T_STAT_COUNTER_ID 18
391#define MAX_X_STAT_COUNTER_ID 18
392
393#define UNKNOWN_ADDRESS 0
394#define UNICAST_ADDRESS 1
395#define MULTICAST_ADDRESS 2
396#define BROADCAST_ADDRESS 3
397
398#define SINGLE_FUNCTION 0
399#define MULTI_FUNCTION 1
400
401#define IP_V4 0
402#define IP_V6 1
403