tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
20 */
21
22#ifndef _INTEL_IOMMU_H_
23#define _INTEL_IOMMU_H_
24
25#include <linux/types.h>
26#include <linux/iova.h>
27#include <linux/io.h>
28#include <linux/dma_remapping.h>
29#include <asm/cacheflush.h>
30#include <asm/iommu.h>
31
32/*
33 * Intel IOMMU register specification per version 1.0 public spec.
34 */
35
36#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
37#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
38#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
39#define DMAR_GCMD_REG 0x18 /* Global command register */
40#define DMAR_GSTS_REG 0x1c /* Global status register */
41#define DMAR_RTADDR_REG 0x20 /* Root entry table */
42#define DMAR_CCMD_REG 0x28 /* Context command reg */
43#define DMAR_FSTS_REG 0x34 /* Fault Status register */
44#define DMAR_FECTL_REG 0x38 /* Fault control register */
45#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
46#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
47#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
48#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
49#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
50#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
51#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
52#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
53#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
54#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
55#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
56#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
57#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
58#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
59
60#define OFFSET_STRIDE (9)
61/*
62#define dmar_readl(dmar, reg) readl(dmar + reg)
63#define dmar_readq(dmar, reg) ({ \
64 u32 lo, hi; \
65 lo = readl(dmar + reg); \
66 hi = readl(dmar + reg + 4); \
67 (((u64) hi) << 32) + lo; })
68*/
69static inline u64 dmar_readq(void __iomem *addr)
70{
71 u32 lo, hi;
72 lo = readl(addr);
73 hi = readl(addr + 4);
74 return (((u64) hi) << 32) + lo;
75}
76
77static inline void dmar_writeq(void __iomem *addr, u64 val)
78{
79 writel((u32)val, addr);
80 writel((u32)(val >> 32), addr + 4);
81}
82
83#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
84#define DMAR_VER_MINOR(v) ((v) & 0x0f)
85
86/*
87 * Decoding Capability Register
88 */
89#define cap_read_drain(c) (((c) >> 55) & 1)
90#define cap_write_drain(c) (((c) >> 54) & 1)
91#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
92#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
93#define cap_pgsel_inv(c) (((c) >> 39) & 1)
94
95#define cap_super_page_val(c) (((c) >> 34) & 0xf)
96#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
97 * OFFSET_STRIDE) + 21)
98
99#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
100#define cap_max_fault_reg_offset(c) \
101 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
102
103#define cap_zlr(c) (((c) >> 22) & 1)
104#define cap_isoch(c) (((c) >> 23) & 1)
105#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
106#define cap_sagaw(c) (((c) >> 8) & 0x1f)
107#define cap_caching_mode(c) (((c) >> 7) & 1)
108#define cap_phmr(c) (((c) >> 6) & 1)
109#define cap_plmr(c) (((c) >> 5) & 1)
110#define cap_rwbf(c) (((c) >> 4) & 1)
111#define cap_afl(c) (((c) >> 3) & 1)
112#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
113/*
114 * Extended Capability Register
115 */
116
117#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
118#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
119#define ecap_max_iotlb_offset(e) \
120 (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
121#define ecap_coherent(e) ((e) & 0x1)
122#define ecap_qis(e) ((e) & 0x2)
123#define ecap_eim_support(e) ((e >> 4) & 0x1)
124#define ecap_ir_support(e) ((e >> 3) & 0x1)
125#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
126
127
128/* IOTLB_REG */
129#define DMA_TLB_FLUSH_GRANU_OFFSET 60
130#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
131#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
132#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
133#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
134#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
135#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
136#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
137#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
138#define DMA_TLB_IVT (((u64)1) << 63)
139#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
140#define DMA_TLB_MAX_SIZE (0x3f)
141
142/* INVALID_DESC */
143#define DMA_CCMD_INVL_GRANU_OFFSET 61
144#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
145#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
146#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
147#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
148#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
149#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
150#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
151#define DMA_ID_TLB_ADDR(addr) (addr)
152#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
153
154/* PMEN_REG */
155#define DMA_PMEN_EPM (((u32)1)<<31)
156#define DMA_PMEN_PRS (((u32)1)<<0)
157
158/* GCMD_REG */
159#define DMA_GCMD_TE (((u32)1) << 31)
160#define DMA_GCMD_SRTP (((u32)1) << 30)
161#define DMA_GCMD_SFL (((u32)1) << 29)
162#define DMA_GCMD_EAFL (((u32)1) << 28)
163#define DMA_GCMD_WBF (((u32)1) << 27)
164#define DMA_GCMD_QIE (((u32)1) << 26)
165#define DMA_GCMD_SIRTP (((u32)1) << 24)
166#define DMA_GCMD_IRE (((u32) 1) << 25)
167
168/* GSTS_REG */
169#define DMA_GSTS_TES (((u32)1) << 31)
170#define DMA_GSTS_RTPS (((u32)1) << 30)
171#define DMA_GSTS_FLS (((u32)1) << 29)
172#define DMA_GSTS_AFLS (((u32)1) << 28)
173#define DMA_GSTS_WBFS (((u32)1) << 27)
174#define DMA_GSTS_QIES (((u32)1) << 26)
175#define DMA_GSTS_IRTPS (((u32)1) << 24)
176#define DMA_GSTS_IRES (((u32)1) << 25)
177
178/* CCMD_REG */
179#define DMA_CCMD_ICC (((u64)1) << 63)
180#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
181#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
182#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
183#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
184#define DMA_CCMD_MASK_NOBIT 0
185#define DMA_CCMD_MASK_1BIT 1
186#define DMA_CCMD_MASK_2BIT 2
187#define DMA_CCMD_MASK_3BIT 3
188#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
189#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
190
191/* FECTL_REG */
192#define DMA_FECTL_IM (((u32)1) << 31)
193
194/* FSTS_REG */
195#define DMA_FSTS_PPF ((u32)2)
196#define DMA_FSTS_PFO ((u32)1)
197#define DMA_FSTS_IQE (1 << 4)
198#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
199
200/* FRCD_REG, 32 bits access */
201#define DMA_FRCD_F (((u32)1) << 31)
202#define dma_frcd_type(d) ((d >> 30) & 1)
203#define dma_frcd_fault_reason(c) (c & 0xff)
204#define dma_frcd_source_id(c) (c & 0xffff)
205/* low 64 bit */
206#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
207
208#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
209do { \
210 cycles_t start_time = get_cycles(); \
211 while (1) { \
212 sts = op(iommu->reg + offset); \
213 if (cond) \
214 break; \
215 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
216 panic("DMAR hardware is malfunctioning\n"); \
217 cpu_relax(); \
218 } \
219} while (0)
220
221#define QI_LENGTH 256 /* queue length */
222
223enum {
224 QI_FREE,
225 QI_IN_USE,
226 QI_DONE
227};
228
229#define QI_CC_TYPE 0x1
230#define QI_IOTLB_TYPE 0x2
231#define QI_DIOTLB_TYPE 0x3
232#define QI_IEC_TYPE 0x4
233#define QI_IWD_TYPE 0x5
234
235#define QI_IEC_SELECTIVE (((u64)1) << 4)
236#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
237#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
238
239#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
240#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
241
242#define QI_IOTLB_DID(did) (((u64)did) << 16)
243#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
244#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
245#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
246#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
247#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
248#define QI_IOTLB_AM(am) (((u8)am))
249
250#define QI_CC_FM(fm) (((u64)fm) << 48)
251#define QI_CC_SID(sid) (((u64)sid) << 32)
252#define QI_CC_DID(did) (((u64)did) << 16)
253#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
254
255struct qi_desc {
256 u64 low, high;
257};
258
259struct q_inval {
260 spinlock_t q_lock;
261 struct qi_desc *desc; /* invalidation queue */
262 int *desc_status; /* desc status */
263 int free_head; /* first free entry */
264 int free_tail; /* last free entry */
265 int free_cnt;
266};
267
268#ifdef CONFIG_INTR_REMAP
269/* 1MB - maximum possible interrupt remapping table size */
270#define INTR_REMAP_PAGE_ORDER 8
271#define INTR_REMAP_TABLE_REG_SIZE 0xf
272
273#define INTR_REMAP_TABLE_ENTRIES 65536
274
275struct ir_table {
276 struct irte *base;
277};
278#endif
279
280struct iommu_flush {
281 int (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
282 u64 type, int non_present_entry_flush);
283 int (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
284 unsigned int size_order, u64 type, int non_present_entry_flush);
285};
286
287struct intel_iommu {
288 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
289 u64 cap;
290 u64 ecap;
291 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
292 spinlock_t register_lock; /* protect register handling */
293 int seq_id; /* sequence id of the iommu */
294 int agaw; /* agaw of this iommu */
295
296#ifdef CONFIG_DMAR
297 unsigned long *domain_ids; /* bitmap of domains */
298 struct dmar_domain **domains; /* ptr to domains */
299 spinlock_t lock; /* protect context, domain ids */
300 struct root_entry *root_entry; /* virtual address */
301
302 unsigned int irq;
303 unsigned char name[7]; /* Device Name */
304 struct iommu_flush flush;
305#endif
306 struct q_inval *qi; /* Queued invalidation info */
307#ifdef CONFIG_INTR_REMAP
308 struct ir_table *ir_table; /* Interrupt remapping info */
309#endif
310};
311
312static inline void __iommu_flush_cache(
313 struct intel_iommu *iommu, void *addr, int size)
314{
315 if (!ecap_coherent(iommu->ecap))
316 clflush_cache_range(addr, size);
317}
318
319extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
320
321extern int alloc_iommu(struct dmar_drhd_unit *drhd);
322extern void free_iommu(struct intel_iommu *iommu);
323extern int dmar_enable_qi(struct intel_iommu *iommu);
324extern void qi_global_iec(struct intel_iommu *iommu);
325
326extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
327 u8 fm, u64 type, int non_present_entry_flush);
328extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
329 unsigned int size_order, u64 type,
330 int non_present_entry_flush);
331
332extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
333
334extern void *intel_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
335extern void intel_free_coherent(struct device *, size_t, void *, dma_addr_t);
336extern dma_addr_t intel_map_single(struct device *, phys_addr_t, size_t, int);
337extern void intel_unmap_single(struct device *, dma_addr_t, size_t, int);
338extern int intel_map_sg(struct device *, struct scatterlist *, int, int);
339extern void intel_unmap_sg(struct device *, struct scatterlist *, int, int);
340
341#endif