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1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
23
24#include <linux/device.h>
25#include <linux/uio.h>
26#include <linux/kref.h>
27#include <linux/completion.h>
28#include <linux/rcupdate.h>
29#include <linux/dma-mapping.h>
30
31/**
32 * typedef dma_cookie_t - an opaque DMA cookie
33 *
34 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
35 */
36typedef s32 dma_cookie_t;
37
38#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
39
40/**
41 * enum dma_status - DMA transaction status
42 * @DMA_SUCCESS: transaction completed successfully
43 * @DMA_IN_PROGRESS: transaction not yet processed
44 * @DMA_ERROR: transaction failed
45 */
46enum dma_status {
47 DMA_SUCCESS,
48 DMA_IN_PROGRESS,
49 DMA_ERROR,
50};
51
52/**
53 * enum dma_transaction_type - DMA transaction types/indexes
54 */
55enum dma_transaction_type {
56 DMA_MEMCPY,
57 DMA_XOR,
58 DMA_PQ_XOR,
59 DMA_DUAL_XOR,
60 DMA_PQ_UPDATE,
61 DMA_ZERO_SUM,
62 DMA_PQ_ZERO_SUM,
63 DMA_MEMSET,
64 DMA_MEMCPY_CRC32C,
65 DMA_INTERRUPT,
66 DMA_PRIVATE,
67 DMA_SLAVE,
68};
69
70/* last transaction type for creation of the capabilities mask */
71#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
72
73
74/**
75 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
76 * control completion, and communicate status.
77 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
78 * this transaction
79 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
80 * acknowledges receipt, i.e. has has a chance to establish any
81 * dependency chains
82 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
83 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
84 */
85enum dma_ctrl_flags {
86 DMA_PREP_INTERRUPT = (1 << 0),
87 DMA_CTRL_ACK = (1 << 1),
88 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
89 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
90};
91
92/**
93 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
94 * See linux/cpumask.h
95 */
96typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
97
98/**
99 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
100 * @refcount: local_t used for open-coded "bigref" counting
101 * @memcpy_count: transaction counter
102 * @bytes_transferred: byte counter
103 */
104
105struct dma_chan_percpu {
106 /* stats */
107 unsigned long memcpy_count;
108 unsigned long bytes_transferred;
109};
110
111/**
112 * struct dma_chan - devices supply DMA channels, clients use them
113 * @device: ptr to the dma device who supplies this channel, always !%NULL
114 * @cookie: last cookie value returned to client
115 * @chan_id: channel ID for sysfs
116 * @dev: class device for sysfs
117 * @refcount: kref, used in "bigref" slow-mode
118 * @slow_ref: indicates that the DMA channel is free
119 * @rcu: the DMA channel's RCU head
120 * @device_node: used to add this to the device chan list
121 * @local: per-cpu pointer to a struct dma_chan_percpu
122 * @client-count: how many clients are using this channel
123 * @table_count: number of appearances in the mem-to-mem allocation table
124 * @private: private data for certain client-channel associations
125 */
126struct dma_chan {
127 struct dma_device *device;
128 dma_cookie_t cookie;
129
130 /* sysfs */
131 int chan_id;
132 struct dma_chan_dev *dev;
133
134 struct list_head device_node;
135 struct dma_chan_percpu *local;
136 int client_count;
137 int table_count;
138 void *private;
139};
140
141/**
142 * struct dma_chan_dev - relate sysfs device node to backing channel device
143 * @chan - driver channel device
144 * @device - sysfs device
145 * @dev_id - parent dma_device dev_id
146 * @idr_ref - reference count to gate release of dma_device dev_id
147 */
148struct dma_chan_dev {
149 struct dma_chan *chan;
150 struct device device;
151 int dev_id;
152 atomic_t *idr_ref;
153};
154
155static inline const char *dma_chan_name(struct dma_chan *chan)
156{
157 return dev_name(&chan->dev->device);
158}
159
160void dma_chan_cleanup(struct kref *kref);
161
162/**
163 * typedef dma_filter_fn - callback filter for dma_request_channel
164 * @chan: channel to be reviewed
165 * @filter_param: opaque parameter passed through dma_request_channel
166 *
167 * When this optional parameter is specified in a call to dma_request_channel a
168 * suitable channel is passed to this routine for further dispositioning before
169 * being returned. Where 'suitable' indicates a non-busy channel that
170 * satisfies the given capability mask. It returns 'true' to indicate that the
171 * channel is suitable.
172 */
173typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
174
175typedef void (*dma_async_tx_callback)(void *dma_async_param);
176/**
177 * struct dma_async_tx_descriptor - async transaction descriptor
178 * ---dma generic offload fields---
179 * @cookie: tracking cookie for this transaction, set to -EBUSY if
180 * this tx is sitting on a dependency list
181 * @flags: flags to augment operation preparation, control completion, and
182 * communicate status
183 * @phys: physical address of the descriptor
184 * @tx_list: driver common field for operations that require multiple
185 * descriptors
186 * @chan: target channel for this operation
187 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
188 * @callback: routine to call after this operation is complete
189 * @callback_param: general parameter to pass to the callback routine
190 * ---async_tx api specific fields---
191 * @next: at completion submit this descriptor
192 * @parent: pointer to the next level up in the dependency chain
193 * @lock: protect the parent and next pointers
194 */
195struct dma_async_tx_descriptor {
196 dma_cookie_t cookie;
197 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
198 dma_addr_t phys;
199 struct list_head tx_list;
200 struct dma_chan *chan;
201 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
202 dma_async_tx_callback callback;
203 void *callback_param;
204 struct dma_async_tx_descriptor *next;
205 struct dma_async_tx_descriptor *parent;
206 spinlock_t lock;
207};
208
209/**
210 * struct dma_device - info on the entity supplying DMA services
211 * @chancnt: how many DMA channels are supported
212 * @channels: the list of struct dma_chan
213 * @global_node: list_head for global dma_device_list
214 * @cap_mask: one or more dma_capability flags
215 * @max_xor: maximum number of xor sources, 0 if no capability
216 * @refcount: reference count
217 * @done: IO completion struct
218 * @dev_id: unique device ID
219 * @dev: struct device reference for dma mapping api
220 * @device_alloc_chan_resources: allocate resources and return the
221 * number of allocated descriptors
222 * @device_free_chan_resources: release DMA channel's resources
223 * @device_prep_dma_memcpy: prepares a memcpy operation
224 * @device_prep_dma_xor: prepares a xor operation
225 * @device_prep_dma_zero_sum: prepares a zero_sum operation
226 * @device_prep_dma_memset: prepares a memset operation
227 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
228 * @device_prep_slave_sg: prepares a slave dma operation
229 * @device_terminate_all: terminate all pending operations
230 * @device_issue_pending: push pending transactions to hardware
231 */
232struct dma_device {
233
234 unsigned int chancnt;
235 struct list_head channels;
236 struct list_head global_node;
237 dma_cap_mask_t cap_mask;
238 int max_xor;
239
240 int dev_id;
241 struct device *dev;
242
243 int (*device_alloc_chan_resources)(struct dma_chan *chan);
244 void (*device_free_chan_resources)(struct dma_chan *chan);
245
246 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
247 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
248 size_t len, unsigned long flags);
249 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
250 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
251 unsigned int src_cnt, size_t len, unsigned long flags);
252 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
253 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
254 size_t len, u32 *result, unsigned long flags);
255 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
256 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
257 unsigned long flags);
258 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
259 struct dma_chan *chan, unsigned long flags);
260
261 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
262 struct dma_chan *chan, struct scatterlist *sgl,
263 unsigned int sg_len, enum dma_data_direction direction,
264 unsigned long flags);
265 void (*device_terminate_all)(struct dma_chan *chan);
266
267 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
268 dma_cookie_t cookie, dma_cookie_t *last,
269 dma_cookie_t *used);
270 void (*device_issue_pending)(struct dma_chan *chan);
271};
272
273/* --- public DMA engine API --- */
274
275#ifdef CONFIG_DMA_ENGINE
276void dmaengine_get(void);
277void dmaengine_put(void);
278#else
279static inline void dmaengine_get(void)
280{
281}
282static inline void dmaengine_put(void)
283{
284}
285#endif
286
287#ifdef CONFIG_NET_DMA
288#define net_dmaengine_get() dmaengine_get()
289#define net_dmaengine_put() dmaengine_put()
290#else
291static inline void net_dmaengine_get(void)
292{
293}
294static inline void net_dmaengine_put(void)
295{
296}
297#endif
298
299dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
300 void *dest, void *src, size_t len);
301dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
302 struct page *page, unsigned int offset, void *kdata, size_t len);
303dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
304 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
305 unsigned int src_off, size_t len);
306void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
307 struct dma_chan *chan);
308
309static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
310{
311 tx->flags |= DMA_CTRL_ACK;
312}
313
314static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
315{
316 tx->flags &= ~DMA_CTRL_ACK;
317}
318
319static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
320{
321 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
322}
323
324#define first_dma_cap(mask) __first_dma_cap(&(mask))
325static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
326{
327 return min_t(int, DMA_TX_TYPE_END,
328 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
329}
330
331#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
332static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
333{
334 return min_t(int, DMA_TX_TYPE_END,
335 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
336}
337
338#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
339static inline void
340__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
341{
342 set_bit(tx_type, dstp->bits);
343}
344
345#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
346static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
347{
348 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
349}
350
351#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
352static inline int
353__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
354{
355 return test_bit(tx_type, srcp->bits);
356}
357
358#define for_each_dma_cap_mask(cap, mask) \
359 for ((cap) = first_dma_cap(mask); \
360 (cap) < DMA_TX_TYPE_END; \
361 (cap) = next_dma_cap((cap), (mask)))
362
363/**
364 * dma_async_issue_pending - flush pending transactions to HW
365 * @chan: target DMA channel
366 *
367 * This allows drivers to push copies to HW in batches,
368 * reducing MMIO writes where possible.
369 */
370static inline void dma_async_issue_pending(struct dma_chan *chan)
371{
372 chan->device->device_issue_pending(chan);
373}
374
375#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
376
377/**
378 * dma_async_is_tx_complete - poll for transaction completion
379 * @chan: DMA channel
380 * @cookie: transaction identifier to check status of
381 * @last: returns last completed cookie, can be NULL
382 * @used: returns last issued cookie, can be NULL
383 *
384 * If @last and @used are passed in, upon return they reflect the driver
385 * internal state and can be used with dma_async_is_complete() to check
386 * the status of multiple cookies without re-checking hardware state.
387 */
388static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
389 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
390{
391 return chan->device->device_is_tx_complete(chan, cookie, last, used);
392}
393
394#define dma_async_memcpy_complete(chan, cookie, last, used)\
395 dma_async_is_tx_complete(chan, cookie, last, used)
396
397/**
398 * dma_async_is_complete - test a cookie against chan state
399 * @cookie: transaction identifier to test status of
400 * @last_complete: last know completed transaction
401 * @last_used: last cookie value handed out
402 *
403 * dma_async_is_complete() is used in dma_async_memcpy_complete()
404 * the test logic is separated for lightweight testing of multiple cookies
405 */
406static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
407 dma_cookie_t last_complete, dma_cookie_t last_used)
408{
409 if (last_complete <= last_used) {
410 if ((cookie <= last_complete) || (cookie > last_used))
411 return DMA_SUCCESS;
412 } else {
413 if ((cookie <= last_complete) && (cookie > last_used))
414 return DMA_SUCCESS;
415 }
416 return DMA_IN_PROGRESS;
417}
418
419enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
420#ifdef CONFIG_DMA_ENGINE
421enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
422void dma_issue_pending_all(void);
423#else
424static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
425{
426 return DMA_SUCCESS;
427}
428static inline void dma_issue_pending_all(void)
429{
430 do { } while (0);
431}
432#endif
433
434/* --- DMA device --- */
435
436int dma_async_device_register(struct dma_device *device);
437void dma_async_device_unregister(struct dma_device *device);
438void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
439struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
440#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
441struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
442void dma_release_channel(struct dma_chan *chan);
443
444/* --- Helper iov-locking functions --- */
445
446struct dma_page_list {
447 char __user *base_address;
448 int nr_pages;
449 struct page **pages;
450};
451
452struct dma_pinned_list {
453 int nr_iovecs;
454 struct dma_page_list page_list[0];
455};
456
457struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
458void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
459
460dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
461 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
462dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
463 struct dma_pinned_list *pinned_list, struct page *page,
464 unsigned int offset, size_t len);
465
466#endif /* DMAENGINE_H */