tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
17/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
23#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24#define BCM_VLAN 1
25#endif
26
27
28/* error/debug prints */
29
30#define DRV_MODULE_NAME "bnx2x"
31#define PFX DRV_MODULE_NAME ": "
32
33/* for messages that are currently off */
34#define BNX2X_MSG_OFF 0
35#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
36#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
37#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
38#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
39#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
40#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
41
42#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
43
44/* regular debug print */
45#define DP(__mask, __fmt, __args...) do { \
46 if (bp->msglevel & (__mask)) \
47 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
48 bp->dev ? (bp->dev->name) : "?", ##__args); \
49 } while (0)
50
51/* errors debug print */
52#define BNX2X_DBG_ERR(__fmt, __args...) do { \
53 if (bp->msglevel & NETIF_MSG_PROBE) \
54 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
55 bp->dev ? (bp->dev->name) : "?", ##__args); \
56 } while (0)
57
58/* for errors (never masked) */
59#define BNX2X_ERR(__fmt, __args...) do { \
60 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
61 bp->dev ? (bp->dev->name) : "?", ##__args); \
62 } while (0)
63
64/* before we have a dev->name use dev_info() */
65#define BNX2X_DEV_INFO(__fmt, __args...) do { \
66 if (bp->msglevel & NETIF_MSG_PROBE) \
67 dev_info(&bp->pdev->dev, __fmt, ##__args); \
68 } while (0)
69
70
71#ifdef BNX2X_STOP_ON_ERROR
72#define bnx2x_panic() do { \
73 bp->panic = 1; \
74 BNX2X_ERR("driver assert\n"); \
75 bnx2x_int_disable(bp); \
76 bnx2x_panic_dump(bp); \
77 } while (0)
78#else
79#define bnx2x_panic() do { \
80 BNX2X_ERR("driver assert\n"); \
81 bnx2x_panic_dump(bp); \
82 } while (0)
83#endif
84
85
86#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
87#define U64_HI(x) (u32)(((u64)(x)) >> 32)
88#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
89
90
91#define REG_ADDR(bp, offset) (bp->regview + offset)
92
93#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
94#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
95#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
96
97#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
98#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
99#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
100#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
101
102#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
103#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
104
105#define REG_RD_DMAE(bp, offset, valp, len32) \
106 do { \
107 bnx2x_read_dmae(bp, offset, len32);\
108 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
109 } while (0)
110
111#define REG_WR_DMAE(bp, offset, valp, len32) \
112 do { \
113 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
114 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
115 offset, len32); \
116 } while (0)
117
118#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
119 offsetof(struct shmem_region, field))
120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122
123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
124#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
125
126
127/* fast path */
128
129struct sw_rx_bd {
130 struct sk_buff *skb;
131 DECLARE_PCI_UNMAP_ADDR(mapping)
132};
133
134struct sw_tx_bd {
135 struct sk_buff *skb;
136 u16 first_bd;
137};
138
139struct sw_rx_page {
140 struct page *page;
141 DECLARE_PCI_UNMAP_ADDR(mapping)
142};
143
144
145/* MC hsi */
146#define BCM_PAGE_SHIFT 12
147#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
148#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
149#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
150
151#define PAGES_PER_SGE_SHIFT 0
152#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
153#define SGE_PAGE_SIZE PAGE_SIZE
154#define SGE_PAGE_SHIFT PAGE_SHIFT
155#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
156
157#define BCM_RX_ETH_PAYLOAD_ALIGN 64
158
159/* SGE ring related macros */
160#define NUM_RX_SGE_PAGES 2
161#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
162#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
163/* RX_SGE_CNT is promised to be a power of 2 */
164#define RX_SGE_MASK (RX_SGE_CNT - 1)
165#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
166#define MAX_RX_SGE (NUM_RX_SGE - 1)
167#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
168 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
169#define RX_SGE(x) ((x) & MAX_RX_SGE)
170
171/* SGE producer mask related macros */
172/* Number of bits in one sge_mask array element */
173#define RX_SGE_MASK_ELEM_SZ 64
174#define RX_SGE_MASK_ELEM_SHIFT 6
175#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
176
177/* Creates a bitmask of all ones in less significant bits.
178 idx - index of the most significant bit in the created mask */
179#define RX_SGE_ONES_MASK(idx) \
180 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
181#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
182
183/* Number of u64 elements in SGE mask array */
184#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
185 RX_SGE_MASK_ELEM_SZ)
186#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
187#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
188
189
190struct bnx2x_fastpath {
191
192 struct napi_struct napi;
193
194 struct host_status_block *status_blk;
195 dma_addr_t status_blk_mapping;
196
197 struct eth_tx_db_data *hw_tx_prods;
198 dma_addr_t tx_prods_mapping;
199
200 struct sw_tx_bd *tx_buf_ring;
201
202 struct eth_tx_bd *tx_desc_ring;
203 dma_addr_t tx_desc_mapping;
204
205 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
206 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
207
208 struct eth_rx_bd *rx_desc_ring;
209 dma_addr_t rx_desc_mapping;
210
211 union eth_rx_cqe *rx_comp_ring;
212 dma_addr_t rx_comp_mapping;
213
214 /* SGE ring */
215 struct eth_rx_sge *rx_sge_ring;
216 dma_addr_t rx_sge_mapping;
217
218 u64 sge_mask[RX_SGE_MASK_LEN];
219
220 int state;
221#define BNX2X_FP_STATE_CLOSED 0
222#define BNX2X_FP_STATE_IRQ 0x80000
223#define BNX2X_FP_STATE_OPENING 0x90000
224#define BNX2X_FP_STATE_OPEN 0xa0000
225#define BNX2X_FP_STATE_HALTING 0xb0000
226#define BNX2X_FP_STATE_HALTED 0xc0000
227
228 u8 index; /* number in fp array */
229 u8 cl_id; /* eth client id */
230 u8 sb_id; /* status block number in HW */
231#define FP_IDX(fp) (fp->index)
232#define FP_CL_ID(fp) (fp->cl_id)
233#define BP_CL_ID(bp) (bp->fp[0].cl_id)
234#define FP_SB_ID(fp) (fp->sb_id)
235#define CNIC_SB_ID 0
236
237 u16 tx_pkt_prod;
238 u16 tx_pkt_cons;
239 u16 tx_bd_prod;
240 u16 tx_bd_cons;
241 u16 *tx_cons_sb;
242
243 u16 fp_c_idx;
244 u16 fp_u_idx;
245
246 u16 rx_bd_prod;
247 u16 rx_bd_cons;
248 u16 rx_comp_prod;
249 u16 rx_comp_cons;
250 u16 rx_sge_prod;
251 /* The last maximal completed SGE */
252 u16 last_max_sge;
253 u16 *rx_cons_sb;
254 u16 *rx_bd_cons_sb;
255
256 unsigned long tx_pkt,
257 rx_pkt,
258 rx_calls;
259 /* TPA related */
260 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
261 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
262#define BNX2X_TPA_START 1
263#define BNX2X_TPA_STOP 2
264 u8 disable_tpa;
265#ifdef BNX2X_STOP_ON_ERROR
266 u64 tpa_queue_used;
267#endif
268
269 struct bnx2x *bp; /* parent */
270};
271
272#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
273
274#define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))
275
276
277/* MC hsi */
278#define MAX_FETCH_BD 13 /* HW max BDs per packet */
279#define RX_COPY_THRESH 92
280
281#define NUM_TX_RINGS 16
282#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
283#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
284#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
285#define MAX_TX_BD (NUM_TX_BD - 1)
286#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
287#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
288 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
289#define TX_BD(x) ((x) & MAX_TX_BD)
290#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
291
292/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
293#define NUM_RX_RINGS 8
294#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
295#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
296#define RX_DESC_MASK (RX_DESC_CNT - 1)
297#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
298#define MAX_RX_BD (NUM_RX_BD - 1)
299#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
300#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
301 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
302#define RX_BD(x) ((x) & MAX_RX_BD)
303
304/* As long as CQE is 4 times bigger than BD entry we have to allocate
305 4 times more pages for CQ ring in order to keep it balanced with
306 BD ring */
307#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
308#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
309#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
310#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
311#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
312#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
313#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
314 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
315#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
316
317
318/* This is needed for determining of last_max */
319#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
320
321#define __SGE_MASK_SET_BIT(el, bit) \
322 do { \
323 el = ((el) | ((u64)0x1 << (bit))); \
324 } while (0)
325
326#define __SGE_MASK_CLEAR_BIT(el, bit) \
327 do { \
328 el = ((el) & (~((u64)0x1 << (bit)))); \
329 } while (0)
330
331#define SGE_MASK_SET_BIT(fp, idx) \
332 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
333 ((idx) & RX_SGE_MASK_ELEM_MASK))
334
335#define SGE_MASK_CLEAR_BIT(fp, idx) \
336 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
337 ((idx) & RX_SGE_MASK_ELEM_MASK))
338
339
340/* used on a CID received from the HW */
341#define SW_CID(x) (le32_to_cpu(x) & \
342 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
343#define CQE_CMD(x) (le32_to_cpu(x) >> \
344 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
345
346#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
347 le32_to_cpu((bd)->addr_lo))
348#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
349
350
351#define DPM_TRIGER_TYPE 0x40
352#define DOORBELL(bp, cid, val) \
353 do { \
354 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
355 DPM_TRIGER_TYPE); \
356 } while (0)
357
358
359/* TX CSUM helpers */
360#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
361 skb->csum_offset)
362#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
363 skb->csum_offset))
364
365#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
366
367#define XMIT_PLAIN 0
368#define XMIT_CSUM_V4 0x1
369#define XMIT_CSUM_V6 0x2
370#define XMIT_CSUM_TCP 0x4
371#define XMIT_GSO_V4 0x8
372#define XMIT_GSO_V6 0x10
373
374#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
375#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
376
377
378/* stuff added to make the code fit 80Col */
379
380#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
381
382#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
383#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
384#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
385 (TPA_TYPE_START | TPA_TYPE_END))
386
387#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
388
389#define BNX2X_IP_CSUM_ERR(cqe) \
390 (!((cqe)->fast_path_cqe.status_flags & \
391 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
392 ((cqe)->fast_path_cqe.type_error_flags & \
393 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
394
395#define BNX2X_L4_CSUM_ERR(cqe) \
396 (!((cqe)->fast_path_cqe.status_flags & \
397 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
398 ((cqe)->fast_path_cqe.type_error_flags & \
399 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
400
401#define BNX2X_RX_CSUM_OK(cqe) \
402 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
403
404#define BNX2X_RX_SUM_FIX(cqe) \
405 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
406 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
407 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
408
409
410#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
411#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
412
413#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
414#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
415#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
416
417#define BNX2X_RX_SB_INDEX \
418 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
419
420#define BNX2X_RX_SB_BD_INDEX \
421 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
422
423#define BNX2X_RX_SB_INDEX_NUM \
424 (((U_SB_ETH_RX_CQ_INDEX << \
425 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
426 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
427 ((U_SB_ETH_RX_BD_INDEX << \
428 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
429 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
430
431#define BNX2X_TX_SB_INDEX \
432 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
433
434
435/* end of fast path */
436
437/* common */
438
439struct bnx2x_common {
440
441 u32 chip_id;
442/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
443#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
444
445#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
446#define CHIP_NUM_57710 0x164e
447#define CHIP_NUM_57711 0x164f
448#define CHIP_NUM_57711E 0x1650
449#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
450#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
451#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
452#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
453 CHIP_IS_57711E(bp))
454#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
455
456#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
457#define CHIP_REV_Ax 0x00000000
458/* assume maximum 5 revisions */
459#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
460/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
461#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
462 !(CHIP_REV(bp) & 0x00001000))
463/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
464#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
465 (CHIP_REV(bp) & 0x00001000))
466
467#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
468 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
469
470#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
471#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
472
473 int flash_size;
474#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
475#define NVRAM_TIMEOUT_COUNT 30000
476#define NVRAM_PAGE_SIZE 256
477
478 u32 shmem_base;
479
480 u32 hw_config;
481 u32 board;
482
483 u32 bc_ver;
484
485 char *name;
486};
487
488
489/* end of common */
490
491/* port */
492
493struct nig_stats {
494 u32 brb_discard;
495 u32 brb_packet;
496 u32 brb_truncate;
497 u32 flow_ctrl_discard;
498 u32 flow_ctrl_octets;
499 u32 flow_ctrl_packet;
500 u32 mng_discard;
501 u32 mng_octet_inp;
502 u32 mng_octet_out;
503 u32 mng_packet_inp;
504 u32 mng_packet_out;
505 u32 pbf_octets;
506 u32 pbf_packet;
507 u32 safc_inp;
508 u32 egress_mac_pkt0_lo;
509 u32 egress_mac_pkt0_hi;
510 u32 egress_mac_pkt1_lo;
511 u32 egress_mac_pkt1_hi;
512};
513
514struct bnx2x_port {
515 u32 pmf;
516
517 u32 link_config;
518
519 u32 supported;
520/* link settings - missing defines */
521#define SUPPORTED_2500baseX_Full (1 << 15)
522
523 u32 advertising;
524/* link settings - missing defines */
525#define ADVERTISED_2500baseX_Full (1 << 15)
526
527 u32 phy_addr;
528
529 /* used to synchronize phy accesses */
530 struct mutex phy_mutex;
531
532 u32 port_stx;
533
534 struct nig_stats old_nig_stats;
535};
536
537/* end of port */
538
539
540enum bnx2x_stats_event {
541 STATS_EVENT_PMF = 0,
542 STATS_EVENT_LINK_UP,
543 STATS_EVENT_UPDATE,
544 STATS_EVENT_STOP,
545 STATS_EVENT_MAX
546};
547
548enum bnx2x_stats_state {
549 STATS_STATE_DISABLED = 0,
550 STATS_STATE_ENABLED,
551 STATS_STATE_MAX
552};
553
554struct bnx2x_eth_stats {
555 u32 total_bytes_received_hi;
556 u32 total_bytes_received_lo;
557 u32 total_bytes_transmitted_hi;
558 u32 total_bytes_transmitted_lo;
559 u32 total_unicast_packets_received_hi;
560 u32 total_unicast_packets_received_lo;
561 u32 total_multicast_packets_received_hi;
562 u32 total_multicast_packets_received_lo;
563 u32 total_broadcast_packets_received_hi;
564 u32 total_broadcast_packets_received_lo;
565 u32 total_unicast_packets_transmitted_hi;
566 u32 total_unicast_packets_transmitted_lo;
567 u32 total_multicast_packets_transmitted_hi;
568 u32 total_multicast_packets_transmitted_lo;
569 u32 total_broadcast_packets_transmitted_hi;
570 u32 total_broadcast_packets_transmitted_lo;
571 u32 valid_bytes_received_hi;
572 u32 valid_bytes_received_lo;
573
574 u32 error_bytes_received_hi;
575 u32 error_bytes_received_lo;
576
577 u32 rx_stat_ifhcinbadoctets_hi;
578 u32 rx_stat_ifhcinbadoctets_lo;
579 u32 tx_stat_ifhcoutbadoctets_hi;
580 u32 tx_stat_ifhcoutbadoctets_lo;
581 u32 rx_stat_dot3statsfcserrors_hi;
582 u32 rx_stat_dot3statsfcserrors_lo;
583 u32 rx_stat_dot3statsalignmenterrors_hi;
584 u32 rx_stat_dot3statsalignmenterrors_lo;
585 u32 rx_stat_dot3statscarriersenseerrors_hi;
586 u32 rx_stat_dot3statscarriersenseerrors_lo;
587 u32 rx_stat_falsecarriererrors_hi;
588 u32 rx_stat_falsecarriererrors_lo;
589 u32 rx_stat_etherstatsundersizepkts_hi;
590 u32 rx_stat_etherstatsundersizepkts_lo;
591 u32 rx_stat_dot3statsframestoolong_hi;
592 u32 rx_stat_dot3statsframestoolong_lo;
593 u32 rx_stat_etherstatsfragments_hi;
594 u32 rx_stat_etherstatsfragments_lo;
595 u32 rx_stat_etherstatsjabbers_hi;
596 u32 rx_stat_etherstatsjabbers_lo;
597 u32 rx_stat_maccontrolframesreceived_hi;
598 u32 rx_stat_maccontrolframesreceived_lo;
599 u32 rx_stat_bmac_xpf_hi;
600 u32 rx_stat_bmac_xpf_lo;
601 u32 rx_stat_bmac_xcf_hi;
602 u32 rx_stat_bmac_xcf_lo;
603 u32 rx_stat_xoffstateentered_hi;
604 u32 rx_stat_xoffstateentered_lo;
605 u32 rx_stat_xonpauseframesreceived_hi;
606 u32 rx_stat_xonpauseframesreceived_lo;
607 u32 rx_stat_xoffpauseframesreceived_hi;
608 u32 rx_stat_xoffpauseframesreceived_lo;
609 u32 tx_stat_outxonsent_hi;
610 u32 tx_stat_outxonsent_lo;
611 u32 tx_stat_outxoffsent_hi;
612 u32 tx_stat_outxoffsent_lo;
613 u32 tx_stat_flowcontroldone_hi;
614 u32 tx_stat_flowcontroldone_lo;
615 u32 tx_stat_etherstatscollisions_hi;
616 u32 tx_stat_etherstatscollisions_lo;
617 u32 tx_stat_dot3statssinglecollisionframes_hi;
618 u32 tx_stat_dot3statssinglecollisionframes_lo;
619 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
620 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
621 u32 tx_stat_dot3statsdeferredtransmissions_hi;
622 u32 tx_stat_dot3statsdeferredtransmissions_lo;
623 u32 tx_stat_dot3statsexcessivecollisions_hi;
624 u32 tx_stat_dot3statsexcessivecollisions_lo;
625 u32 tx_stat_dot3statslatecollisions_hi;
626 u32 tx_stat_dot3statslatecollisions_lo;
627 u32 tx_stat_etherstatspkts64octets_hi;
628 u32 tx_stat_etherstatspkts64octets_lo;
629 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
630 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
631 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
632 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
633 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
634 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
635 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
636 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
637 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
638 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
639 u32 tx_stat_etherstatspktsover1522octets_hi;
640 u32 tx_stat_etherstatspktsover1522octets_lo;
641 u32 tx_stat_bmac_2047_hi;
642 u32 tx_stat_bmac_2047_lo;
643 u32 tx_stat_bmac_4095_hi;
644 u32 tx_stat_bmac_4095_lo;
645 u32 tx_stat_bmac_9216_hi;
646 u32 tx_stat_bmac_9216_lo;
647 u32 tx_stat_bmac_16383_hi;
648 u32 tx_stat_bmac_16383_lo;
649 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
650 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
651 u32 tx_stat_bmac_ufl_hi;
652 u32 tx_stat_bmac_ufl_lo;
653
654 u32 brb_drop_hi;
655 u32 brb_drop_lo;
656 u32 brb_truncate_hi;
657 u32 brb_truncate_lo;
658
659 u32 jabber_packets_received;
660
661 u32 etherstatspkts1024octetsto1522octets_hi;
662 u32 etherstatspkts1024octetsto1522octets_lo;
663 u32 etherstatspktsover1522octets_hi;
664 u32 etherstatspktsover1522octets_lo;
665
666 u32 no_buff_discard;
667
668 u32 mac_filter_discard;
669 u32 xxoverflow_discard;
670 u32 brb_truncate_discard;
671 u32 mac_discard;
672
673 u32 driver_xoff;
674 u32 rx_err_discard_pkt;
675 u32 rx_skb_alloc_failed;
676 u32 hw_csum_err;
677};
678
679#define STATS_OFFSET32(stat_name) \
680 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
681
682
683#ifdef BNX2X_MULTI
684#define MAX_CONTEXT 16
685#else
686#define MAX_CONTEXT 1
687#endif
688
689union cdu_context {
690 struct eth_context eth;
691 char pad[1024];
692};
693
694#define MAX_DMAE_C 8
695
696/* DMA memory not used in fastpath */
697struct bnx2x_slowpath {
698 union cdu_context context[MAX_CONTEXT];
699 struct eth_stats_query fw_stats;
700 struct mac_configuration_cmd mac_config;
701 struct mac_configuration_cmd mcast_config;
702
703 /* used by dmae command executer */
704 struct dmae_command dmae[MAX_DMAE_C];
705
706 u32 stats_comp;
707 union mac_stats mac_stats;
708 struct nig_stats nig_stats;
709 struct host_port_stats port_stats;
710 struct host_func_stats func_stats;
711
712 u32 wb_comp;
713 u32 wb_data[4];
714};
715
716#define bnx2x_sp(bp, var) (&bp->slowpath->var)
717#define bnx2x_sp_mapping(bp, var) \
718 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
719
720
721/* attn group wiring */
722#define MAX_DYNAMIC_ATTN_GRPS 8
723
724struct attn_route {
725 u32 sig[4];
726};
727
728struct bnx2x {
729 /* Fields used in the tx and intr/napi performance paths
730 * are grouped together in the beginning of the structure
731 */
732 struct bnx2x_fastpath fp[MAX_CONTEXT];
733 void __iomem *regview;
734 void __iomem *doorbells;
735#define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
736
737 struct net_device *dev;
738 struct pci_dev *pdev;
739
740 atomic_t intr_sem;
741 struct msix_entry msix_table[MAX_CONTEXT+1];
742
743 int tx_ring_size;
744
745#ifdef BCM_VLAN
746 struct vlan_group *vlgrp;
747#endif
748
749 u32 rx_csum;
750 u32 rx_offset;
751 u32 rx_buf_size;
752#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
753#define ETH_MIN_PACKET_SIZE 60
754#define ETH_MAX_PACKET_SIZE 1500
755#define ETH_MAX_JUMBO_PACKET_SIZE 9600
756
757 struct host_def_status_block *def_status_blk;
758#define DEF_SB_ID 16
759 u16 def_c_idx;
760 u16 def_u_idx;
761 u16 def_x_idx;
762 u16 def_t_idx;
763 u16 def_att_idx;
764 u32 attn_state;
765 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
766 u32 nig_mask;
767
768 /* slow path ring */
769 struct eth_spe *spq;
770 dma_addr_t spq_mapping;
771 u16 spq_prod_idx;
772 struct eth_spe *spq_prod_bd;
773 struct eth_spe *spq_last_bd;
774 u16 *dsb_sp_prod;
775 u16 spq_left; /* serialize spq */
776 /* used to synchronize spq accesses */
777 spinlock_t spq_lock;
778
779 /* Flags for marking that there is a STAT_QUERY or
780 SET_MAC ramrod pending */
781 u8 stats_pending;
782 u8 set_mac_pending;
783
784 /* End of fields used in the performance code paths */
785
786 int panic;
787 int msglevel;
788
789 u32 flags;
790#define PCIX_FLAG 1
791#define PCI_32BIT_FLAG 2
792#define ONE_TDMA_FLAG 4 /* no longer used */
793#define NO_WOL_FLAG 8
794#define USING_DAC_FLAG 0x10
795#define USING_MSIX_FLAG 0x20
796#define ASF_ENABLE_FLAG 0x40
797#define TPA_ENABLE_FLAG 0x80
798#define NO_MCP_FLAG 0x100
799#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
800#define HW_VLAN_TX_FLAG 0x400
801#define HW_VLAN_RX_FLAG 0x800
802
803 int func;
804#define BP_PORT(bp) (bp->func % PORT_MAX)
805#define BP_FUNC(bp) (bp->func)
806#define BP_E1HVN(bp) (bp->func >> 1)
807#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
808
809 int pm_cap;
810 int pcie_cap;
811
812 struct delayed_work sp_task;
813 struct work_struct reset_task;
814
815 struct timer_list timer;
816 int timer_interval;
817 int current_interval;
818
819 u16 fw_seq;
820 u16 fw_drv_pulse_wr_seq;
821 u32 func_stx;
822
823 struct link_params link_params;
824 struct link_vars link_vars;
825
826 struct bnx2x_common common;
827 struct bnx2x_port port;
828
829 u32 mf_config;
830 u16 e1hov;
831 u8 e1hmf;
832#define IS_E1HMF(bp) (bp->e1hmf != 0)
833
834 u8 wol;
835
836 int rx_ring_size;
837
838 u16 tx_quick_cons_trip_int;
839 u16 tx_quick_cons_trip;
840 u16 tx_ticks_int;
841 u16 tx_ticks;
842
843 u16 rx_quick_cons_trip_int;
844 u16 rx_quick_cons_trip;
845 u16 rx_ticks_int;
846 u16 rx_ticks;
847
848 u32 lin_cnt;
849
850 int state;
851#define BNX2X_STATE_CLOSED 0x0
852#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
853#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
854#define BNX2X_STATE_OPEN 0x3000
855#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
856#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
857#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
858#define BNX2X_STATE_DISABLED 0xd000
859#define BNX2X_STATE_DIAG 0xe000
860#define BNX2X_STATE_ERROR 0xf000
861
862 int num_queues;
863#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
864
865 u32 rx_mode;
866#define BNX2X_RX_MODE_NONE 0
867#define BNX2X_RX_MODE_NORMAL 1
868#define BNX2X_RX_MODE_ALLMULTI 2
869#define BNX2X_RX_MODE_PROMISC 3
870#define BNX2X_MAX_MULTICAST 64
871#define BNX2X_MAX_EMUL_MULTI 16
872
873 dma_addr_t def_status_blk_mapping;
874
875 struct bnx2x_slowpath *slowpath;
876 dma_addr_t slowpath_mapping;
877
878#ifdef BCM_ISCSI
879 void *t1;
880 dma_addr_t t1_mapping;
881 void *t2;
882 dma_addr_t t2_mapping;
883 void *timers;
884 dma_addr_t timers_mapping;
885 void *qm;
886 dma_addr_t qm_mapping;
887#endif
888
889 int dmae_ready;
890 /* used to synchronize dmae accesses */
891 struct mutex dmae_mutex;
892 struct dmae_command init_dmae;
893
894 /* used to synchronize stats collecting */
895 int stats_state;
896 /* used by dmae command loader */
897 struct dmae_command stats_dmae;
898 int executer_idx;
899
900 u16 stats_counter;
901 struct tstorm_per_client_stats old_tclient;
902 struct xstorm_per_client_stats old_xclient;
903 struct bnx2x_eth_stats eth_stats;
904
905 struct z_stream_s *strm;
906 void *gunzip_buf;
907 dma_addr_t gunzip_mapping;
908 int gunzip_outlen;
909#define FW_BUF_SIZE 0x8000
910
911};
912
913
914#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
915
916#define for_each_nondefault_queue(bp, var) \
917 for (var = 1; var < bp->num_queues; var++)
918#define is_multi(bp) (bp->num_queues > 1)
919
920
921void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
922void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
923 u32 len32);
924int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
925
926static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
927 int wait)
928{
929 u32 val;
930
931 do {
932 val = REG_RD(bp, reg);
933 if (val == expected)
934 break;
935 ms -= wait;
936 msleep(wait);
937
938 } while (ms > 0);
939
940 return val;
941}
942
943
944/* load/unload mode */
945#define LOAD_NORMAL 0
946#define LOAD_OPEN 1
947#define LOAD_DIAG 2
948#define UNLOAD_NORMAL 0
949#define UNLOAD_CLOSE 1
950
951
952/* DMAE command defines */
953#define DMAE_CMD_SRC_PCI 0
954#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
955
956#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
957#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
958
959#define DMAE_CMD_C_DST_PCI 0
960#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
961
962#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
963
964#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
965#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
966#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
967#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
968
969#define DMAE_CMD_PORT_0 0
970#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
971
972#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
973#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
974#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
975
976#define DMAE_LEN32_RD_MAX 0x80
977#define DMAE_LEN32_WR_MAX 0x400
978
979#define DMAE_COMP_VAL 0xe0d0d0ae
980
981#define MAX_DMAE_C_PER_PORT 8
982#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
983 BP_E1HVN(bp))
984#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
985 E1HVN_MAX)
986
987
988/* PCIE link and speed */
989#define PCICFG_LINK_WIDTH 0x1f00000
990#define PCICFG_LINK_WIDTH_SHIFT 20
991#define PCICFG_LINK_SPEED 0xf0000
992#define PCICFG_LINK_SPEED_SHIFT 16
993
994
995#define BNX2X_NUM_STATS 42
996#define BNX2X_NUM_TESTS 8
997
998#define BNX2X_MAC_LOOPBACK 0
999#define BNX2X_PHY_LOOPBACK 1
1000#define BNX2X_MAC_LOOPBACK_FAILED 1
1001#define BNX2X_PHY_LOOPBACK_FAILED 2
1002#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1003 BNX2X_PHY_LOOPBACK_FAILED)
1004
1005
1006#define STROM_ASSERT_ARRAY_SIZE 50
1007
1008
1009/* must be used on a CID before placing it on a HW ring */
1010#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1011
1012#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1013#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1014
1015
1016#define BNX2X_BTR 3
1017#define MAX_SPQ_PENDING 8
1018
1019
1020/* CMNG constants
1021 derived from lab experiments, and not from system spec calculations !!! */
1022#define DEF_MIN_RATE 100
1023/* resolution of the rate shaping timer - 100 usec */
1024#define RS_PERIODIC_TIMEOUT_USEC 100
1025/* resolution of fairness algorithm in usecs -
1026 coefficient for calculating the actual t fair */
1027#define T_FAIR_COEF 10000000
1028/* number of bytes in single QM arbitration cycle -
1029 coefficient for calculating the fairness timer */
1030#define QM_ARB_BYTES 40000
1031#define FAIR_MEM 2
1032
1033
1034#define ATTN_NIG_FOR_FUNC (1L << 8)
1035#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1036#define GPIO_2_FUNC (1L << 10)
1037#define GPIO_3_FUNC (1L << 11)
1038#define GPIO_4_FUNC (1L << 12)
1039#define ATTN_GENERAL_ATTN_1 (1L << 13)
1040#define ATTN_GENERAL_ATTN_2 (1L << 14)
1041#define ATTN_GENERAL_ATTN_3 (1L << 15)
1042#define ATTN_GENERAL_ATTN_4 (1L << 13)
1043#define ATTN_GENERAL_ATTN_5 (1L << 14)
1044#define ATTN_GENERAL_ATTN_6 (1L << 15)
1045
1046#define ATTN_HARD_WIRED_MASK 0xff00
1047#define ATTENTION_ID 4
1048
1049
1050/* stuff added to make the code fit 80Col */
1051
1052#define BNX2X_PMF_LINK_ASSERT \
1053 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1054
1055#define BNX2X_MC_ASSERT_BITS \
1056 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1057 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1058 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1059 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1060
1061#define BNX2X_MCP_ASSERT \
1062 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1063
1064#define BNX2X_DOORQ_ASSERT \
1065 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1066
1067#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1068#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1069 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1070 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1071 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1072 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1073 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1074
1075#define HW_INTERRUT_ASSERT_SET_0 \
1076 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1077 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1078 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1079 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1080#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1081 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1082 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1083 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1084 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1085#define HW_INTERRUT_ASSERT_SET_1 \
1086 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1087 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1088 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1089 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1090 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1091 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1092 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1093 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1094 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1095 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1096 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1097#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1098 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1099 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1100 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1101 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1102 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1103 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1104 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1105 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1106 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1107 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1108#define HW_INTERRUT_ASSERT_SET_2 \
1109 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1110 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1111 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1112 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1113 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1114#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1115 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1116 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1117 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1118 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1119 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1120 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1121
1122
1123#define MULTI_FLAGS \
1124 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1125 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1126 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1127 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1128 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1129
1130#define MULTI_MASK 0x7f
1131
1132
1133#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1134#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1135#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1136#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1137
1138#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1139
1140#define BNX2X_SP_DSB_INDEX \
1141(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1142
1143
1144#define CAM_IS_INVALID(x) \
1145(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1146
1147#define CAM_INVALIDATE(x) \
1148 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1149
1150
1151/* Number of u32 elements in MC hash array */
1152#define MC_HASH_SIZE 8
1153#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1154 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1155
1156
1157#ifndef PXP2_REG_PXP2_INT_STS
1158#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1159#endif
1160
1161/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1162
1163#endif /* bnx2x.h */