tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Hitachi SCA HD64570 and HD64572 common driver for Linux
3 *
4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Sources of information:
11 * Hitachi HD64570 SCA User's Manual
12 * Hitachi HD64572 SCA-II User's Manual
13 *
14 * We use the following SCA memory map:
15 *
16 * Packet buffer descriptor rings - starting from winbase or win0base:
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
19 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
20 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
21 *
22 * Packet data buffers - starting from winbase + buff_offset:
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
25 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
26 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
27 */
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/slab.h>
32#include <linux/jiffies.h>
33#include <linux/types.h>
34#include <linux/fcntl.h>
35#include <linux/interrupt.h>
36#include <linux/in.h>
37#include <linux/string.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/ioport.h>
41#include <linux/bitops.h>
42
43#include <asm/system.h>
44#include <asm/uaccess.h>
45#include <asm/io.h>
46
47#include <linux/netdevice.h>
48#include <linux/skbuff.h>
49
50#include <linux/hdlc.h>
51
52#if (!defined (__HD64570_H) && !defined (__HD64572_H)) || \
53 (defined (__HD64570_H) && defined (__HD64572_H))
54#error Either hd64570.h or hd64572.h must be included
55#endif
56
57#define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
58#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
59#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
60
61#define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
62#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
63#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
64
65#ifdef __HD64570_H /* HD64570 */
66#define sca_outa(value, reg, card) sca_outw(value, reg, card)
67#define sca_ina(reg, card) sca_inw(reg, card)
68#define writea(value, ptr) writew(value, ptr)
69
70#else /* HD64572 */
71#define sca_outa(value, reg, card) sca_outl(value, reg, card)
72#define sca_ina(reg, card) sca_inl(reg, card)
73#define writea(value, ptr) writel(value, ptr)
74#endif
75
76static inline struct net_device *port_to_dev(port_t *port)
77{
78 return port->dev;
79}
80
81static inline int sca_intr_status(card_t *card)
82{
83 u8 result = 0;
84
85#ifdef __HD64570_H /* HD64570 */
86 u8 isr0 = sca_in(ISR0, card);
87 u8 isr1 = sca_in(ISR1, card);
88
89 if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
90 if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
91 if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
92 if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
93 if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
94 if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
95
96#else /* HD64572 */
97 u32 isr0 = sca_inl(ISR0, card);
98
99 if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0);
100 if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0);
101 if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1);
102 if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1);
103 if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0);
104 if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1);
105
106#endif /* HD64570 vs HD64572 */
107
108 if (!(result & SCA_INTR_DMAC_TX(0)))
109 if (sca_in(DSR_TX(0), card) & DSR_EOM)
110 result |= SCA_INTR_DMAC_TX(0);
111 if (!(result & SCA_INTR_DMAC_TX(1)))
112 if (sca_in(DSR_TX(1), card) & DSR_EOM)
113 result |= SCA_INTR_DMAC_TX(1);
114
115 return result;
116}
117
118static inline port_t* dev_to_port(struct net_device *dev)
119{
120 return dev_to_hdlc(dev)->priv;
121}
122
123static inline u16 next_desc(port_t *port, u16 desc, int transmit)
124{
125 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
126 : port_to_card(port)->rx_ring_buffers);
127}
128
129
130
131static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
132{
133 u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
134 u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
135
136 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
137 return log_node(port) * (rx_buffs + tx_buffs) +
138 transmit * rx_buffs + desc;
139}
140
141
142
143static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
144{
145 /* Descriptor offset always fits in 16 bytes */
146 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
147}
148
149
150
151static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, int transmit)
152{
153#ifdef PAGE0_ALWAYS_MAPPED
154 return (pkt_desc __iomem *)(win0base(port_to_card(port))
155 + desc_offset(port, desc, transmit));
156#else
157 return (pkt_desc __iomem *)(winbase(port_to_card(port))
158 + desc_offset(port, desc, transmit));
159#endif
160}
161
162
163
164static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
165{
166 return port_to_card(port)->buff_offset +
167 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
168}
169
170
171static inline void sca_set_carrier(port_t *port)
172{
173 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
174#ifdef DEBUG_LINK
175 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
176 port_to_dev(port)->name);
177#endif
178 netif_carrier_on(port_to_dev(port));
179 } else {
180#ifdef DEBUG_LINK
181 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
182 port_to_dev(port)->name);
183#endif
184 netif_carrier_off(port_to_dev(port));
185 }
186}
187
188
189static void sca_init_sync_port(port_t *port)
190{
191 card_t *card = port_to_card(port);
192 int transmit, i;
193
194 port->rxin = 0;
195 port->txin = 0;
196 port->txlast = 0;
197
198#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
199 openwin(card, 0);
200#endif
201
202 for (transmit = 0; transmit < 2; transmit++) {
203 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
204 u16 buffs = transmit ? card->tx_ring_buffers
205 : card->rx_ring_buffers;
206
207 for (i = 0; i < buffs; i++) {
208 pkt_desc __iomem *desc = desc_address(port, i, transmit);
209 u16 chain_off = desc_offset(port, i + 1, transmit);
210 u32 buff_off = buffer_offset(port, i, transmit);
211
212 writea(chain_off, &desc->cp);
213 writel(buff_off, &desc->bp);
214 writew(0, &desc->len);
215 writeb(0, &desc->stat);
216 }
217
218 /* DMA disable - to halt state */
219 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
220 DSR_RX(phy_node(port)), card);
221 /* software ABORT - to initial state */
222 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
223 DCR_RX(phy_node(port)), card);
224
225#ifdef __HD64570_H
226 sca_out(0, dmac + CPB, card); /* pointer base */
227#endif
228 /* current desc addr */
229 sca_outa(desc_offset(port, 0, transmit), dmac + CDAL, card);
230 if (!transmit)
231 sca_outa(desc_offset(port, buffs - 1, transmit),
232 dmac + EDAL, card);
233 else
234 sca_outa(desc_offset(port, 0, transmit), dmac + EDAL,
235 card);
236
237 /* clear frame end interrupt counter */
238 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
239 DCR_RX(phy_node(port)), card);
240
241 if (!transmit) { /* Receive */
242 /* set buffer length */
243 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
244 /* Chain mode, Multi-frame */
245 sca_out(0x14, DMR_RX(phy_node(port)), card);
246 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
247 card);
248 /* DMA enable */
249 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
250 } else { /* Transmit */
251 /* Chain mode, Multi-frame */
252 sca_out(0x14, DMR_TX(phy_node(port)), card);
253 /* enable underflow interrupts */
254 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
255 }
256 }
257 sca_set_carrier(port);
258}
259
260
261
262#ifdef NEED_SCA_MSCI_INTR
263/* MSCI interrupt service */
264static inline void sca_msci_intr(port_t *port)
265{
266 u16 msci = get_msci(port);
267 card_t* card = port_to_card(port);
268 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
269
270 /* Reset MSCI TX underrun and CDCD status bit */
271 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
272
273 if (stat & ST1_UDRN) {
274 /* TX Underrun error detected */
275 port_to_dev(port)->stats.tx_errors++;
276 port_to_dev(port)->stats.tx_fifo_errors++;
277 }
278
279 if (stat & ST1_CDCD)
280 sca_set_carrier(port);
281}
282#endif
283
284
285
286static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u16 rxin)
287{
288 struct net_device *dev = port_to_dev(port);
289 struct sk_buff *skb;
290 u16 len;
291 u32 buff;
292#ifndef ALL_PAGES_ALWAYS_MAPPED
293 u32 maxlen;
294 u8 page;
295#endif
296
297 len = readw(&desc->len);
298 skb = dev_alloc_skb(len);
299 if (!skb) {
300 dev->stats.rx_dropped++;
301 return;
302 }
303
304 buff = buffer_offset(port, rxin, 0);
305#ifndef ALL_PAGES_ALWAYS_MAPPED
306 page = buff / winsize(card);
307 buff = buff % winsize(card);
308 maxlen = winsize(card) - buff;
309
310 openwin(card, page);
311
312 if (len > maxlen) {
313 memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
314 openwin(card, page + 1);
315 memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
316 } else
317#endif
318 memcpy_fromio(skb->data, winbase(card) + buff, len);
319
320#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
321 /* select pkt_desc table page back */
322 openwin(card, 0);
323#endif
324 skb_put(skb, len);
325#ifdef DEBUG_PKT
326 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
327 debug_frame(skb);
328#endif
329 dev->stats.rx_packets++;
330 dev->stats.rx_bytes += skb->len;
331 dev->last_rx = jiffies;
332 skb->protocol = hdlc_type_trans(skb, dev);
333 netif_rx(skb);
334}
335
336
337
338/* Receive DMA interrupt service */
339static inline void sca_rx_intr(port_t *port)
340{
341 struct net_device *dev = port_to_dev(port);
342 u16 dmac = get_dmac_rx(port);
343 card_t *card = port_to_card(port);
344 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
345
346 /* Reset DSR status bits */
347 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
348 DSR_RX(phy_node(port)), card);
349
350 if (stat & DSR_BOF)
351 /* Dropped one or more frames */
352 dev->stats.rx_over_errors++;
353
354 while (1) {
355 u32 desc_off = desc_offset(port, port->rxin, 0);
356 pkt_desc __iomem *desc;
357 u32 cda = sca_ina(dmac + CDAL, card);
358
359 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
360 break; /* No frame received */
361
362 desc = desc_address(port, port->rxin, 0);
363 stat = readb(&desc->stat);
364 if (!(stat & ST_RX_EOM))
365 port->rxpart = 1; /* partial frame received */
366 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
367 dev->stats.rx_errors++;
368 if (stat & ST_RX_OVERRUN)
369 dev->stats.rx_fifo_errors++;
370 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
371 ST_RX_RESBIT)) || port->rxpart)
372 dev->stats.rx_frame_errors++;
373 else if (stat & ST_RX_CRC)
374 dev->stats.rx_crc_errors++;
375 if (stat & ST_RX_EOM)
376 port->rxpart = 0; /* received last fragment */
377 } else
378 sca_rx(card, port, desc, port->rxin);
379
380 /* Set new error descriptor address */
381 sca_outa(desc_off, dmac + EDAL, card);
382 port->rxin = next_desc(port, port->rxin, 0);
383 }
384
385 /* make sure RX DMA is enabled */
386 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
387}
388
389
390
391/* Transmit DMA interrupt service */
392static inline void sca_tx_intr(port_t *port)
393{
394 struct net_device *dev = port_to_dev(port);
395 u16 dmac = get_dmac_tx(port);
396 card_t* card = port_to_card(port);
397 u8 stat;
398
399 spin_lock(&port->lock);
400
401 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
402
403 /* Reset DSR status bits */
404 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
405 DSR_TX(phy_node(port)), card);
406
407 while (1) {
408 pkt_desc __iomem *desc;
409
410 u32 desc_off = desc_offset(port, port->txlast, 1);
411 u32 cda = sca_ina(dmac + CDAL, card);
412 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
413 break; /* Transmitter is/will_be sending this frame */
414
415 desc = desc_address(port, port->txlast, 1);
416 dev->stats.tx_packets++;
417 dev->stats.tx_bytes += readw(&desc->len);
418 writeb(0, &desc->stat); /* Free descriptor */
419 port->txlast = next_desc(port, port->txlast, 1);
420 }
421
422 netif_wake_queue(dev);
423 spin_unlock(&port->lock);
424}
425
426
427
428static irqreturn_t sca_intr(int irq, void* dev_id)
429{
430 card_t *card = dev_id;
431 int i;
432 u8 stat;
433 int handled = 0;
434
435#ifndef ALL_PAGES_ALWAYS_MAPPED
436 u8 page = sca_get_page(card);
437#endif
438
439 while((stat = sca_intr_status(card)) != 0) {
440 handled = 1;
441 for (i = 0; i < 2; i++) {
442 port_t *port = get_port(card, i);
443 if (port) {
444 if (stat & SCA_INTR_MSCI(i))
445 sca_msci_intr(port);
446
447 if (stat & SCA_INTR_DMAC_RX(i))
448 sca_rx_intr(port);
449
450 if (stat & SCA_INTR_DMAC_TX(i))
451 sca_tx_intr(port);
452 }
453 }
454 }
455
456#ifndef ALL_PAGES_ALWAYS_MAPPED
457 openwin(card, page); /* Restore original page */
458#endif
459 return IRQ_RETVAL(handled);
460}
461
462
463
464static void sca_set_port(port_t *port)
465{
466 card_t* card = port_to_card(port);
467 u16 msci = get_msci(port);
468 u8 md2 = sca_in(msci + MD2, card);
469 unsigned int tmc, br = 10, brv = 1024;
470
471
472 if (port->settings.clock_rate > 0) {
473 /* Try lower br for better accuracy*/
474 do {
475 br--;
476 brv >>= 1; /* brv = 2^9 = 512 max in specs */
477
478 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
479 tmc = CLOCK_BASE / brv / port->settings.clock_rate;
480 }while (br > 1 && tmc <= 128);
481
482 if (tmc < 1) {
483 tmc = 1;
484 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
485 brv = 1;
486 } else if (tmc > 255)
487 tmc = 256; /* tmc=0 means 256 - low baud rates */
488
489 port->settings.clock_rate = CLOCK_BASE / brv / tmc;
490 } else {
491 br = 9; /* Minimum clock rate */
492 tmc = 256; /* 8bit = 0 */
493 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
494 }
495
496 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
497 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
498 port->tmc = tmc;
499
500 /* baud divisor - time constant*/
501#ifdef __HD64570_H
502 sca_out(port->tmc, msci + TMC, card);
503#else
504 sca_out(port->tmc, msci + TMCR, card);
505 sca_out(port->tmc, msci + TMCT, card);
506#endif
507
508 /* Set BRG bits */
509 sca_out(port->rxs, msci + RXS, card);
510 sca_out(port->txs, msci + TXS, card);
511
512 if (port->settings.loopback)
513 md2 |= MD2_LOOPBACK;
514 else
515 md2 &= ~MD2_LOOPBACK;
516
517 sca_out(md2, msci + MD2, card);
518
519}
520
521
522
523static void sca_open(struct net_device *dev)
524{
525 port_t *port = dev_to_port(dev);
526 card_t* card = port_to_card(port);
527 u16 msci = get_msci(port);
528 u8 md0, md2;
529
530 switch(port->encoding) {
531 case ENCODING_NRZ: md2 = MD2_NRZ; break;
532 case ENCODING_NRZI: md2 = MD2_NRZI; break;
533 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
534 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
535 default: md2 = MD2_MANCHESTER;
536 }
537
538 if (port->settings.loopback)
539 md2 |= MD2_LOOPBACK;
540
541 switch(port->parity) {
542 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
543 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
544#ifdef __HD64570_H
545 case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
546#else
547 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
548#endif
549 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
550 default: md0 = MD0_HDLC | MD0_CRC_NONE;
551 }
552
553 sca_out(CMD_RESET, msci + CMD, card);
554 sca_out(md0, msci + MD0, card);
555 sca_out(0x00, msci + MD1, card); /* no address field check */
556 sca_out(md2, msci + MD2, card);
557 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
558#ifdef __HD64570_H
559 sca_out(CTL_IDLE, msci + CTL, card);
560#else
561 /* Skip the rest of underrun frame */
562 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
563#endif
564
565#ifdef __HD64570_H
566 /* Allow at least 8 bytes before requesting RX DMA operation */
567 /* TX with higher priority and possibly with shorter transfers */
568 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
569 sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
570 sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
571#else
572 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
573 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
574 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
575 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
576 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
577#endif
578
579/* We're using the following interrupts:
580 - TXINT (DMAC completed all transmisions, underrun or DCD change)
581 - all DMA interrupts
582*/
583
584 sca_set_carrier(port);
585
586#ifdef __HD64570_H
587 /* MSCI TX INT and RX INT A IRQ enable */
588 sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
589 sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
590 sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
591 IER0, card); /* TXINT and RXINT */
592 /* enable DMA IRQ */
593 sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
594 IER1, card);
595#else
596 /* MSCI TXINT and RXINTA interrupt enable */
597 sca_outl(IE0_TXINT | IE0_RXINTA | IE0_UDRN | IE0_CDCD, msci + IE0,
598 card);
599 /* DMA & MSCI IRQ enable */
600 sca_outl(sca_inl(IER0, card) |
601 (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, card);
602#endif
603
604#ifdef __HD64570_H
605 sca_out(port->tmc, msci + TMC, card); /* Restore registers */
606#else
607 sca_out(port->tmc, msci + TMCR, card);
608 sca_out(port->tmc, msci + TMCT, card);
609#endif
610 sca_out(port->rxs, msci + RXS, card);
611 sca_out(port->txs, msci + TXS, card);
612 sca_out(CMD_TX_ENABLE, msci + CMD, card);
613 sca_out(CMD_RX_ENABLE, msci + CMD, card);
614
615 netif_start_queue(dev);
616}
617
618
619
620static void sca_close(struct net_device *dev)
621{
622 port_t *port = dev_to_port(dev);
623 card_t* card = port_to_card(port);
624
625 /* reset channel */
626 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
627#ifdef __HD64570_H
628 /* disable MSCI interrupts */
629 sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
630 IER0, card);
631 /* disable DMA interrupts */
632 sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
633 IER1, card);
634#else
635 /* disable DMA & MSCI IRQ */
636 sca_outl(sca_inl(IER0, card) &
637 (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, card);
638#endif
639 netif_stop_queue(dev);
640}
641
642
643
644static int sca_attach(struct net_device *dev, unsigned short encoding,
645 unsigned short parity)
646{
647 if (encoding != ENCODING_NRZ &&
648 encoding != ENCODING_NRZI &&
649 encoding != ENCODING_FM_MARK &&
650 encoding != ENCODING_FM_SPACE &&
651 encoding != ENCODING_MANCHESTER)
652 return -EINVAL;
653
654 if (parity != PARITY_NONE &&
655 parity != PARITY_CRC16_PR0 &&
656 parity != PARITY_CRC16_PR1 &&
657#ifdef __HD64570_H
658 parity != PARITY_CRC16_PR0_CCITT &&
659#else
660 parity != PARITY_CRC32_PR1_CCITT &&
661#endif
662 parity != PARITY_CRC16_PR1_CCITT)
663 return -EINVAL;
664
665 dev_to_port(dev)->encoding = encoding;
666 dev_to_port(dev)->parity = parity;
667 return 0;
668}
669
670
671
672#ifdef DEBUG_RINGS
673static void sca_dump_rings(struct net_device *dev)
674{
675 port_t *port = dev_to_port(dev);
676 card_t *card = port_to_card(port);
677 u16 cnt;
678#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
679 u8 page;
680#endif
681
682#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
683 page = sca_get_page(card);
684 openwin(card, 0);
685#endif
686
687 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
688 sca_ina(get_dmac_rx(port) + CDAL, card),
689 sca_ina(get_dmac_rx(port) + EDAL, card),
690 sca_in(DSR_RX(phy_node(port)), card), port->rxin,
691 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE?"":"in");
692 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
693 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
694
695 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
696 "last=%u %sactive",
697 sca_ina(get_dmac_tx(port) + CDAL, card),
698 sca_ina(get_dmac_tx(port) + EDAL, card),
699 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
700 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
701
702 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
703 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
704 printk("\n");
705
706 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, "
707 "ST: %02x %02x %02x %02x"
708#ifdef __HD64572_H
709 " %02x"
710#endif
711 ", FST: %02x CST: %02x %02x\n",
712 sca_in(get_msci(port) + MD0, card),
713 sca_in(get_msci(port) + MD1, card),
714 sca_in(get_msci(port) + MD2, card),
715 sca_in(get_msci(port) + ST0, card),
716 sca_in(get_msci(port) + ST1, card),
717 sca_in(get_msci(port) + ST2, card),
718 sca_in(get_msci(port) + ST3, card),
719#ifdef __HD64572_H
720 sca_in(get_msci(port) + ST4, card),
721#endif
722 sca_in(get_msci(port) + FST, card),
723 sca_in(get_msci(port) + CST0, card),
724 sca_in(get_msci(port) + CST1, card));
725
726#ifdef __HD64572_H
727 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
728 sca_inl(ISR0, card), sca_inl(ISR1, card));
729#else
730 printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
731 sca_in(ISR1, card), sca_in(ISR2, card));
732#endif
733
734#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
735 openwin(card, page); /* Restore original page */
736#endif
737}
738#endif /* DEBUG_RINGS */
739
740
741
742static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
743{
744 port_t *port = dev_to_port(dev);
745 card_t *card = port_to_card(port);
746 pkt_desc __iomem *desc;
747 u32 buff, len;
748#ifndef ALL_PAGES_ALWAYS_MAPPED
749 u8 page;
750 u32 maxlen;
751#endif
752
753 spin_lock_irq(&port->lock);
754
755 desc = desc_address(port, port->txin + 1, 1);
756 if (readb(&desc->stat)) { /* allow 1 packet gap */
757 /* should never happen - previous xmit should stop queue */
758#ifdef DEBUG_PKT
759 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
760#endif
761 netif_stop_queue(dev);
762 spin_unlock_irq(&port->lock);
763 return 1; /* request packet to be queued */
764 }
765
766#ifdef DEBUG_PKT
767 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
768 debug_frame(skb);
769#endif
770
771 desc = desc_address(port, port->txin, 1);
772 buff = buffer_offset(port, port->txin, 1);
773 len = skb->len;
774#ifndef ALL_PAGES_ALWAYS_MAPPED
775 page = buff / winsize(card);
776 buff = buff % winsize(card);
777 maxlen = winsize(card) - buff;
778
779 openwin(card, page);
780 if (len > maxlen) {
781 memcpy_toio(winbase(card) + buff, skb->data, maxlen);
782 openwin(card, page + 1);
783 memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
784 }
785 else
786#endif
787 memcpy_toio(winbase(card) + buff, skb->data, len);
788
789#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
790 openwin(card, 0); /* select pkt_desc table page back */
791#endif
792 writew(len, &desc->len);
793 writeb(ST_TX_EOM, &desc->stat);
794 dev->trans_start = jiffies;
795
796 port->txin = next_desc(port, port->txin, 1);
797 sca_outa(desc_offset(port, port->txin, 1),
798 get_dmac_tx(port) + EDAL, card);
799
800 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
801
802 desc = desc_address(port, port->txin + 1, 1);
803 if (readb(&desc->stat)) /* allow 1 packet gap */
804 netif_stop_queue(dev);
805
806 spin_unlock_irq(&port->lock);
807
808 dev_kfree_skb(skb);
809 return 0;
810}
811
812
813
814#ifdef NEED_DETECT_RAM
815static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
816{
817 /* Round RAM size to 32 bits, fill from end to start */
818 u32 i = ramsize &= ~3;
819
820#ifndef ALL_PAGES_ALWAYS_MAPPED
821 u32 size = winsize(card);
822
823 openwin(card, (i - 4) / size); /* select last window */
824#endif
825 do {
826 i -= 4;
827#ifndef ALL_PAGES_ALWAYS_MAPPED
828 if ((i + 4) % size == 0)
829 openwin(card, i / size);
830 writel(i ^ 0x12345678, rambase + i % size);
831#else
832 writel(i ^ 0x12345678, rambase + i);
833#endif
834 }while (i > 0);
835
836 for (i = 0; i < ramsize ; i += 4) {
837#ifndef ALL_PAGES_ALWAYS_MAPPED
838 if (i % size == 0)
839 openwin(card, i / size);
840
841 if (readl(rambase + i % size) != (i ^ 0x12345678))
842 break;
843#else
844 if (readl(rambase + i) != (i ^ 0x12345678))
845 break;
846#endif
847 }
848
849 return i;
850}
851#endif /* NEED_DETECT_RAM */
852
853
854
855static void __devinit sca_init(card_t *card, int wait_states)
856{
857 sca_out(wait_states, WCRL, card); /* Wait Control */
858 sca_out(wait_states, WCRM, card);
859 sca_out(wait_states, WCRH, card);
860
861 sca_out(0, DMER, card); /* DMA Master disable */
862 sca_out(0x03, PCR, card); /* DMA priority */
863 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
864 sca_out(0, DSR_TX(0), card);
865 sca_out(0, DSR_RX(1), card);
866 sca_out(0, DSR_TX(1), card);
867 sca_out(DMER_DME, DMER, card); /* DMA Master enable */
868}