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linux
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h>
8#include <asm/msi_bitmap.h>
9
10/*
11 * Global registers
12 */
13
14#define MPIC_GREG_BASE 0x01000
15
16#define MPIC_GREG_FEATURE_0 0x00000
17#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
18#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
19#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
20#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
21#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22#define MPIC_GREG_FEATURE_1 0x00010
23#define MPIC_GREG_GLOBAL_CONF_0 0x00020
24#define MPIC_GREG_GCONF_RESET 0x80000000
25#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
26#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
27#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
28#define MPIC_GREG_GCONF_MCK 0x08000000
29#define MPIC_GREG_GLOBAL_CONF_1 0x00030
30#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
31#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
32#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
33 (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
34#define MPIC_GREG_VENDOR_0 0x00040
35#define MPIC_GREG_VENDOR_1 0x00050
36#define MPIC_GREG_VENDOR_2 0x00060
37#define MPIC_GREG_VENDOR_3 0x00070
38#define MPIC_GREG_VENDOR_ID 0x00080
39#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
40#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
41#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
42#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
43#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
44#define MPIC_GREG_PROCESSOR_INIT 0x00090
45#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
46#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
47#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
48#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
49#define MPIC_GREG_IPI_STRIDE 0x10
50#define MPIC_GREG_SPURIOUS 0x000e0
51#define MPIC_GREG_TIMER_FREQ 0x000f0
52
53/*
54 *
55 * Timer registers
56 */
57#define MPIC_TIMER_BASE 0x01100
58#define MPIC_TIMER_STRIDE 0x40
59
60#define MPIC_TIMER_CURRENT_CNT 0x00000
61#define MPIC_TIMER_BASE_CNT 0x00010
62#define MPIC_TIMER_VECTOR_PRI 0x00020
63#define MPIC_TIMER_DESTINATION 0x00030
64
65/*
66 * Per-Processor registers
67 */
68
69#define MPIC_CPU_THISBASE 0x00000
70#define MPIC_CPU_BASE 0x20000
71#define MPIC_CPU_STRIDE 0x01000
72
73#define MPIC_CPU_IPI_DISPATCH_0 0x00040
74#define MPIC_CPU_IPI_DISPATCH_1 0x00050
75#define MPIC_CPU_IPI_DISPATCH_2 0x00060
76#define MPIC_CPU_IPI_DISPATCH_3 0x00070
77#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
78#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
79#define MPIC_CPU_TASKPRI_MASK 0x0000000f
80#define MPIC_CPU_WHOAMI 0x00090
81#define MPIC_CPU_WHOAMI_MASK 0x0000001f
82#define MPIC_CPU_INTACK 0x000a0
83#define MPIC_CPU_EOI 0x000b0
84#define MPIC_CPU_MCACK 0x000c0
85
86/*
87 * Per-source registers
88 */
89
90#define MPIC_IRQ_BASE 0x10000
91#define MPIC_IRQ_STRIDE 0x00020
92#define MPIC_IRQ_VECTOR_PRI 0x00000
93#define MPIC_VECPRI_MASK 0x80000000
94#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
95#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
96#define MPIC_VECPRI_PRIORITY_SHIFT 16
97#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
98#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
99#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
100#define MPIC_VECPRI_POLARITY_MASK 0x00800000
101#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
102#define MPIC_VECPRI_SENSE_EDGE 0x00000000
103#define MPIC_VECPRI_SENSE_MASK 0x00400000
104#define MPIC_IRQ_DESTINATION 0x00010
105
106#define MPIC_MAX_IRQ_SOURCES 2048
107#define MPIC_MAX_CPUS 32
108#define MPIC_MAX_ISU 32
109
110/*
111 * Tsi108 implementation of MPIC has many differences from the original one
112 */
113
114/*
115 * Global registers
116 */
117
118#define TSI108_GREG_BASE 0x00000
119#define TSI108_GREG_FEATURE_0 0x00000
120#define TSI108_GREG_GLOBAL_CONF_0 0x00004
121#define TSI108_GREG_VENDOR_ID 0x0000c
122#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
123#define TSI108_GREG_IPI_STRIDE 0x0c
124#define TSI108_GREG_SPURIOUS 0x00010
125#define TSI108_GREG_TIMER_FREQ 0x00014
126
127/*
128 * Timer registers
129 */
130#define TSI108_TIMER_BASE 0x0030
131#define TSI108_TIMER_STRIDE 0x10
132#define TSI108_TIMER_CURRENT_CNT 0x00000
133#define TSI108_TIMER_BASE_CNT 0x00004
134#define TSI108_TIMER_VECTOR_PRI 0x00008
135#define TSI108_TIMER_DESTINATION 0x0000c
136
137/*
138 * Per-Processor registers
139 */
140#define TSI108_CPU_BASE 0x00300
141#define TSI108_CPU_STRIDE 0x00040
142#define TSI108_CPU_IPI_DISPATCH_0 0x00200
143#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
144#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
145#define TSI108_CPU_WHOAMI 0xffffffff
146#define TSI108_CPU_INTACK 0x00004
147#define TSI108_CPU_EOI 0x00008
148#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
149
150/*
151 * Per-source registers
152 */
153#define TSI108_IRQ_BASE 0x00100
154#define TSI108_IRQ_STRIDE 0x00008
155#define TSI108_IRQ_VECTOR_PRI 0x00000
156#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
157#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
158#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
159#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
160#define TSI108_VECPRI_SENSE_EDGE 0x00000000
161#define TSI108_VECPRI_POLARITY_MASK 0x01000000
162#define TSI108_VECPRI_SENSE_MASK 0x02000000
163#define TSI108_IRQ_DESTINATION 0x00004
164
165/* weird mpic register indices and mask bits in the HW info array */
166enum {
167 MPIC_IDX_GREG_BASE = 0,
168 MPIC_IDX_GREG_FEATURE_0,
169 MPIC_IDX_GREG_GLOBAL_CONF_0,
170 MPIC_IDX_GREG_VENDOR_ID,
171 MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
172 MPIC_IDX_GREG_IPI_STRIDE,
173 MPIC_IDX_GREG_SPURIOUS,
174 MPIC_IDX_GREG_TIMER_FREQ,
175
176 MPIC_IDX_TIMER_BASE,
177 MPIC_IDX_TIMER_STRIDE,
178 MPIC_IDX_TIMER_CURRENT_CNT,
179 MPIC_IDX_TIMER_BASE_CNT,
180 MPIC_IDX_TIMER_VECTOR_PRI,
181 MPIC_IDX_TIMER_DESTINATION,
182
183 MPIC_IDX_CPU_BASE,
184 MPIC_IDX_CPU_STRIDE,
185 MPIC_IDX_CPU_IPI_DISPATCH_0,
186 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
187 MPIC_IDX_CPU_CURRENT_TASK_PRI,
188 MPIC_IDX_CPU_WHOAMI,
189 MPIC_IDX_CPU_INTACK,
190 MPIC_IDX_CPU_EOI,
191 MPIC_IDX_CPU_MCACK,
192
193 MPIC_IDX_IRQ_BASE,
194 MPIC_IDX_IRQ_STRIDE,
195 MPIC_IDX_IRQ_VECTOR_PRI,
196
197 MPIC_IDX_VECPRI_VECTOR_MASK,
198 MPIC_IDX_VECPRI_POLARITY_POSITIVE,
199 MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
200 MPIC_IDX_VECPRI_SENSE_LEVEL,
201 MPIC_IDX_VECPRI_SENSE_EDGE,
202 MPIC_IDX_VECPRI_POLARITY_MASK,
203 MPIC_IDX_VECPRI_SENSE_MASK,
204 MPIC_IDX_IRQ_DESTINATION,
205 MPIC_IDX_END
206};
207
208
209#ifdef CONFIG_MPIC_U3_HT_IRQS
210/* Fixup table entry */
211struct mpic_irq_fixup
212{
213 u8 __iomem *base;
214 u8 __iomem *applebase;
215 u32 data;
216 unsigned int index;
217};
218#endif /* CONFIG_MPIC_U3_HT_IRQS */
219
220
221enum mpic_reg_type {
222 mpic_access_mmio_le,
223 mpic_access_mmio_be,
224#ifdef CONFIG_PPC_DCR
225 mpic_access_dcr
226#endif
227};
228
229struct mpic_reg_bank {
230 u32 __iomem *base;
231#ifdef CONFIG_PPC_DCR
232 dcr_host_t dhost;
233#endif /* CONFIG_PPC_DCR */
234};
235
236struct mpic_irq_save {
237 u32 vecprio,
238 dest;
239#ifdef CONFIG_MPIC_U3_HT_IRQS
240 u32 fixup_data;
241#endif
242};
243
244/* The instance data of a given MPIC */
245struct mpic
246{
247 /* The remapper for this MPIC */
248 struct irq_host *irqhost;
249
250 /* The "linux" controller struct */
251 struct irq_chip hc_irq;
252#ifdef CONFIG_MPIC_U3_HT_IRQS
253 struct irq_chip hc_ht_irq;
254#endif
255#ifdef CONFIG_SMP
256 struct irq_chip hc_ipi;
257#endif
258 const char *name;
259 /* Flags */
260 unsigned int flags;
261 /* How many irq sources in a given ISU */
262 unsigned int isu_size;
263 unsigned int isu_shift;
264 unsigned int isu_mask;
265 unsigned int irq_count;
266 /* Number of sources */
267 unsigned int num_sources;
268 /* Number of CPUs */
269 unsigned int num_cpus;
270 /* default senses array */
271 unsigned char *senses;
272 unsigned int senses_count;
273
274 /* vector numbers used for internal sources (ipi/timers) */
275 unsigned int ipi_vecs[4];
276 unsigned int timer_vecs[4];
277
278 /* Spurious vector to program into unused sources */
279 unsigned int spurious_vec;
280
281#ifdef CONFIG_MPIC_U3_HT_IRQS
282 /* The fixup table */
283 struct mpic_irq_fixup *fixups;
284 spinlock_t fixup_lock;
285#endif
286
287 /* Register access method */
288 enum mpic_reg_type reg_type;
289
290 /* The various ioremap'ed bases */
291 struct mpic_reg_bank gregs;
292 struct mpic_reg_bank tmregs;
293 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
294 struct mpic_reg_bank isus[MPIC_MAX_ISU];
295
296 /* Protected sources */
297 unsigned long *protected;
298
299#ifdef CONFIG_MPIC_WEIRD
300 /* Pointer to HW info array */
301 u32 *hw_set;
302#endif
303
304#ifdef CONFIG_PCI_MSI
305 struct msi_bitmap msi_bitmap;
306#endif
307
308#ifdef CONFIG_MPIC_BROKEN_REGREAD
309 u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
310#endif
311
312 /* link */
313 struct mpic *next;
314
315 struct sys_device sysdev;
316
317#ifdef CONFIG_PM
318 struct mpic_irq_save *save_data;
319#endif
320};
321
322/*
323 * MPIC flags (passed to mpic_alloc)
324 *
325 * The top 4 bits contain an MPIC bhw id that is used to index the
326 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
327 * Note setting any ID (leaving those bits to 0) means standard MPIC
328 */
329
330/* This is the primary controller, only that one has IPIs and
331 * has afinity control. A non-primary MPIC always uses CPU0
332 * registers only
333 */
334#define MPIC_PRIMARY 0x00000001
335
336/* Set this for a big-endian MPIC */
337#define MPIC_BIG_ENDIAN 0x00000002
338/* Broken U3 MPIC */
339#define MPIC_U3_HT_IRQS 0x00000004
340/* Broken IPI registers (autodetected) */
341#define MPIC_BROKEN_IPI 0x00000008
342/* MPIC wants a reset */
343#define MPIC_WANTS_RESET 0x00000010
344/* Spurious vector requires EOI */
345#define MPIC_SPV_EOI 0x00000020
346/* No passthrough disable */
347#define MPIC_NO_PTHROU_DIS 0x00000040
348/* DCR based MPIC */
349#define MPIC_USES_DCR 0x00000080
350/* MPIC has 11-bit vector fields (or larger) */
351#define MPIC_LARGE_VECTORS 0x00000100
352/* Enable delivery of prio 15 interrupts as MCK instead of EE */
353#define MPIC_ENABLE_MCK 0x00000200
354/* Disable bias among target selection, spread interrupts evenly */
355#define MPIC_NO_BIAS 0x00000400
356/* Ignore NIRQS as reported by FRR */
357#define MPIC_BROKEN_FRR_NIRQS 0x00000800
358/* Destination only supports a single CPU at a time */
359#define MPIC_SINGLE_DEST_CPU 0x00001000
360
361/* MPIC HW modification ID */
362#define MPIC_REGSET_MASK 0xf0000000
363#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
364#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
365
366#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
367#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
368
369/* Allocate the controller structure and setup the linux irq descs
370 * for the range if interrupts passed in. No HW initialization is
371 * actually performed.
372 *
373 * @phys_addr: physial base address of the MPIC
374 * @flags: flags, see constants above
375 * @isu_size: number of interrupts in an ISU. Use 0 to use a
376 * standard ISU-less setup (aka powermac)
377 * @irq_offset: first irq number to assign to this mpic
378 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
379 * to match the number of sources
380 * @ipi_offset: first irq number to assign to this mpic IPI sources,
381 * used only on primary mpic
382 * @senses: array of sense values
383 * @senses_num: number of entries in the array
384 *
385 * Note about the sense array. If none is passed, all interrupts are
386 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
387 * case they are edge positive (and the array is ignored anyway).
388 * The values in the array start at the first source of the MPIC,
389 * that is senses[0] correspond to linux irq "irq_offset".
390 */
391extern struct mpic *mpic_alloc(struct device_node *node,
392 phys_addr_t phys_addr,
393 unsigned int flags,
394 unsigned int isu_size,
395 unsigned int irq_count,
396 const char *name);
397
398/* Assign ISUs, to call before mpic_init()
399 *
400 * @mpic: controller structure as returned by mpic_alloc()
401 * @isu_num: ISU number
402 * @phys_addr: physical address of the ISU
403 */
404extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
405 phys_addr_t phys_addr);
406
407/* Set default sense codes
408 *
409 * @mpic: controller
410 * @senses: array of sense codes
411 * @count: size of above array
412 *
413 * Optionally provide an array (indexed on hardware interrupt numbers
414 * for this MPIC) of default sense codes for the chip. Those are linux
415 * sense codes IRQ_TYPE_*
416 *
417 * The driver gets ownership of the pointer, don't dispose of it or
418 * anything like that. __init only.
419 */
420extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
421
422
423/* Initialize the controller. After this has been called, none of the above
424 * should be called again for this mpic
425 */
426extern void mpic_init(struct mpic *mpic);
427
428/*
429 * All of the following functions must only be used after the
430 * ISUs have been assigned and the controller fully initialized
431 * with mpic_init()
432 */
433
434
435/* Change the priority of an interrupt. Default is 8 for irqs and
436 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
437 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
438 */
439extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
440
441/* Setup a non-boot CPU */
442extern void mpic_setup_this_cpu(void);
443
444/* Clean up for kexec (or cpu offline or ...) */
445extern void mpic_teardown_this_cpu(int secondary);
446
447/* Get the current cpu priority for this cpu (0..15) */
448extern int mpic_cpu_get_priority(void);
449
450/* Set the current cpu priority for this cpu */
451extern void mpic_cpu_set_priority(int prio);
452
453/* Request IPIs on primary mpic */
454extern void mpic_request_ipis(void);
455
456/* Send an IPI (non offseted number 0..3) */
457extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
458
459/* Send a message (IPI) to a given target (cpu number or MSG_*) */
460void smp_mpic_message_pass(int target, int msg);
461
462/* Unmask a specific virq */
463extern void mpic_unmask_irq(unsigned int irq);
464/* Mask a specific virq */
465extern void mpic_mask_irq(unsigned int irq);
466/* EOI a specific virq */
467extern void mpic_end_irq(unsigned int irq);
468
469/* Fetch interrupt from a given mpic */
470extern unsigned int mpic_get_one_irq(struct mpic *mpic);
471/* This one gets from the primary mpic */
472extern unsigned int mpic_get_irq(void);
473/* Fetch Machine Check interrupt from primary mpic */
474extern unsigned int mpic_get_mcirq(void);
475
476/* Set the EPIC clock ratio */
477void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
478
479/* Enable/Disable EPIC serial interrupt mode */
480void mpic_set_serial_int(struct mpic *mpic, int enable);
481
482#endif /* __KERNEL__ */
483#endif /* _ASM_POWERPC_MPIC_H */