tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26#ifndef __R8A66597_H__
27#define __R8A66597_H__
28
29#define SYSCFG0 0x00
30#define SYSCFG1 0x02
31#define SYSSTS0 0x04
32#define SYSSTS1 0x06
33#define DVSTCTR0 0x08
34#define DVSTCTR1 0x0A
35#define TESTMODE 0x0C
36#define PINCFG 0x0E
37#define DMA0CFG 0x10
38#define DMA1CFG 0x12
39#define CFIFO 0x14
40#define D0FIFO 0x18
41#define D1FIFO 0x1C
42#define CFIFOSEL 0x20
43#define CFIFOCTR 0x22
44#define CFIFOSIE 0x24
45#define D0FIFOSEL 0x28
46#define D0FIFOCTR 0x2A
47#define D1FIFOSEL 0x2C
48#define D1FIFOCTR 0x2E
49#define INTENB0 0x30
50#define INTENB1 0x32
51#define INTENB2 0x34
52#define BRDYENB 0x36
53#define NRDYENB 0x38
54#define BEMPENB 0x3A
55#define SOFCFG 0x3C
56#define INTSTS0 0x40
57#define INTSTS1 0x42
58#define INTSTS2 0x44
59#define BRDYSTS 0x46
60#define NRDYSTS 0x48
61#define BEMPSTS 0x4A
62#define FRMNUM 0x4C
63#define UFRMNUM 0x4E
64#define USBADDR 0x50
65#define USBREQ 0x54
66#define USBVAL 0x56
67#define USBINDX 0x58
68#define USBLENG 0x5A
69#define DCPCFG 0x5C
70#define DCPMAXP 0x5E
71#define DCPCTR 0x60
72#define PIPESEL 0x64
73#define PIPECFG 0x68
74#define PIPEBUF 0x6A
75#define PIPEMAXP 0x6C
76#define PIPEPERI 0x6E
77#define PIPE1CTR 0x70
78#define PIPE2CTR 0x72
79#define PIPE3CTR 0x74
80#define PIPE4CTR 0x76
81#define PIPE5CTR 0x78
82#define PIPE6CTR 0x7A
83#define PIPE7CTR 0x7C
84#define PIPE8CTR 0x7E
85#define PIPE9CTR 0x80
86#define PIPE1TRE 0x90
87#define PIPE1TRN 0x92
88#define PIPE2TRE 0x94
89#define PIPE2TRN 0x96
90#define PIPE3TRE 0x98
91#define PIPE3TRN 0x9A
92#define PIPE4TRE 0x9C
93#define PIPE4TRN 0x9E
94#define PIPE5TRE 0xA0
95#define PIPE5TRN 0xA2
96#define DEVADD0 0xD0
97#define DEVADD1 0xD2
98#define DEVADD2 0xD4
99#define DEVADD3 0xD6
100#define DEVADD4 0xD8
101#define DEVADD5 0xDA
102#define DEVADD6 0xDC
103#define DEVADD7 0xDE
104#define DEVADD8 0xE0
105#define DEVADD9 0xE2
106#define DEVADDA 0xE4
107
108/* System Configuration Control Register */
109#define XTAL 0xC000 /* b15-14: Crystal selection */
110#define XTAL48 0x8000 /* 48MHz */
111#define XTAL24 0x4000 /* 24MHz */
112#define XTAL12 0x0000 /* 12MHz */
113#define XCKE 0x2000 /* b13: External clock enable */
114#define PLLC 0x0800 /* b11: PLL control */
115#define SCKE 0x0400 /* b10: USB clock enable */
116#define PCSDIS 0x0200 /* b9: not CS wakeup */
117#define LPSME 0x0100 /* b8: Low power sleep mode */
118#define HSE 0x0080 /* b7: Hi-speed enable */
119#define DCFM 0x0040 /* b6: Controller function select */
120#define DRPD 0x0020 /* b5: D+/- pull down control */
121#define DPRPU 0x0010 /* b4: D+ pull up control */
122#define USBE 0x0001 /* b0: USB module operation enable */
123
124/* System Configuration Status Register */
125#define OVCBIT 0x8000 /* b15-14: Over-current bit */
126#define OVCMON 0xC000 /* b15-14: Over-current monitor */
127#define SOFEA 0x0020 /* b5: SOF monitor */
128#define IDMON 0x0004 /* b3: ID-pin monitor */
129#define LNST 0x0003 /* b1-0: D+, D- line status */
130#define SE1 0x0003 /* SE1 */
131#define FS_KSTS 0x0002 /* Full-Speed K State */
132#define FS_JSTS 0x0001 /* Full-Speed J State */
133#define LS_JSTS 0x0002 /* Low-Speed J State */
134#define LS_KSTS 0x0001 /* Low-Speed K State */
135#define SE0 0x0000 /* SE0 */
136
137/* Device State Control Register */
138#define EXTLP0 0x0400 /* b10: External port */
139#define VBOUT 0x0200 /* b9: VBUS output */
140#define WKUP 0x0100 /* b8: Remote wakeup */
141#define RWUPE 0x0080 /* b7: Remote wakeup sense */
142#define USBRST 0x0040 /* b6: USB reset enable */
143#define RESUME 0x0020 /* b5: Resume enable */
144#define UACT 0x0010 /* b4: USB bus enable */
145#define RHST 0x0007 /* b1-0: Reset handshake status */
146#define HSPROC 0x0004 /* HS handshake is processing */
147#define HSMODE 0x0003 /* Hi-Speed mode */
148#define FSMODE 0x0002 /* Full-Speed mode */
149#define LSMODE 0x0001 /* Low-Speed mode */
150#define UNDECID 0x0000 /* Undecided */
151
152/* Test Mode Register */
153#define UTST 0x000F /* b3-0: Test select */
154#define H_TST_PACKET 0x000C /* HOST TEST Packet */
155#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
156#define H_TST_K 0x000A /* HOST TEST K */
157#define H_TST_J 0x0009 /* HOST TEST J */
158#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
159#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
160#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
161#define P_TST_K 0x0002 /* PERI TEST K */
162#define P_TST_J 0x0001 /* PERI TEST J */
163#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
164
165/* Data Pin Configuration Register */
166#define LDRV 0x8000 /* b15: Drive Current Adjust */
167#define VIF1 0x0000 /* VIF = 1.8V */
168#define VIF3 0x8000 /* VIF = 3.3V */
169#define INTA 0x0001 /* b1: USB INT-pin active */
170
171/* DMAx Pin Configuration Register */
172#define DREQA 0x4000 /* b14: Dreq active select */
173#define BURST 0x2000 /* b13: Burst mode */
174#define DACKA 0x0400 /* b10: Dack active select */
175#define DFORM 0x0380 /* b9-7: DMA mode select */
176#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
177#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
178#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
179#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
180#define DENDA 0x0040 /* b6: Dend active select */
181#define PKTM 0x0020 /* b5: Packet mode */
182#define DENDE 0x0010 /* b4: Dend enable */
183#define OBUS 0x0004 /* b2: OUTbus mode */
184
185/* CFIFO/DxFIFO Port Select Register */
186#define RCNT 0x8000 /* b15: Read count mode */
187#define REW 0x4000 /* b14: Buffer rewind */
188#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
189#define DREQE 0x1000 /* b12: DREQ output enable */
190#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
191#define MBW 0x0800
192#else
193#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
194#endif
195#define MBW_8 0x0000 /* 8bit */
196#define MBW_16 0x0400 /* 16bit */
197#define BIGEND 0x0100 /* b8: Big endian mode */
198#define BYTE_LITTLE 0x0000 /* little dendian */
199#define BYTE_BIG 0x0100 /* big endifan */
200#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
201#define CURPIPE 0x000F /* b2-0: PIPE select */
202
203/* CFIFO/DxFIFO Port Control Register */
204#define BVAL 0x8000 /* b15: Buffer valid flag */
205#define BCLR 0x4000 /* b14: Buffer clear */
206#define FRDY 0x2000 /* b13: FIFO ready */
207#define DTLN 0x0FFF /* b11-0: FIFO received data length */
208
209/* Interrupt Enable Register 0 */
210#define VBSE 0x8000 /* b15: VBUS interrupt */
211#define RSME 0x4000 /* b14: Resume interrupt */
212#define SOFE 0x2000 /* b13: Frame update interrupt */
213#define DVSE 0x1000 /* b12: Device state transition interrupt */
214#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
215#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
216#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
217#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
218
219/* Interrupt Enable Register 1 */
220#define OVRCRE 0x8000 /* b15: Over-current interrupt */
221#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
222#define DTCHE 0x1000 /* b12: Detach sense interrupt */
223#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
224#define EOFERRE 0x0040 /* b6: EOF error interrupt */
225#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
226#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
227
228/* BRDY Interrupt Enable/Status Register */
229#define BRDY9 0x0200 /* b9: PIPE9 */
230#define BRDY8 0x0100 /* b8: PIPE8 */
231#define BRDY7 0x0080 /* b7: PIPE7 */
232#define BRDY6 0x0040 /* b6: PIPE6 */
233#define BRDY5 0x0020 /* b5: PIPE5 */
234#define BRDY4 0x0010 /* b4: PIPE4 */
235#define BRDY3 0x0008 /* b3: PIPE3 */
236#define BRDY2 0x0004 /* b2: PIPE2 */
237#define BRDY1 0x0002 /* b1: PIPE1 */
238#define BRDY0 0x0001 /* b1: PIPE0 */
239
240/* NRDY Interrupt Enable/Status Register */
241#define NRDY9 0x0200 /* b9: PIPE9 */
242#define NRDY8 0x0100 /* b8: PIPE8 */
243#define NRDY7 0x0080 /* b7: PIPE7 */
244#define NRDY6 0x0040 /* b6: PIPE6 */
245#define NRDY5 0x0020 /* b5: PIPE5 */
246#define NRDY4 0x0010 /* b4: PIPE4 */
247#define NRDY3 0x0008 /* b3: PIPE3 */
248#define NRDY2 0x0004 /* b2: PIPE2 */
249#define NRDY1 0x0002 /* b1: PIPE1 */
250#define NRDY0 0x0001 /* b1: PIPE0 */
251
252/* BEMP Interrupt Enable/Status Register */
253#define BEMP9 0x0200 /* b9: PIPE9 */
254#define BEMP8 0x0100 /* b8: PIPE8 */
255#define BEMP7 0x0080 /* b7: PIPE7 */
256#define BEMP6 0x0040 /* b6: PIPE6 */
257#define BEMP5 0x0020 /* b5: PIPE5 */
258#define BEMP4 0x0010 /* b4: PIPE4 */
259#define BEMP3 0x0008 /* b3: PIPE3 */
260#define BEMP2 0x0004 /* b2: PIPE2 */
261#define BEMP1 0x0002 /* b1: PIPE1 */
262#define BEMP0 0x0001 /* b0: PIPE0 */
263
264/* SOF Pin Configuration Register */
265#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
266#define BRDYM 0x0040 /* b6: BRDY clear timing */
267#define INTL 0x0020 /* b5: Interrupt sense select */
268#define EDGESTS 0x0010 /* b4: */
269#define SOFMODE 0x000C /* b3-2: SOF pin select */
270#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
271#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
272#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
273
274/* Interrupt Status Register 0 */
275#define VBINT 0x8000 /* b15: VBUS interrupt */
276#define RESM 0x4000 /* b14: Resume interrupt */
277#define SOFR 0x2000 /* b13: SOF frame update interrupt */
278#define DVST 0x1000 /* b12: Device state transition interrupt */
279#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
280#define BEMP 0x0400 /* b10: Buffer empty interrupt */
281#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
282#define BRDY 0x0100 /* b8: Buffer ready interrupt */
283#define VBSTS 0x0080 /* b7: VBUS input port */
284#define DVSQ 0x0070 /* b6-4: Device state */
285#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
286#define DS_SPD_ADDR 0x0060 /* Suspend Address */
287#define DS_SPD_DFLT 0x0050 /* Suspend Default */
288#define DS_SPD_POWR 0x0040 /* Suspend Powered */
289#define DS_SUSP 0x0040 /* Suspend */
290#define DS_CNFG 0x0030 /* Configured */
291#define DS_ADDS 0x0020 /* Address */
292#define DS_DFLT 0x0010 /* Default */
293#define DS_POWR 0x0000 /* Powered */
294#define DVSQS 0x0030 /* b5-4: Device state */
295#define VALID 0x0008 /* b3: Setup packet detected flag */
296#define CTSQ 0x0007 /* b2-0: Control transfer stage */
297#define CS_SQER 0x0006 /* Sequence error */
298#define CS_WRND 0x0005 /* Control write nodata status stage */
299#define CS_WRSS 0x0004 /* Control write status stage */
300#define CS_WRDS 0x0003 /* Control write data stage */
301#define CS_RDSS 0x0002 /* Control read status stage */
302#define CS_RDDS 0x0001 /* Control read data stage */
303#define CS_IDST 0x0000 /* Idle or setup stage */
304
305/* Interrupt Status Register 1 */
306#define OVRCR 0x8000 /* b15: Over-current interrupt */
307#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
308#define DTCH 0x1000 /* b12: Detach sense interrupt */
309#define ATTCH 0x0800 /* b11: Attach sense interrupt */
310#define EOFERR 0x0040 /* b6: EOF-error interrupt */
311#define SIGN 0x0020 /* b5: Setup ignore interrupt */
312#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
313
314/* Frame Number Register */
315#define OVRN 0x8000 /* b15: Overrun error */
316#define CRCE 0x4000 /* b14: Received data error */
317#define FRNM 0x07FF /* b10-0: Frame number */
318
319/* Micro Frame Number Register */
320#define UFRNM 0x0007 /* b2-0: Micro frame number */
321
322/* Default Control Pipe Maxpacket Size Register */
323/* Pipe Maxpacket Size Register */
324#define DEVSEL 0xF000 /* b15-14: Device address select */
325#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
326
327/* Default Control Pipe Control Register */
328#define BSTS 0x8000 /* b15: Buffer status */
329#define SUREQ 0x4000 /* b14: Send USB request */
330#define CSCLR 0x2000 /* b13: complete-split status clear */
331#define CSSTS 0x1000 /* b12: complete-split status */
332#define SUREQCLR 0x0800 /* b11: stop setup request */
333#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
334#define SQSET 0x0080 /* b7: Sequence toggle bit set */
335#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
336#define PBUSY 0x0020 /* b5: pipe busy */
337#define PINGE 0x0010 /* b4: ping enable */
338#define CCPL 0x0004 /* b2: Enable control transfer complete */
339#define PID 0x0003 /* b1-0: Response PID */
340#define PID_STALL11 0x0003 /* STALL */
341#define PID_STALL 0x0002 /* STALL */
342#define PID_BUF 0x0001 /* BUF */
343#define PID_NAK 0x0000 /* NAK */
344
345/* Pipe Window Select Register */
346#define PIPENM 0x0007 /* b2-0: Pipe select */
347
348/* Pipe Configuration Register */
349#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
350#define R8A66597_ISO 0xC000 /* Isochronous */
351#define R8A66597_INT 0x8000 /* Interrupt */
352#define R8A66597_BULK 0x4000 /* Bulk */
353#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
354#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
355#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
356#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
357#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
358#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
359
360/* Pipe Buffer Configuration Register */
361#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
362#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
363#define PIPE0BUF 256
364#define PIPExBUF 64
365
366/* Pipe Maxpacket Size Register */
367#define MXPS 0x07FF /* b10-0: Maxpacket size */
368
369/* Pipe Cycle Configuration Register */
370#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
371#define IITV 0x0007 /* b2-0: Isochronous interval */
372
373/* Pipex Control Register */
374#define BSTS 0x8000 /* b15: Buffer status */
375#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
376#define CSCLR 0x2000 /* b13: complete-split status clear */
377#define CSSTS 0x1000 /* b12: complete-split status */
378#define ATREPM 0x0400 /* b10: Auto repeat mode */
379#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
380#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
381#define SQSET 0x0080 /* b7: Sequence toggle bit set */
382#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
383#define PBUSY 0x0020 /* b5: pipe busy */
384#define PID 0x0003 /* b1-0: Response PID */
385
386/* PIPExTRE */
387#define TRENB 0x0200 /* b9: Transaction counter enable */
388#define TRCLR 0x0100 /* b8: Transaction counter clear */
389
390/* PIPExTRN */
391#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
392
393/* DEVADDx */
394#define UPPHUB 0x7800
395#define HUBPORT 0x0700
396#define USBSPD 0x00C0
397#define RTPORT 0x0001
398
399#define R8A66597_MAX_NUM_PIPE 10
400#define R8A66597_BUF_BSIZE 8
401#define R8A66597_MAX_DEVICE 10
402#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
403#define R8A66597_MAX_ROOT_HUB 1
404#else
405#define R8A66597_MAX_ROOT_HUB 2
406#endif
407#define R8A66597_MAX_SAMPLING 5
408#define R8A66597_RH_POLL_TIME 10
409#define R8A66597_MAX_DMA_CHANNEL 2
410#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
411#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
412#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
413#define make_devsel(addr) (addr << 12)
414
415struct r8a66597_pipe_info {
416 unsigned long timer_interval;
417 u16 pipenum;
418 u16 address; /* R8A66597 HCD usb address */
419 u16 epnum;
420 u16 maxpacket;
421 u16 type;
422 u16 bufnum;
423 u16 buf_bsize;
424 u16 interval;
425 u16 dir_in;
426};
427
428struct r8a66597_pipe {
429 struct r8a66597_pipe_info info;
430
431 unsigned long fifoaddr;
432 unsigned long fifosel;
433 unsigned long fifoctr;
434 unsigned long pipectr;
435 unsigned long pipetre;
436 unsigned long pipetrn;
437};
438
439struct r8a66597_td {
440 struct r8a66597_pipe *pipe;
441 struct urb *urb;
442 struct list_head queue;
443
444 u16 type;
445 u16 pipenum;
446 int iso_cnt;
447
448 u16 address; /* R8A66597's USB address */
449 u16 maxpacket;
450
451 unsigned zero_packet:1;
452 unsigned short_packet:1;
453 unsigned set_address:1;
454};
455
456struct r8a66597_device {
457 u16 address; /* R8A66597's USB address */
458 u16 hub_port;
459 u16 root_port;
460
461 unsigned short ep_in_toggle;
462 unsigned short ep_out_toggle;
463 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
464 unsigned char dma_map;
465
466 enum usb_device_state state;
467
468 struct usb_device *udev;
469 int usb_address;
470 struct list_head device_list;
471};
472
473struct r8a66597_root_hub {
474 u32 port;
475 u16 old_syssts;
476 int scount;
477
478 struct r8a66597_device *dev;
479};
480
481struct r8a66597 {
482 spinlock_t lock;
483 unsigned long reg;
484
485 struct r8a66597_device device0;
486 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
487 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
488
489 struct timer_list rh_timer;
490 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
491 struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
492
493 unsigned short address_map;
494 unsigned short timeout_map;
495 unsigned short interval_map;
496 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
497 unsigned char dma_map;
498
499 struct list_head child_device;
500 unsigned long child_connect_map[4];
501};
502
503static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
504{
505 return (struct r8a66597 *)(hcd->hcd_priv);
506}
507
508static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
509{
510 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
511}
512
513static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
514 u16 pipenum)
515{
516 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
517 return NULL;
518
519 return list_entry(r8a66597->pipe_queue[pipenum].next,
520 struct r8a66597_td, queue);
521}
522
523static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
524 u16 pipenum)
525{
526 struct r8a66597_td *td;
527
528 td = r8a66597_get_td(r8a66597, pipenum);
529 return (td ? td->urb : NULL);
530}
531
532static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
533{
534 return inw(r8a66597->reg + offset);
535}
536
537static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
538 unsigned long offset, u16 *buf,
539 int len)
540{
541#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
542 unsigned long fifoaddr = r8a66597->reg + offset;
543 unsigned long count;
544
545 count = len / 4;
546 insl(fifoaddr, buf, count);
547
548 if (len & 0x00000003) {
549 unsigned long tmp = inl(fifoaddr);
550 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
551 }
552#else
553 len = (len + 1) / 2;
554 insw(r8a66597->reg + offset, buf, len);
555#endif
556}
557
558static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
559 unsigned long offset)
560{
561 outw(val, r8a66597->reg + offset);
562}
563
564static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
565 unsigned long offset, u16 *buf,
566 int len)
567{
568 unsigned long fifoaddr = r8a66597->reg + offset;
569#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
570 unsigned long count;
571 unsigned char *pb;
572 int i;
573
574 count = len / 4;
575 outsl(fifoaddr, buf, count);
576
577 if (len & 0x00000003) {
578 pb = (unsigned char *)buf + count * 4;
579 for (i = 0; i < (len & 0x00000003); i++) {
580 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
581 outb(pb[i], fifoaddr + i);
582 else
583 outb(pb[i], fifoaddr + 3 - i);
584 }
585 }
586#else
587 int odd = len & 0x0001;
588
589 len = len / 2;
590 outsw(fifoaddr, buf, len);
591 if (unlikely(odd)) {
592 buf = &buf[len];
593 outb((unsigned char)*buf, fifoaddr);
594 }
595#endif
596}
597
598static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
599 u16 val, u16 pat, unsigned long offset)
600{
601 u16 tmp;
602 tmp = r8a66597_read(r8a66597, offset);
603 tmp = tmp & (~pat);
604 tmp = tmp | val;
605 r8a66597_write(r8a66597, tmp, offset);
606}
607
608#define r8a66597_bclr(r8a66597, val, offset) \
609 r8a66597_mdfy(r8a66597, 0, val, offset)
610#define r8a66597_bset(r8a66597, val, offset) \
611 r8a66597_mdfy(r8a66597, val, 0, offset)
612
613static inline unsigned long get_syscfg_reg(int port)
614{
615 return port == 0 ? SYSCFG0 : SYSCFG1;
616}
617
618static inline unsigned long get_syssts_reg(int port)
619{
620 return port == 0 ? SYSSTS0 : SYSSTS1;
621}
622
623static inline unsigned long get_dvstctr_reg(int port)
624{
625 return port == 0 ? DVSTCTR0 : DVSTCTR1;
626}
627
628static inline unsigned long get_dmacfg_reg(int port)
629{
630 return port == 0 ? DMA0CFG : DMA1CFG;
631}
632
633static inline unsigned long get_intenb_reg(int port)
634{
635 return port == 0 ? INTENB1 : INTENB2;
636}
637
638static inline unsigned long get_intsts_reg(int port)
639{
640 return port == 0 ? INTSTS1 : INTSTS2;
641}
642
643static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
644{
645 unsigned long dvstctr_reg = get_dvstctr_reg(port);
646
647 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
648}
649
650static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
651 int power)
652{
653 unsigned long dvstctr_reg = get_dvstctr_reg(port);
654
655 if (power)
656 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
657 else
658 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
659}
660
661#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
662#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
663#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
664#define get_devadd_addr(address) (DEVADD0 + address * 2)
665
666#define enable_irq_ready(r8a66597, pipenum) \
667 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
668#define disable_irq_ready(r8a66597, pipenum) \
669 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
670#define enable_irq_empty(r8a66597, pipenum) \
671 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
672#define disable_irq_empty(r8a66597, pipenum) \
673 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
674#define enable_irq_nrdy(r8a66597, pipenum) \
675 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
676#define disable_irq_nrdy(r8a66597, pipenum) \
677 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
678
679#endif /* __R8A66597_H__ */
680