tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
6 * but this keeps the ISA-Bridge and slots alive.
7 *
8 */
9
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/hdreg.h>
15#include <linux/ide.h>
16#include <linux/init.h>
17
18#define DRV_NAME "slc90e66"
19
20static DEFINE_SPINLOCK(slc90e66_lock);
21
22static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
23{
24 ide_hwif_t *hwif = HWIF(drive);
25 struct pci_dev *dev = to_pci_dev(hwif->dev);
26 int is_slave = drive->dn & 1;
27 int master_port = hwif->channel ? 0x42 : 0x40;
28 int slave_port = 0x44;
29 unsigned long flags;
30 u16 master_data;
31 u8 slave_data;
32 int control = 0;
33 /* ISP RTC */
34 static const u8 timings[][2] = {
35 { 0, 0 },
36 { 0, 0 },
37 { 1, 0 },
38 { 2, 1 },
39 { 2, 3 }, };
40
41 spin_lock_irqsave(&slc90e66_lock, flags);
42 pci_read_config_word(dev, master_port, &master_data);
43
44 if (pio > 1)
45 control |= 1; /* Programmable timing on */
46 if (drive->media == ide_disk)
47 control |= 4; /* Prefetch, post write */
48 if (pio > 2)
49 control |= 2; /* IORDY */
50 if (is_slave) {
51 master_data |= 0x4000;
52 master_data &= ~0x0070;
53 if (pio > 1) {
54 /* Set PPE, IE and TIME */
55 master_data |= control << 4;
56 }
57 pci_read_config_byte(dev, slave_port, &slave_data);
58 slave_data &= hwif->channel ? 0x0f : 0xf0;
59 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
60 (hwif->channel ? 4 : 0);
61 } else {
62 master_data &= ~0x3307;
63 if (pio > 1) {
64 /* enable PPE, IE and TIME */
65 master_data |= control;
66 }
67 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
68 }
69 pci_write_config_word(dev, master_port, master_data);
70 if (is_slave)
71 pci_write_config_byte(dev, slave_port, slave_data);
72 spin_unlock_irqrestore(&slc90e66_lock, flags);
73}
74
75static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
76{
77 ide_hwif_t *hwif = HWIF(drive);
78 struct pci_dev *dev = to_pci_dev(hwif->dev);
79 u8 maslave = hwif->channel ? 0x42 : 0x40;
80 int sitre = 0, a_speed = 7 << (drive->dn * 4);
81 int u_speed = 0, u_flag = 1 << drive->dn;
82 u16 reg4042, reg44, reg48, reg4a;
83
84 pci_read_config_word(dev, maslave, ®4042);
85 sitre = (reg4042 & 0x4000) ? 1 : 0;
86 pci_read_config_word(dev, 0x44, ®44);
87 pci_read_config_word(dev, 0x48, ®48);
88 pci_read_config_word(dev, 0x4a, ®4a);
89
90 if (speed >= XFER_UDMA_0) {
91 u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
92
93 if (!(reg48 & u_flag))
94 pci_write_config_word(dev, 0x48, reg48|u_flag);
95 /* FIXME: (reg4a & a_speed) ? */
96 if ((reg4a & u_speed) != u_speed) {
97 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
98 pci_read_config_word(dev, 0x4a, ®4a);
99 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
100 }
101 } else {
102 const u8 mwdma_to_pio[] = { 0, 3, 4 };
103 u8 pio;
104
105 if (reg48 & u_flag)
106 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
107 if (reg4a & a_speed)
108 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
109
110 if (speed >= XFER_MW_DMA_0)
111 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
112 else
113 pio = 2; /* only SWDMA2 is allowed */
114
115 slc90e66_set_pio_mode(drive, pio);
116 }
117}
118
119static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
120{
121 struct pci_dev *dev = to_pci_dev(hwif->dev);
122 u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
123
124 pci_read_config_byte(dev, 0x47, ®47);
125
126 /* bit[0(1)]: 0:80, 1:40 */
127 return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
128}
129
130static const struct ide_port_ops slc90e66_port_ops = {
131 .set_pio_mode = slc90e66_set_pio_mode,
132 .set_dma_mode = slc90e66_set_dma_mode,
133 .cable_detect = slc90e66_cable_detect,
134};
135
136static const struct ide_port_info slc90e66_chipset __devinitdata = {
137 .name = DRV_NAME,
138 .enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
139 .port_ops = &slc90e66_port_ops,
140 .host_flags = IDE_HFLAG_LEGACY_IRQS,
141 .pio_mask = ATA_PIO4,
142 .swdma_mask = ATA_SWDMA2_ONLY,
143 .mwdma_mask = ATA_MWDMA12_ONLY,
144 .udma_mask = ATA_UDMA4,
145};
146
147static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
148{
149 return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
150}
151
152static const struct pci_device_id slc90e66_pci_tbl[] = {
153 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
154 { 0, },
155};
156MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
157
158static struct pci_driver driver = {
159 .name = "SLC90e66_IDE",
160 .id_table = slc90e66_pci_tbl,
161 .probe = slc90e66_init_one,
162 .remove = ide_pci_remove,
163};
164
165static int __init slc90e66_ide_init(void)
166{
167 return ide_pci_register_driver(&driver);
168}
169
170static void __exit slc90e66_ide_exit(void)
171{
172 pci_unregister_driver(&driver);
173}
174
175module_init(slc90e66_ide_init);
176module_exit(slc90e66_ide_exit);
177
178MODULE_AUTHOR("Andre Hedrick");
179MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
180MODULE_LICENSE("GPL");